sys/arch/sgimips/mace/pcireg_mace.h

   1 /*      $NetBSD: pcireg_mace.h,v 1.1.4.3 2004/09/21 13:21:20 skrll Exp $        */
   2
   3 /*
   4  * Copyright (c) 2000 Soren S. Jorvang
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *          This product includes software developed for the
  18  *          NetBSD Project.  See http://www.NetBSD.org/ for
  19  *          information about NetBSD.
  20  * 4. The name of the author may not be used to endorse or promote products
  21  *    derived from this software without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 #define MACEPCI_ERROR_ADDR      0x0000
  36 #define MACEPCI_ERROR_FLAGS     0x0004
  37 #define FLAGS_66MHZ_CAP         0x00000001
  38 #define FLAGS_BACKTOBACK_CAP    0x00000002
  39 #define FLAGS_DEVSEL_FAST       0x00000000
  40 #define FLAGS_DEVSEL_MEDIUM     0x00000004
  41 #define FLAGS_DEVSEL_SLOW       0x00000008
  42 #define FLAGS_DEVSEL_MASK       0x0000000c
  43 #define FLAGS_SIG_TARGET_ABORT  0x00000010
  44 #define FLAGS_ADDR_RETRY_ERROR  0x00010000
  45 #define FLAGS_ADDR_DATA_PARITY  0x00020000
  46 #define FLAGS_ADDR_TARGET_ABORT 0x00040000
  47 #define FLAGS_ADDR_MASTER_ABORT 0x00080000
  48 #define FLAGS_ADDR_CONFIG_SPACE 0x00100000
  49 #define FLAGS_ADDR_MEMORY_SPACE 0x00200000
  50 #define FLAGS_SIG_SYSTEM_ERROR  0x00400000
  51 #define FLAGS_READ_BUF_OVERRUN  0x00800000
  52 #define FLAGS_PARITY_ERROR      0x01000000
  53 #define FLAGS_INTERRUPT_TEST    0x02000000
  54 #define FLAGS_SYSTEM_ERROR      0x04000000
  55 #define FLAGS_ILL_HOST_TRANSACT 0x08000000
  56 #define FLAGS_RETRY_ERROR       0x10000000
  57 #define FLAGS_DATA_PARITY       0x20000000
  58 #define FLAGS_TARGET_ABORT      0x40000000
  59 #define FLAGS_MASTER_ABORT      0x80000000
  60 #define MACEPCI_CONTROL         0x0008
  61 #define CONTROL_INT0_SCSI0      0x00000001
  62 #define CONTROL_INT1_SCSI1      0x00000002
  63 #define CONTROL_INT2_SLOT0_A    0x00000004
  64 #define CONTROL_INT3_SLOT1_A    0x00000008
  65 #define CONTROL_INT4_SLOT2_A    0x00000010
  66 #define CONTROL_INT5_SLOTS_BCD  0x00000020
  67 #define CONTROL_INT6_SLOTS_CDB  0x00000040
  68 #define CONTROL_INT7_SLOTS_DBC  0x00000080
  69 #define CONTROL_INT_MASK        0x000000ff
  70 #define CONTROL_SERR_N_ENABLE   0x00000100
  71 #define CONTROL_REQ_N6_PRIORITY 0x00000200              /* Revision 1 only */
  72 #define CONTROL_PARITY_ERROR    0x00000400
  73 #define CONTROL_MRM_READAHEAD   0x00000800
  74 #define CONTROL_REG_N3_PRIORITY 0x00001000
  75 #define CONTROL_REG_N4_PRIORITY 0x00002000
  76 #define CONTROL_REG_N5_PRIORITY 0x00004000
  77 #define CONTROL_PARKING_ON_LAST 0x00008000
  78 #define CONTROL_INT0_INVAL_BUFS 0x00010000
  79 #define CONTROL_INT1_INVAL_BUFS 0x00020000
  80 #define CONTROL_INT2_INVAL_BUFS 0x00040000
  81 #define CONTROL_INT3_INVAL_BUFS 0x00080000
  82 #define CONTROL_INT4_INVAL_BUFS 0x00100000
  83 #define CONTROL_INT5_INVAL_BUFS 0x00200000
  84 #define CONTROL_INT6_INVAL_BUFS 0x00400000
  85 #define CONTROL_INT7_INVAL_BUFS 0x00800000
  86 #define CONTROL_OVERRUN_COND_I  0x01000000
  87 #define CONTROL_PARITY_ERROR_I  0x02000000
  88 #define CONTROL_SYSTEM_ERROR_I  0x04000000
  89 #define CONTROL_ILL_TRANS_I     0x08000000
  90 #define CONTROL_RETRY_ERROR_I   0x10000000
  91 #define CONTROL_DATA_PARITY_I   0x20000000
  92 #define CONTROL_TARGET_ABORT_I  0x40000000
  93 #define CONTROL_MASTER_ABORT_I  0x80000000
  94 #define MACEPCI_REVISION        0x000c
  95 #define MACEPCI_WBFLUSH         0x000c
  96 #define MACEPCI_CONFIG_ADDR     0x0cf8
  97 #define MACEPCI_CONFIG_DATA     0x0cfc
  98
  99 #define MACEPCI_MEM_KSEG        0x1a000000
 100 #define MACEPCI_IO_KSEG         0x18000000
 101 #define MACEPCI_MEM_XKSEG       0x000000280000000
 102 #define MACEPCI_IO_XKSEG        0x000000100000000