sys/arch/sun3/dev/esp.c

   1 /*      $NetBSD: esp.c,v 1.27 2008/04/13 04:55:53 tsutsui Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jeremy Cooper and Gordon W. Ross
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * "Front end" glue for the ncr53c9x chip, formerly known as the
  34  * Emulex SCSI Processor (ESP) which is what we actually have.
  35  */
  36
  37 #include <sys/cdefs.h>
  38 __KERNEL_RCSID(0, "$NetBSD: esp.c,v 1.27 2008/04/13 04:55:53 tsutsui Exp $");
  39
  40 #include <sys/types.h>
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/kernel.h>
  44 #include <sys/errno.h>
  45 #include <sys/device.h>
  46 #include <sys/buf.h>
  47
  48 #include <dev/scsipi/scsi_all.h>
  49 #include <dev/scsipi/scsipi_all.h>
  50 #include <dev/scsipi/scsiconf.h>
  51 #include <dev/scsipi/scsi_message.h>
  52
  53 #include <machine/autoconf.h>
  54 #include <machine/bus.h>
  55
  56 #include <dev/ic/ncr53c9xreg.h>
  57 #include <dev/ic/ncr53c9xvar.h>
  58
  59 #include <sun3/dev/dmareg.h>
  60 #include <sun3/dev/dmavar.h>
  61
  62 #define ESP_REG_SIZE    (12*4)
  63
  64 struct esp_softc {
  65         struct ncr53c9x_softc sc_ncr53c9x;      /* glue to MI code */
  66         bus_space_tag_t sc_bst;                 /* bus space tag */
  67         bus_space_handle_t sc_bsh;              /* bus space handle */
  68         struct dma_softc *sc_dma;               /* pointer to my dma */
  69 };
  70
  71 static int      espmatch(device_t, cfdata_t, void *);
  72 static void     espattach(device_t, device_t, void *);
  73
  74 CFATTACH_DECL_NEW(esp, sizeof(struct esp_softc),
  75     espmatch, espattach, NULL, NULL);
  76
  77 /*
  78  * Functions and the switch for the MI code.
  79  */
  80 static uint8_t  esp_read_reg(struct ncr53c9x_softc *, int);
  81 static void     esp_write_reg(struct ncr53c9x_softc *, int, uint8_t);
  82 static int      esp_dma_isintr(struct ncr53c9x_softc *);
  83 static void     esp_dma_reset(struct ncr53c9x_softc *);
  84 static int      esp_dma_intr(struct ncr53c9x_softc *);
  85 static int      esp_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *,
  86                     int, size_t *);
  87 static void     esp_dma_go(struct ncr53c9x_softc *);
  88 static void     esp_dma_stop(struct ncr53c9x_softc *);
  89 static int      esp_dma_isactive(struct ncr53c9x_softc *);
  90
  91 static struct ncr53c9x_glue esp_glue = {
  92         esp_read_reg,
  93         esp_write_reg,
  94         esp_dma_isintr,
  95         esp_dma_reset,
  96         esp_dma_intr,
  97         esp_dma_setup,
  98         esp_dma_go,
  99         esp_dma_stop,
 100         esp_dma_isactive,
 101         NULL,                   /* gl_clear_latched_intr */
 102 };
 103
 104 static int
 105 espmatch(device_t parent, struct cfdata *cf, void *aux)
 106 {
 107         struct confargs *ca = aux;
 108
 109         /*
 110          * Check for the esp registers.
 111          */
 112         if (bus_peek(ca->ca_bustype,
 113             ca->ca_paddr + (NCR_STAT * 4), 1) == -1)
 114                 return 0;
 115
 116         /* If default ipl, fill it in. */
 117         if (ca->ca_intpri == -1)
 118                 ca->ca_intpri = 2;
 119
 120         return 1;
 121 }
 122
 123 static void
 124 espattach(device_t parent, device_t self, void *aux)
 125 {
 126         struct esp_softc *esc = device_private(self);
 127         struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
 128         struct confargs *ca = aux;
 129
 130         /*
 131          * Set up glue for MI code early; we use some of it here.
 132          */
 133         sc->sc_dev = self;
 134         sc->sc_glue = &esp_glue;
 135
 136         /*
 137          * Map the ESP registers.
 138          */
 139         esc->sc_bst = ca->ca_bustag;
 140         if (bus_space_map(esc->sc_bst, ca->ca_paddr, ESP_REG_SIZE, 0,
 141             &esc->sc_bsh) != 0) {
 142                 aprint_error(": can't map register\n");
 143                 return;
 144         }
 145
 146         /* Other settings */
 147         sc->sc_id = 7;
 148         sc->sc_freq = 20;       /* The 3/80 esp runs at 20 MHz */
 149
 150         /*
 151          * Hook up the DMA driver.
 152          */
 153         esc->sc_dma = espdmafind(device_unit(self));
 154         esc->sc_dma->sc_client = sc; /* Point back to us */
 155
 156         /*
 157          * XXX More of this should be in ncr53c9x_attach(), but
 158          * XXX should we really poke around the chip that much in
 159          * XXX the MI code?  Think about this more...
 160          */
 161
 162         /*
 163          * It is necessary to try to load the 2nd config register here,
 164          * to find out what rev the esp chip is, else the ncr53c9x_reset
 165          * will not set up the defaults correctly.
 166          */
 167         sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
 168         sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
 169         sc->sc_cfg3 = NCRCFG3_CDB;
 170         NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
 171
 172         if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
 173             (NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
 174                 sc->sc_rev = NCR_VARIANT_ESP100;
 175         } else {
 176                 sc->sc_cfg2 = NCRCFG2_SCSI2;
 177                 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
 178                 sc->sc_cfg3 = 0;
 179                 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
 180                 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
 181                 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
 182                 if (NCR_READ_REG(sc, NCR_CFG3) !=
 183                     (NCRCFG3_CDB | NCRCFG3_FCLK)) {
 184                         sc->sc_rev = NCR_VARIANT_ESP100A;
 185                 } else {
 186                         /* NCRCFG2_FE enables > 64K transfers */
 187                         sc->sc_cfg2 |= NCRCFG2_FE;
 188                         sc->sc_cfg3 = 0;
 189                         NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
 190                         sc->sc_rev = NCR_VARIANT_ESP200;
 191                 }
 192         }
 193
 194         /*
 195          * XXX minsync and maxxfer _should_ be set up in MI code,
 196          * XXX but it appears to have some dependency on what sort
 197          * XXX of DMA we're hooked up to, etc.
 198          */
 199
 200         /*
 201          * This is the value used to start sync negotiations
 202          * Note that the NCR register "SYNCTP" is programmed
 203          * in "clocks per byte", and has a minimum value of 4.
 204          * The SCSI period used in negotiation is one-fourth
 205          * of the time (in nanoseconds) needed to transfer one byte.
 206          * Since the chip's clock is given in MHz, we have the following
 207          * formula: 4 * period = (1000 / freq) * 4
 208          */
 209         sc->sc_minsync = 1000 / sc->sc_freq;
 210
 211         /*
 212          * Alas, we must now modify the value a bit, because it's
 213          * only valid when can switch on FASTCLK and FASTSCSI bits
 214          * in config register 3...
 215          */
 216         switch (sc->sc_rev) {
 217         case NCR_VARIANT_ESP100:
 218                 sc->sc_maxxfer = 64 * 1024;
 219                 sc->sc_minsync = 0;     /* No synch on old chip? */
 220                 break;
 221
 222         case NCR_VARIANT_ESP100A:
 223                 sc->sc_maxxfer = 64 * 1024;
 224                 /* Min clocks/byte is 5 */
 225                 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
 226                 break;
 227
 228         case NCR_VARIANT_ESP200:
 229                 sc->sc_maxxfer = 16 * 1024 * 1024;
 230                 /* XXX - do actually set FAST* bits */
 231                 break;
 232         }
 233
 234         /* and the interuppts */
 235         isr_add_autovect(ncr53c9x_intr, sc, ca->ca_intpri);
 236         evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
 237             device_xname(self), "intr");
 238
 239         /* Do the common parts of attachment. */
 240         sc->sc_adapter.adapt_minphys = minphys;
 241         sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
 242         ncr53c9x_attach(sc);
 243
 244         /* Turn on target selection using the `dma' method */
 245         sc->sc_features |= NCR_F_DMASELECT;
 246 }
 247
 248
 249 /*
 250  * Glue functions.
 251  */
 252
 253 uint8_t
 254 esp_read_reg(struct ncr53c9x_softc *sc, int reg)
 255 {
 256         struct esp_softc *esc = (struct esp_softc *)sc;
 257
 258         return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4);
 259 }
 260
 261 void
 262 esp_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
 263 {
 264         struct esp_softc *esc = (struct esp_softc *)sc;
 265
 266         bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4, val);
 267 }
 268
 269 int
 270 esp_dma_isintr(struct ncr53c9x_softc *sc)
 271 {
 272         struct esp_softc *esc = (struct esp_softc *)sc;
 273
 274         return DMA_ISINTR(esc->sc_dma);
 275 }
 276
 277 void
 278 esp_dma_reset(struct ncr53c9x_softc *sc)
 279 {
 280         struct esp_softc *esc = (struct esp_softc *)sc;
 281
 282         dma_reset(esc->sc_dma);
 283 }
 284
 285 int
 286 esp_dma_intr(struct ncr53c9x_softc *sc)
 287 {
 288         struct esp_softc *esc = (struct esp_softc *)sc;
 289
 290         return espdmaintr(esc->sc_dma);
 291 }
 292
 293 int
 294 esp_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
 295     int datain, size_t *dmasize)
 296 {
 297         struct esp_softc *esc = (struct esp_softc *)sc;
 298
 299         return dma_setup(esc->sc_dma, addr, len, datain, dmasize);
 300 }
 301
 302 void
 303 esp_dma_go(struct ncr53c9x_softc *sc)
 304 {
 305         struct esp_softc *esc = (struct esp_softc *)sc;
 306
 307         DMA_GO(esc->sc_dma);
 308 }
 309
 310 void
 311 esp_dma_stop(struct ncr53c9x_softc *sc)
 312 {
 313         struct esp_softc *esc = (struct esp_softc *)sc;
 314
 315         DMA_STOP(esc->sc_dma);
 316 }
 317
 318 int
 319 esp_dma_isactive(struct ncr53c9x_softc *sc)
 320 {
 321         struct esp_softc *esc = (struct esp_softc *)sc;
 322
 323         return DMA_ISACTIVE(esc->sc_dma);
 324 }