sys/arch/sun3/sun3x/pmap_pvt.h

   1 /*      $NetBSD: pmap_pvt.h,v 1.14 2006/09/20 09:35:57 tsutsui Exp $    */
   2
   3 /*-
   4  * Copyright (c) 1996 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jeremy Cooper.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _SUN3X_PMAPPVT_H
  33 #define _SUN3X_PMAPPVT_H
  34
  35 #include "opt_pmap_debug.h"
  36
  37 /*************************** TMGR STRUCTURES ***************************
  38  * The sun3x 'tmgr' structures contain MMU tables and additional       *
  39  * information about their current usage and availability.             *
  40  ***********************************************************************/
  41 typedef struct a_tmgr_struct a_tmgr_t;
  42 typedef struct b_tmgr_struct b_tmgr_t;
  43 typedef struct c_tmgr_struct c_tmgr_t;
  44
  45 /* A level A table manager contains a pointer to an MMU table of long
  46  * format table descriptors (an 'A' table), a pointer to the pmap
  47  * currently using the table, and the number of wired and active entries
  48  * it contains.
  49  */
  50 struct a_tmgr_struct {
  51         pmap_t          at_parent; /* pmap currently using this table    */
  52         mmu_long_dte_t  *at_dtbl;  /* the MMU table being managed        */
  53         uint8_t         at_wcnt;   /* no. of wired entries in this table */
  54         uint8_t         at_ecnt;   /* no. of valid entries in this table */
  55         uint16_t        at_dum1;   /* structure padding                  */
  56         TAILQ_ENTRY(a_tmgr_struct) at_link;  /* list linker              */
  57 };
  58
  59 /* A level B table manager contains a pointer to an MMU table of
  60  * short format table descriptors (a 'B' table), a pointer to the level
  61  * A table manager currently using it, the index of this B table
  62  * within that parent A table, and the number of wired and active entries
  63  * it currently contains.
  64  */
  65 struct b_tmgr_struct {
  66         a_tmgr_t        *bt_parent; /* Parent 'A' table manager         */
  67         mmu_short_dte_t *bt_dtbl;   /* the MMU table being managed      */
  68         uint8_t         bt_pidx;    /* this table's index in the parent */
  69         uint8_t         bt_wcnt;    /* no. of wired entries in table    */
  70         uint8_t         bt_ecnt;    /* no. of valid entries in table    */
  71         uint8_t         bt_dum1;    /* structure padding                */
  72         TAILQ_ENTRY(b_tmgr_struct) bt_link; /* list linker              */
  73 };
  74
  75 /* A level 'C' table manager consists of pointer to an MMU table of short
  76  * format page descriptors (a 'C' table), a pointer to the level B table
  77  * manager currently using it, and the number of wired and active pages
  78  * it currently contains.
  79  *
  80  * Additionally, the table manager contains a pointer to the pmap
  81  * that is currently using it and the starting virtual address of the
  82  * range that the MMU table manages.  These two items can be obtained
  83  * through the traversal of other table manager structures, but having
  84  * them close at hand helps speed up operations in the PV system.
  85  */
  86 struct c_tmgr_struct {
  87         b_tmgr_t        *ct_parent; /* Parent 'B' table manager         */
  88         mmu_short_pte_t *ct_dtbl;   /* the MMU table being managed      */
  89         uint8_t         ct_pidx;    /* this table's index in the parent */
  90         uint8_t         ct_wcnt;    /* no. of wired entries in table    */
  91         uint8_t         ct_ecnt;    /* no. of valid entries in table    */
  92         uint8_t         ct_dum1;    /* structure padding                */
  93         TAILQ_ENTRY(c_tmgr_struct) ct_link; /* list linker              */
  94 #define MMU_SHORT_PTE_WIRED     MMU_SHORT_PTE_UN1
  95 #define MMU_PTE_WIRED           ((*pte)->attr.raw & MMU_SHORT_PTE_WIRED)
  96         pmap_t          ct_pmap;    /* pmap currently using this table  */
  97         vaddr_t         ct_va;      /* starting va that this table maps */
  98 };
  99
 100 /* The Mach VM code requires that the pmap module be able to apply
 101  * several different operations on all page descriptors that map to a
 102  * given physical address.  A few of these are:
 103  *  + invalidate all mappings to a page.
 104  *  + change the type of protection on all mappings to a page.
 105  *  + determine if a physical page has been written to
 106  *  + determine if a physical page has been accessed (read from)
 107  *  + clear such information
 108  * The collection of structures and tables which we used to make this
 109  * possible is known as the 'Physical to Virtual' or 'PV' system.
 110  *
 111  * Every physical page of memory managed by the virtual memory system
 112  * will have a structure which describes whether or not it has been
 113  * modified or referenced, and contains a list of page descriptors that
 114  * are currently mapped to it (if any).  This array of structures is
 115  * known as the 'PV' list.
 116  *
 117  ** Old PV Element structure
 118  * To keep a list of page descriptors currently using the page, another
 119  * structure had to be invented.  Its sole purpose is to be a link in
 120  * a chain of such structures.  No other information is contained within
 121  * the structure however!  The other piece of information it holds is
 122  * hidden within its address.  By maintaining a one-to-one correspondence
 123  * of page descriptors in the system and such structures, this address can
 124  * readily be translated into its associated page descriptor by using a
 125  * simple macro.  This bizzare structure is simply known as a 'PV
 126  * Element', or 'pve' for short.
 127  *
 128  ** New PV Element structure
 129  * To keep a list of page descriptors currently using the page, another
 130  * structure had to be invented.  Its sole purpose is to indicate the index
 131  * of the next PTE currently referencing the page.  By maintaining a one-to-
 132  * one correspondence of page descriptors in the system and such structures,
 133  * this same index is also the index of the next PV element, which describes
 134  * the index of yet another page mapped to the same address and so on.  The
 135  * special index 'PVE_EOL' is used to represent the end of the list.
 136  */
 137 struct pv_struct {
 138         u_short pv_idx;         /* Index of PTE using this page */
 139         u_short pv_flags;       /* Physical page status flags */
 140 #define PV_FLAGS_USED   MMU_SHORT_PTE_USED
 141 #define PV_FLAGS_MDFY   MMU_SHORT_PTE_M
 142 };
 143 typedef struct pv_struct pv_t;
 144
 145 struct pv_elem_struct {
 146         u_short pve_next;
 147 #define PVE_EOL 0xffff          /* End-of-list marker */
 148 };
 149 typedef struct pv_elem_struct pv_elem_t;
 150
 151 /* Physical memory on the 3/80 is not contiguous.  The ROM Monitor
 152  * provides us with a linked list of memory segments describing each
 153  * segment with its base address and its size.
 154  */
 155 struct pmap_physmem_struct {
 156         paddr_t         pmem_start;  /* Starting physical address      */
 157         paddr_t         pmem_end;    /* First byte outside of range    */
 158         int             pmem_pvbase; /* Offset within the pv list      */
 159         struct pmap_physmem_struct *pmem_next; /* Next block of memory */
 160 };
 161
 162 /* These are defined in pmap.c */
 163 extern struct pmap_physmem_struct avail_mem[];
 164
 165 #endif /* _SUN3X_PMAPPVT_H */