sys/arch/x68k/dev/dmacvar.h

   1 /*      $NetBSD: dmacvar.h,v 1.9 2008/06/25 08:14:59 isaki Exp $        */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Minoura Makoto.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 /*
  33  * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k.
  34  */
  35
  36 #include <dev/ic/mc68450reg.h>
  37 #include <machine/bus.h>
  38
  39 #define DMAC_MAPSIZE 64
  40
  41 typedef int (*dmac_intr_handler_t)(void *);
  42
  43 /*
  44  * Structure that describes a single transfer.
  45  */
  46 struct dmac_channel_stat;
  47 struct dmac_dma_xfer {
  48         struct dmac_channel_stat *dx_channel;
  49         bus_dmamap_t    dx_dmamap;      /* dmamap tag */
  50         bus_dma_tag_t   dx_tag;         /* dma tag for the transfer */
  51         int             dx_ocr;         /* direction */
  52         int             dx_scr;         /* SCR value */
  53         void            *dx_device;     /* (initial) device address */
  54 #ifdef DMAC_ARRAYCHAIN
  55         struct dmac_sg_array *dx_array; /* DMAC array chain */
  56         int             dx_done;
  57 #endif
  58         int             dx_nextoff;     /* for continued operation */
  59         int             dx_nextsize;
  60 };
  61
  62 /*
  63  * Struct that holds the channel status.
  64  * Embedded in the device softc for each channel.
  65  */
  66 struct dmac_channel_stat {
  67         int                     ch_channel; /* channel number */
  68         char                    ch_name[8]; /* user device name */
  69         bus_space_handle_t      ch_bht; /* bus_space handle */
  70         int                     ch_dcr; /* device description */
  71         int                     ch_ocr; /* operation size, request mode */
  72         int                     ch_normalv; /* normal interrupt vector */
  73         int                     ch_errorv; /* error interrupt vector */
  74         dmac_intr_handler_t     ch_normal; /* normal interrupt handler */
  75         dmac_intr_handler_t     ch_error; /* error interrupt handler */
  76         void                    *ch_normalarg;
  77         void                    *ch_errorarg;
  78         struct dmac_dma_xfer    ch_xfer;
  79         struct dmac_sg_array    *ch_map; /* transfer map for arraychain mode */
  80         bus_dma_segment_t       ch_seg[1];
  81         struct dmac_softc       *ch_softc; /* device softc link */
  82 };
  83
  84 /*
  85  * DMAC softc
  86  */
  87 struct dmac_softc {
  88         device_t                sc_dev;
  89
  90         bus_space_tag_t         sc_bst;
  91         bus_space_handle_t      sc_bht;
  92
  93         struct dmac_channel_stat sc_channels[DMAC_NCHAN];
  94 };
  95
  96
  97 #define DMAC_ADDR       0xe84000
  98
  99 #define DMAC_MAXSEGSZ   0xff00
 100 #define DMAC_BOUNDARY   0
 101
 102 struct dmac_channel_stat *dmac_alloc_channel(device_t, int, const char *,
 103         int, dmac_intr_handler_t, void *, int, dmac_intr_handler_t, void *);
 104                 /* ch, name, normalv, normal, errorv, error */
 105 int dmac_free_channel(device_t, int, void *);
 106                 /* ch, channel */
 107 struct dmac_dma_xfer *dmac_alloc_xfer(struct dmac_channel_stat *,
 108         bus_dma_tag_t, bus_dmamap_t);
 109 int dmac_load_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
 110
 111 int dmac_start_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
 112 int dmac_start_xfer_offset(struct dmac_softc *, struct dmac_dma_xfer *,
 113         u_int, u_int);
 114 int dmac_abort_xfer(struct dmac_softc *, struct dmac_dma_xfer *);
 115 /* Compatibility function: alloc, fill defaults, load */
 116 struct dmac_dma_xfer *dmac_prepare_xfer(struct dmac_channel_stat *,
 117         bus_dma_tag_t, bus_dmamap_t, int, int, void *);
 118         /* chan, dmat, map, dir, sequence, dar */