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Expand PMF_FN_* macros.
[netbsd-mini2440.git] / sys / dev / usb / ehci.c
blob93d32ccbbdfac5c878264686034c008a8345ad94
1 /* $NetBSD: ehci.c,v 1.164 2009/11/14 17:06:12 uebayasi Exp $ */
2
3 /*
4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and
9 * Jeremy Morse (jeremy.morse@gmail.com).
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
35 *
36 * The EHCI 1.0 spec can be found at
37 * http://www.intel.com/technology/usb/spec.htm
38 * and the USB 2.0 spec at
39 * http://www.usb.org/developers/docs/
40 *
41 */
42
43 /*
44 * TODO:
45 * 1) hold off explorations by companion controllers until ehci has started.
46 *
47 * 2) The hub driver needs to handle and schedule the transaction translator,
48 * to assign place in frame where different devices get to go. See chapter
49 * on hubs in USB 2.0 for details.
50 *
51 * 3) Command failures are not recovered correctly.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.164 2009/11/14 17:06:12 uebayasi Exp $");
56
57 #include "ohci.h"
58 #include "uhci.h"
59
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/malloc.h>
64 #include <sys/device.h>
65 #include <sys/select.h>
66 #include <sys/proc.h>
67 #include <sys/queue.h>
68 #include <sys/mutex.h>
69 #include <sys/bus.h>
70
71 #include <machine/endian.h>
72
73 #include <dev/usb/usb.h>
74 #include <dev/usb/usbdi.h>
75 #include <dev/usb/usbdivar.h>
76 #include <dev/usb/usb_mem.h>
77 #include <dev/usb/usb_quirks.h>
78
79 #include <dev/usb/ehcireg.h>
80 #include <dev/usb/ehcivar.h>
81 #include <dev/usb/usbroothub_subr.h>
82
83 #ifdef EHCI_DEBUG
84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0)
85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0)
86 int ehcidebug = 0;
87 #else
88 #define DPRINTF(x)
89 #define DPRINTFN(n,x)
90 #endif
91
92 struct ehci_pipe {
93 struct usbd_pipe pipe;
94 int nexttoggle;
95
96 ehci_soft_qh_t *sqh;
97 union {
98 ehci_soft_qtd_t *qtd;
99 /* ehci_soft_itd_t *itd; */
100 } tail;
101 union {
102 /* Control pipe */
103 struct {
104 usb_dma_t reqdma;
105 u_int length;
106 } ctl;
107 /* Interrupt pipe */
108 struct {
109 u_int length;
110 } intr;
111 /* Bulk pipe */
112 struct {
113 u_int length;
114 } bulk;
115 /* Iso pipe */
116 struct {
117 u_int next_frame;
118 u_int cur_xfers;
119 } isoc;
120 } u;
121 };
122
123 Static usbd_status ehci_open(usbd_pipe_handle);
124 Static void ehci_poll(struct usbd_bus *);
125 Static void ehci_softintr(void *);
126 Static int ehci_intr1(ehci_softc_t *);
127 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
128 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
129 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *);
130 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *);
131 Static void ehci_idone(struct ehci_xfer *);
132 Static void ehci_timeout(void *);
133 Static void ehci_timeout_task(void *);
134 Static void ehci_intrlist_timeout(void *);
135
136 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
137 Static void ehci_freem(struct usbd_bus *, usb_dma_t *);
138
139 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
140 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
141
142 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
143 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
144 Static void ehci_root_ctrl_abort(usbd_xfer_handle);
145 Static void ehci_root_ctrl_close(usbd_pipe_handle);
146 Static void ehci_root_ctrl_done(usbd_xfer_handle);
147
148 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
149 Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
150 Static void ehci_root_intr_abort(usbd_xfer_handle);
151 Static void ehci_root_intr_close(usbd_pipe_handle);
152 Static void ehci_root_intr_done(usbd_xfer_handle);
153
154 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
155 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
156 Static void ehci_device_ctrl_abort(usbd_xfer_handle);
157 Static void ehci_device_ctrl_close(usbd_pipe_handle);
158 Static void ehci_device_ctrl_done(usbd_xfer_handle);
159
160 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
161 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
162 Static void ehci_device_bulk_abort(usbd_xfer_handle);
163 Static void ehci_device_bulk_close(usbd_pipe_handle);
164 Static void ehci_device_bulk_done(usbd_xfer_handle);
165
166 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
167 Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
168 Static void ehci_device_intr_abort(usbd_xfer_handle);
169 Static void ehci_device_intr_close(usbd_pipe_handle);
170 Static void ehci_device_intr_done(usbd_xfer_handle);
171
172 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
173 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
174 Static void ehci_device_isoc_abort(usbd_xfer_handle);
175 Static void ehci_device_isoc_close(usbd_pipe_handle);
176 Static void ehci_device_isoc_done(usbd_xfer_handle);
177
178 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
179 Static void ehci_noop(usbd_pipe_handle pipe);
180
181 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
182 Static void ehci_disown(ehci_softc_t *, int, int);
183
184 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
185 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
186
187 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
188 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
189 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
190 ehci_softc_t *, int, int, usbd_xfer_handle,
191 ehci_soft_qtd_t **, ehci_soft_qtd_t **);
192 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
193 ehci_soft_qtd_t *);
194
195 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc);
196 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd);
197 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc,
198 struct ehci_xfer *exfer);
199 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer,
200 usbd_status status);
201
202 Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
203
204 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
205 int ival);
206
207 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
208 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
209 ehci_soft_qh_t *);
210 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
211 Static void ehci_sync_hc(ehci_softc_t *);
212
213 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
214 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
215
216 #ifdef EHCI_DEBUG
217 Static void ehci_dump_regs(ehci_softc_t *);
218 void ehci_dump(void);
219 Static ehci_softc_t *theehci;
220 Static void ehci_dump_link(ehci_link_t, int);
221 Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
222 Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
223 Static void ehci_dump_qtd(ehci_qtd_t *);
224 Static void ehci_dump_sqh(ehci_soft_qh_t *);
225 #if notyet
226 Static void ehci_dump_sitd(struct ehci_soft_itd *itd);
227 Static void ehci_dump_itd(struct ehci_soft_itd *);
228 #endif
229 #ifdef DIAGNOSTIC
230 Static void ehci_dump_exfer(struct ehci_xfer *);
231 #endif
232 #endif
233
234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
235
236 #define EHCI_INTR_ENDPT 1
237
238 #define ehci_add_intr_list(sc, ex) \
239 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext);
240 #define ehci_del_intr_list(sc, ex) \
241 do { \
242 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \
243 (ex)->inext.tqe_prev = NULL; \
244 } while (0)
245 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL)
246
247 Static const struct usbd_bus_methods ehci_bus_methods = {
248 ehci_open,
249 ehci_softintr,
250 ehci_poll,
251 ehci_allocm,
252 ehci_freem,
253 ehci_allocx,
254 ehci_freex,
255 };
256
257 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = {
258 ehci_root_ctrl_transfer,
259 ehci_root_ctrl_start,
260 ehci_root_ctrl_abort,
261 ehci_root_ctrl_close,
262 ehci_noop,
263 ehci_root_ctrl_done,
264 };
265
266 Static const struct usbd_pipe_methods ehci_root_intr_methods = {
267 ehci_root_intr_transfer,
268 ehci_root_intr_start,
269 ehci_root_intr_abort,
270 ehci_root_intr_close,
271 ehci_noop,
272 ehci_root_intr_done,
273 };
274
275 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = {
276 ehci_device_ctrl_transfer,
277 ehci_device_ctrl_start,
278 ehci_device_ctrl_abort,
279 ehci_device_ctrl_close,
280 ehci_noop,
281 ehci_device_ctrl_done,
282 };
283
284 Static const struct usbd_pipe_methods ehci_device_intr_methods = {
285 ehci_device_intr_transfer,
286 ehci_device_intr_start,
287 ehci_device_intr_abort,
288 ehci_device_intr_close,
289 ehci_device_clear_toggle,
290 ehci_device_intr_done,
291 };
292
293 Static const struct usbd_pipe_methods ehci_device_bulk_methods = {
294 ehci_device_bulk_transfer,
295 ehci_device_bulk_start,
296 ehci_device_bulk_abort,
297 ehci_device_bulk_close,
298 ehci_device_clear_toggle,
299 ehci_device_bulk_done,
300 };
301
302 Static const struct usbd_pipe_methods ehci_device_isoc_methods = {
303 ehci_device_isoc_transfer,
304 ehci_device_isoc_start,
305 ehci_device_isoc_abort,
306 ehci_device_isoc_close,
307 ehci_noop,
308 ehci_device_isoc_done,
309 };
310
311 static const uint8_t revbits[EHCI_MAX_POLLRATE] = {
312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78,
313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c,
314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a,
315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e,
316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79,
317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d,
318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b,
319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f,
320 };
321
322 usbd_status
323 ehci_init(ehci_softc_t *sc)
324 {
325 u_int32_t vers, sparams, cparams, hcr;
326 u_int i;
327 usbd_status err;
328 ehci_soft_qh_t *sqh;
329 u_int ncomp;
330
331 DPRINTF(("ehci_init: start\n"));
332 #ifdef EHCI_DEBUG
333 theehci = sc;
334 #endif
335
336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
337
338 vers = EREAD2(sc, EHCI_HCIVERSION);
339 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev),
340 vers >> 8, vers & 0xff);
341
342 sparams = EREAD4(sc, EHCI_HCSPARAMS);
343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
345 ncomp = EHCI_HCS_N_CC(sparams);
346 if (ncomp != sc->sc_ncomp) {
347 aprint_verbose("%s: wrong number of companions (%d != %d)\n",
348 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp);
349 #if NOHCI == 0 || NUHCI == 0
350 aprint_error("%s: ohci or uhci probably not configured\n",
351 device_xname(sc->sc_dev));
352 #endif
353 if (ncomp < sc->sc_ncomp)
354 sc->sc_ncomp = ncomp;
355 }
356 if (sc->sc_ncomp > 0) {
357 aprint_normal("%s: companion controller%s, %d port%s each:",
358 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "",
359 EHCI_HCS_N_PCC(sparams),
360 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
361 for (i = 0; i < sc->sc_ncomp; i++)
362 aprint_normal(" %s", device_xname(sc->sc_comps[i]));
363 aprint_normal("\n");
364 }
365 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
366 cparams = EREAD4(sc, EHCI_HCCPARAMS);
367 DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
368 sc->sc_hasppc = EHCI_HCS_PPC(sparams);
369
370 if (EHCI_HCC_64BIT(cparams)) {
371 /* MUST clear segment register if 64 bit capable. */
372 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
373 }
374
375 sc->sc_bus.usbrev = USBREV_2_0;
376
377 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag,
378 USB_MEM_RESERVE);
379
380 /* Reset the controller */
381 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev)));
382 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
383 usb_delay_ms(&sc->sc_bus, 1);
384 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
385 for (i = 0; i < 100; i++) {
386 usb_delay_ms(&sc->sc_bus, 1);
387 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
388 if (!hcr)
389 break;
390 }
391 if (hcr) {
392 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev));
393 return (USBD_IOERROR);
394 }
395
396 /* XXX need proper intr scheduling */
397 sc->sc_rand = 96;
398
399 /* frame list size at default, read back what we got and use that */
400 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
401 case 0: sc->sc_flsize = 1024; break;
402 case 1: sc->sc_flsize = 512; break;
403 case 2: sc->sc_flsize = 256; break;
404 case 3: return (USBD_IOERROR);
405 }
406 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
407 EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
408 if (err)
409 return (err);
410 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize));
411 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
412
413 for (i = 0; i < sc->sc_flsize; i++) {
414 sc->sc_flist[i] = EHCI_NULL;
415 }
416
417 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
418
419 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *),
420 M_USB, M_NOWAIT | M_ZERO);
421 if (sc->sc_softitds == NULL)
422 return ENOMEM;
423 LIST_INIT(&sc->sc_freeitds);
424 TAILQ_INIT(&sc->sc_intrhead);
425 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB);
426
427 /* Set up the bus struct. */
428 sc->sc_bus.methods = &ehci_bus_methods;
429 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
430
431 sc->sc_eintrs = EHCI_NORMAL_INTRS;
432
433 /*
434 * Allocate the interrupt dummy QHs. These are arranged to give poll
435 * intervals that are powers of 2 times 1ms.
436 */
437 for (i = 0; i < EHCI_INTRQHS; i++) {
438 sqh = ehci_alloc_sqh(sc);
439 if (sqh == NULL) {
440 err = USBD_NOMEM;
441 goto bad1;
442 }
443 sc->sc_islots[i].sqh = sqh;
444 }
445 for (i = 0; i < EHCI_INTRQHS; i++) {
446 sqh = sc->sc_islots[i].sqh;
447 if (i == 0) {
448 /* The last (1ms) QH terminates. */
449 sqh->qh.qh_link = EHCI_NULL;
450 sqh->next = NULL;
451 } else {
452 /* Otherwise the next QH has half the poll interval */
453 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
454 sqh->qh.qh_link = htole32(sqh->next->physaddr |
455 EHCI_LINK_QH);
456 }
457 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
458 sqh->qh.qh_curqtd = EHCI_NULL;
459 sqh->next = NULL;
460 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
461 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
462 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
463 sqh->sqtd = NULL;
464 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
465 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
466 }
467 /* Point the frame list at the last level (128ms). */
468 for (i = 0; i < sc->sc_flsize; i++) {
469 int j;
470
471 j = (i & ~(EHCI_MAX_POLLRATE-1)) |
472 revbits[i & (EHCI_MAX_POLLRATE-1)];
473 sc->sc_flist[j] = htole32(EHCI_LINK_QH |
474 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1,
475 i)].sqh->physaddr);
476 }
477 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t),
478 BUS_DMASYNC_PREWRITE);
479
480 /* Allocate dummy QH that starts the async list. */
481 sqh = ehci_alloc_sqh(sc);
482 if (sqh == NULL) {
483 err = USBD_NOMEM;
484 goto bad1;
485 }
486 /* Fill the QH */
487 sqh->qh.qh_endp =
488 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
489 sqh->qh.qh_link =
490 htole32(sqh->physaddr | EHCI_LINK_QH);
491 sqh->qh.qh_curqtd = EHCI_NULL;
492 sqh->next = NULL;
493 /* Fill the overlay qTD */
494 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
495 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
496 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
497 sqh->sqtd = NULL;
498 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
499 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
500 #ifdef EHCI_DEBUG
501 if (ehcidebug) {
502 ehci_dump_sqh(sqh);
503 }
504 #endif
505
506 /* Point to async list */
507 sc->sc_async_head = sqh;
508 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
509
510 callout_init(&(sc->sc_tmo_intrlist), 0);
511
512 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE);
513
514 /* Turn on controller */
515 EOWRITE4(sc, EHCI_USBCMD,
516 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */
517 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
518 EHCI_CMD_ASE |
519 EHCI_CMD_PSE |
520 EHCI_CMD_RS);
521
522 /* Take over port ownership */
523 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
524
525 for (i = 0; i < 100; i++) {
526 usb_delay_ms(&sc->sc_bus, 1);
527 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
528 if (!hcr)
529 break;
530 }
531 if (hcr) {
532 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev));
533 return (USBD_IOERROR);
534 }
535
536 /* Enable interrupts */
537 DPRINTFN(1,("ehci_init: enabling\n"));
538 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
539
540 return (USBD_NORMAL_COMPLETION);
541
542 #if 0
543 bad2:
544 ehci_free_sqh(sc, sc->sc_async_head);
545 #endif
546 bad1:
547 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
548 return (err);
549 }
550
551 int
552 ehci_intr(void *v)
553 {
554 ehci_softc_t *sc = v;
555
556 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev))
557 return (0);
558
559 /* If we get an interrupt while polling, then just ignore it. */
560 if (sc->sc_bus.use_polling) {
561 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
562
563 if (intrs)
564 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
565 #ifdef DIAGNOSTIC
566 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n"));
567 #endif
568 return (0);
569 }
570
571 return (ehci_intr1(sc));
572 }
573
574 Static int
575 ehci_intr1(ehci_softc_t *sc)
576 {
577 u_int32_t intrs, eintrs;
578
579 DPRINTFN(20,("ehci_intr1: enter\n"));
580
581 /* In case the interrupt occurs before initialization has completed. */
582 if (sc == NULL) {
583 #ifdef DIAGNOSTIC
584 printf("ehci_intr1: sc == NULL\n");
585 #endif
586 return (0);
587 }
588
589 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
590 if (!intrs)
591 return (0);
592
593 eintrs = intrs & sc->sc_eintrs;
594 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
595 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
596 (u_int)eintrs));
597 if (!eintrs)
598 return (0);
599
600 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
601 sc->sc_bus.intr_context++;
602 sc->sc_bus.no_intrs++;
603 if (eintrs & EHCI_STS_IAA) {
604 DPRINTF(("ehci_intr1: door bell\n"));
605 wakeup(&sc->sc_async_head);
606 eintrs &= ~EHCI_STS_IAA;
607 }
608 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
609 DPRINTFN(5,("ehci_intr1: %s %s\n",
610 eintrs & EHCI_STS_INT ? "INT" : "",
611 eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
612 usb_schedsoftintr(&sc->sc_bus);
613 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
614 }
615 if (eintrs & EHCI_STS_HSE) {
616 printf("%s: unrecoverable error, controller halted\n",
617 device_xname(sc->sc_dev));
618 /* XXX what else */
619 }
620 if (eintrs & EHCI_STS_PCD) {
621 ehci_pcd(sc, sc->sc_intrxfer);
622 eintrs &= ~EHCI_STS_PCD;
623 }
624
625 sc->sc_bus.intr_context--;
626
627 if (eintrs != 0) {
628 /* Block unprocessed interrupts. */
629 sc->sc_eintrs &= ~eintrs;
630 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
631 printf("%s: blocking intrs 0x%x\n",
632 device_xname(sc->sc_dev), eintrs);
633 }
634
635 return (1);
636 }
637
638
639 Static void
640 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
641 {
642 usbd_pipe_handle pipe;
643 u_char *p;
644 int i, m;
645
646 if (xfer == NULL) {
647 /* Just ignore the change. */
648 return;
649 }
650
651 pipe = xfer->pipe;
652
653 p = KERNADDR(&xfer->dmabuf, 0);
654 m = min(sc->sc_noport, xfer->length * 8 - 1);
655 memset(p, 0, xfer->length);
656 for (i = 1; i <= m; i++) {
657 /* Pick out CHANGE bits from the status reg. */
658 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
659 p[i/8] |= 1 << (i%8);
660 }
661 DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
662 xfer->actlen = xfer->length;
663 xfer->status = USBD_NORMAL_COMPLETION;
664
665 usb_transfer_complete(xfer);
666 }
667
668 Static void
669 ehci_softintr(void *v)
670 {
671 struct usbd_bus *bus = v;
672 ehci_softc_t *sc = bus->hci_private;
673 struct ehci_xfer *ex, *nextex;
674
675 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev),
676 sc->sc_bus.intr_context));
677
678 sc->sc_bus.intr_context++;
679
680 /*
681 * The only explanation I can think of for why EHCI is as brain dead
682 * as UHCI interrupt-wise is that Intel was involved in both.
683 * An interrupt just tells us that something is done, we have no
684 * clue what, so we need to scan through all active transfers. :-(
685 */
686 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
687 nextex = TAILQ_NEXT(ex, inext);
688 ehci_check_intr(sc, ex);
689 }
690
691 /* Schedule a callout to catch any dropped transactions. */
692 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
693 !TAILQ_EMPTY(&sc->sc_intrhead))
694 callout_reset(&(sc->sc_tmo_intrlist),
695 (hz), (ehci_intrlist_timeout), (sc));
696
697 #ifdef USB_USE_SOFTINTR
698 if (sc->sc_softwake) {
699 sc->sc_softwake = 0;
700 wakeup(&sc->sc_softwake);
701 }
702 #endif /* USB_USE_SOFTINTR */
703
704 sc->sc_bus.intr_context--;
705 }
706
707 /* Check for an interrupt. */
708 Static void
709 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
710 {
711 int attr;
712
713 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
714
715 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes;
716 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS)
717 ehci_check_itd_intr(sc, ex);
718 else
719 ehci_check_qh_intr(sc, ex);
720
721 return;
722 }
723
724 Static void
725 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
726 {
727 ehci_soft_qtd_t *sqtd, *lsqtd;
728 __uint32_t status;
729
730 if (ex->sqtdstart == NULL) {
731 printf("ehci_check_qh_intr: not valid sqtd\n");
732 return;
733 }
734
735 lsqtd = ex->sqtdend;
736 #ifdef DIAGNOSTIC
737 if (lsqtd == NULL) {
738 printf("ehci_check_qh_intr: lsqtd==0\n");
739 return;
740 }
741 #endif
742 /*
743 * If the last TD is still active we need to check whether there
744 * is a an error somewhere in the middle, or whether there was a
745 * short packet (SPD and not ACTIVE).
746 */
747 usb_syncmem(&lsqtd->dma,
748 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
749 sizeof(lsqtd->qtd.qtd_status),
750 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
751 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
752 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
753 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
754 usb_syncmem(&sqtd->dma,
755 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
756 sizeof(sqtd->qtd.qtd_status),
757 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
758 status = le32toh(sqtd->qtd.qtd_status);
759 usb_syncmem(&sqtd->dma,
760 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
761 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
762 /* If there's an active QTD the xfer isn't done. */
763 if (status & EHCI_QTD_ACTIVE)
764 break;
765 /* Any kind of error makes the xfer done. */
766 if (status & EHCI_QTD_HALTED)
767 goto done;
768 /* We want short packets, and it is short: it's done */
769 if (EHCI_QTD_GET_BYTES(status) != 0)
770 goto done;
771 }
772 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
773 ex, ex->sqtdstart));
774 usb_syncmem(&lsqtd->dma,
775 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status),
776 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD);
777 return;
778 }
779 done:
780 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
781 callout_stop(&(ex->xfer.timeout_handle));
782 ehci_idone(ex);
783 }
784
785 Static void
786 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) {
787 ehci_soft_itd_t *itd;
788 int i;
789
790 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue))
791 return;
792
793 if (ex->itdstart == NULL) {
794 printf("ehci_check_itd_intr: not valid itd\n");
795 return;
796 }
797
798 itd = ex->itdend;
799 #ifdef DIAGNOSTIC
800 if (itd == NULL) {
801 printf("ehci_check_itd_intr: itdend == 0\n");
802 return;
803 }
804 #endif
805
806 /*
807 * check no active transfers in last itd, meaning we're finished
808 */
809
810 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl),
811 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
812 BUS_DMASYNC_POSTREAD);
813
814 for (i = 0; i < 8; i++) {
815 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE)
816 break;
817 }
818
819 if (i == 8) {
820 goto done; /* All 8 descriptors inactive, it's done */
821 }
822
823 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex,
824 ex->itdstart));
825 return;
826 done:
827 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex));
828 callout_stop(&(ex->xfer.timeout_handle));
829 ehci_idone(ex);
830 }
831
832 Static void
833 ehci_idone(struct ehci_xfer *ex)
834 {
835 usbd_xfer_handle xfer = &ex->xfer;
836 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
837 ehci_soft_qtd_t *sqtd, *lsqtd;
838 u_int32_t status = 0, nstatus = 0;
839 int actlen;
840
841 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
842 #ifdef DIAGNOSTIC
843 {
844 int s = splhigh();
845 if (ex->isdone) {
846 splx(s);
847 #ifdef EHCI_DEBUG
848 printf("ehci_idone: ex is done!\n ");
849 ehci_dump_exfer(ex);
850 #else
851 printf("ehci_idone: ex=%p is done!\n", ex);
852 #endif
853 return;
854 }
855 ex->isdone = 1;
856 splx(s);
857 }
858 #endif
859 if (xfer->status == USBD_CANCELLED ||
860 xfer->status == USBD_TIMEOUT) {
861 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
862 return;
863 }
864
865 #ifdef EHCI_DEBUG
866 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
867 if (ehcidebug > 10)
868 ehci_dump_sqtds(ex->sqtdstart);
869 #endif
870
871 /* The transfer is done, compute actual length and status. */
872
873 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)
874 == UE_ISOCHRONOUS) {
875 /* Isoc transfer */
876 struct ehci_soft_itd *itd;
877 int i, nframes, len, uframes;
878
879 nframes = 0;
880 actlen = 0;
881
882 switch (xfer->pipe->endpoint->edesc->bInterval) {
883 case 0:
884 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n");
885 case 1: uframes = 1; break;
886 case 2: uframes = 2; break;
887 case 3: uframes = 4; break;
888 default: uframes = 8; break;
889 }
890
891 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) {
892 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl),
893 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE |
894 BUS_DMASYNC_POSTREAD);
895
896 for (i = 0; i < 8; i += uframes) {
897 /* XXX - driver didn't fill in the frame full
898 * of uframes. This leads to scheduling
899 * inefficiencies, but working around
900 * this doubles complexity of tracking
901 * an xfer.
902 */
903 if (nframes >= xfer->nframes)
904 break;
905
906 status = le32toh(itd->itd.itd_ctl[i]);
907 len = EHCI_ITD_GET_LEN(status);
908 if (EHCI_ITD_GET_STATUS(status) != 0)
909 len = 0; /*No valid data on error*/
910
911 xfer->frlengths[nframes++] = len;
912 actlen += len;
913 }
914
915 if (nframes >= xfer->nframes)
916 break;
917 }
918
919 xfer->actlen = actlen;
920 xfer->status = USBD_NORMAL_COMPLETION;
921 goto end;
922 }
923
924 /* Continue processing xfers using queue heads */
925
926 lsqtd = ex->sqtdend;
927 actlen = 0;
928 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) {
929 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd),
930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
931 nstatus = le32toh(sqtd->qtd.qtd_status);
932 if (nstatus & EHCI_QTD_ACTIVE)
933 break;
934
935 status = nstatus;
936 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
937 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
938 }
939
940
941 /*
942 * If there are left over TDs we need to update the toggle.
943 * The default pipe doesn't need it since control transfers
944 * start the toggle at 0 every time.
945 * For a short transfer we need to update the toggle for the missing
946 * packets within the qTD.
947 */
948 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) &&
949 xfer->pipe->device->default_pipe != xfer->pipe) {
950 DPRINTFN(2, ("ehci_idone: need toggle update "
951 "status=%08x nstatus=%08x\n", status, nstatus));
952 #if 0
953 ehci_dump_sqh(epipe->sqh);
954 ehci_dump_sqtds(ex->sqtdstart);
955 #endif
956 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus);
957 }
958
959 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n",
960 xfer->length, actlen, status));
961 xfer->actlen = actlen;
962 if (status & EHCI_QTD_HALTED) {
963 #ifdef EHCI_DEBUG
964 char sbuf[128];
965
966 snprintb(sbuf, sizeof(sbuf),
967 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE",
968 (u_int32_t)status);
969
970 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, "
971 "status 0x%s\n",
972 xfer->pipe->device->address,
973 xfer->pipe->endpoint->edesc->bEndpointAddress,
974 sbuf));
975 if (ehcidebug > 2) {
976 ehci_dump_sqh(epipe->sqh);
977 ehci_dump_sqtds(ex->sqtdstart);
978 }
979 #endif
980 /* low&full speed has an extra error flag */
981 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) !=
982 EHCI_QH_SPEED_HIGH)
983 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE;
984 else
985 status &= EHCI_QTD_STATERRS;
986 if (status == 0) /* no other errors means a stall */ {
987 xfer->status = USBD_STALLED;
988 } else {
989 xfer->status = USBD_IOERROR; /* more info XXX */
990 }
991 /* XXX need to reset TT on missed microframe */
992 if (status & EHCI_QTD_MISSEDMICRO) {
993 ehci_softc_t *sc =
994 xfer->pipe->device->bus->hci_private;
995
996 printf("%s: missed microframe, TT reset not "
997 "implemented, hub might be inoperational\n",
998 device_xname(sc->sc_dev));
999 }
1000 } else {
1001 xfer->status = USBD_NORMAL_COMPLETION;
1002 }
1003
1004 end:
1005 /* XXX transfer_complete memcpys out transfer data (for in endpoints)
1006 * during this call, before methods->done is called: dma sync required
1007 * beforehand? */
1008 usb_transfer_complete(xfer);
1009 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
1010 }
1011
1012 /*
1013 * Wait here until controller claims to have an interrupt.
1014 * Then call ehci_intr and return. Use timeout to avoid waiting
1015 * too long.
1016 */
1017 Static void
1018 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
1019 {
1020 int timo;
1021 u_int32_t intrs;
1022
1023 xfer->status = USBD_IN_PROGRESS;
1024 for (timo = xfer->timeout; timo >= 0; timo--) {
1025 usb_delay_ms(&sc->sc_bus, 1);
1026 if (sc->sc_dying)
1027 break;
1028 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
1029 sc->sc_eintrs;
1030 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
1031 #ifdef EHCI_DEBUG
1032 if (ehcidebug > 15)
1033 ehci_dump_regs(sc);
1034 #endif
1035 if (intrs) {
1036 ehci_intr1(sc);
1037 if (xfer->status != USBD_IN_PROGRESS)
1038 return;
1039 }
1040 }
1041
1042 /* Timeout */
1043 DPRINTF(("ehci_waitintr: timeout\n"));
1044 xfer->status = USBD_TIMEOUT;
1045 usb_transfer_complete(xfer);
1046 /* XXX should free TD */
1047 }
1048
1049 Static void
1050 ehci_poll(struct usbd_bus *bus)
1051 {
1052 ehci_softc_t *sc = bus->hci_private;
1053 #ifdef EHCI_DEBUG
1054 static int last;
1055 int new;
1056 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1057 if (new != last) {
1058 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
1059 last = new;
1060 }
1061 #endif
1062
1063 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
1064 ehci_intr1(sc);
1065 }
1066
1067 void
1068 ehci_childdet(device_t self, device_t child)
1069 {
1070 struct ehci_softc *sc = device_private(self);
1071
1072 KASSERT(sc->sc_child == child);
1073 sc->sc_child = NULL;
1074 }
1075
1076 int
1077 ehci_detach(struct ehci_softc *sc, int flags)
1078 {
1079 int rv = 0;
1080
1081 if (sc->sc_child != NULL)
1082 rv = config_detach(sc->sc_child, flags);
1083
1084 if (rv != 0)
1085 return (rv);
1086
1087 callout_stop(&(sc->sc_tmo_intrlist));
1088
1089 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
1090
1091 /* XXX free other data structures XXX */
1092 mutex_destroy(&sc->sc_doorbell_lock);
1093 mutex_destroy(&sc->sc_intrhead_lock);
1094
1095 EOWRITE4(sc, EHCI_CONFIGFLAG, 0);
1096
1097 return (rv);
1098 }
1099
1100
1101 int
1102 ehci_activate(device_t self, enum devact act)
1103 {
1104 struct ehci_softc *sc = device_private(self);
1105
1106 switch (act) {
1107 case DVACT_DEACTIVATE:
1108 sc->sc_dying = 1;
1109 return 0;
1110 default:
1111 return EOPNOTSUPP;
1112 }
1113 }
1114
1115 /*
1116 * Handle suspend/resume.
1117 *
1118 * We need to switch to polling mode here, because this routine is
1119 * called from an interrupt context. This is all right since we
1120 * are almost suspended anyway.
1121 *
1122 * Note that this power handler isn't to be registered directly; the
1123 * bus glue needs to call out to it.
1124 */
1125 bool
1126 ehci_suspend(device_t dv, pmf_qual_t qual)
1127 {
1128 ehci_softc_t *sc = device_private(dv);
1129 int i, s;
1130 uint32_t cmd, hcr;
1131
1132 s = splhardusb();
1133
1134 sc->sc_bus.use_polling++;
1135
1136 for (i = 1; i <= sc->sc_noport; i++) {
1137 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1138 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE)
1139 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP);
1140 }
1141
1142 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
1143
1144 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
1145 EOWRITE4(sc, EHCI_USBCMD, cmd);
1146
1147 for (i = 0; i < 100; i++) {
1148 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS);
1149 if (hcr == 0)
1150 break;
1151
1152 usb_delay_ms(&sc->sc_bus, 1);
1153 }
1154 if (hcr != 0)
1155 printf("%s: reset timeout\n", device_xname(dv));
1156
1157 cmd &= ~EHCI_CMD_RS;
1158 EOWRITE4(sc, EHCI_USBCMD, cmd);
1159
1160 for (i = 0; i < 100; i++) {
1161 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1162 if (hcr == EHCI_STS_HCH)
1163 break;
1164
1165 usb_delay_ms(&sc->sc_bus, 1);
1166 }
1167 if (hcr != EHCI_STS_HCH)
1168 printf("%s: config timeout\n", device_xname(dv));
1169
1170 sc->sc_bus.use_polling--;
1171 splx(s);
1172
1173 return true;
1174 }
1175
1176 bool
1177 ehci_resume(device_t dv, pmf_qual_t qual)
1178 {
1179 ehci_softc_t *sc = device_private(dv);
1180 int i;
1181 uint32_t cmd, hcr;
1182
1183 /* restore things in case the bios sucks */
1184 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1185 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1186 EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1187 sc->sc_async_head->physaddr | EHCI_LINK_QH);
1188
1189 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE);
1190
1191 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1192
1193 hcr = 0;
1194 for (i = 1; i <= sc->sc_noport; i++) {
1195 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1196 if ((cmd & EHCI_PS_PO) == 0 &&
1197 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) {
1198 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR);
1199 hcr = 1;
1200 }
1201 }
1202
1203 if (hcr) {
1204 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1205
1206 for (i = 1; i <= sc->sc_noport; i++) {
1207 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR;
1208 if ((cmd & EHCI_PS_PO) == 0 &&
1209 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)
1210 EOWRITE4(sc, EHCI_PORTSC(i),
1211 cmd & ~EHCI_PS_FPR);
1212 }
1213 }
1214
1215 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1216 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1217
1218 for (i = 0; i < 100; i++) {
1219 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1220 if (hcr != EHCI_STS_HCH)
1221 break;
1222
1223 usb_delay_ms(&sc->sc_bus, 1);
1224 }
1225 if (hcr == EHCI_STS_HCH)
1226 printf("%s: config timeout\n", device_xname(dv));
1227
1228 return true;
1229 }
1230
1231 /*
1232 * Shut down the controller when the system is going down.
1233 */
1234 bool
1235 ehci_shutdown(device_t self, int flags)
1236 {
1237 ehci_softc_t *sc = device_private(self);
1238
1239 DPRINTF(("ehci_shutdown: stopping the HC\n"));
1240 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1241 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1242 return true;
1243 }
1244
1245 Static usbd_status
1246 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
1247 {
1248 struct ehci_softc *sc = bus->hci_private;
1249 usbd_status err;
1250
1251 err = usb_allocmem(&sc->sc_bus, size, 0, dma);
1252 if (err == USBD_NOMEM)
1253 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size);
1254 #ifdef EHCI_DEBUG
1255 if (err)
1256 printf("ehci_allocm: usb_allocmem()=%d\n", err);
1257 #endif
1258 return (err);
1259 }
1260
1261 Static void
1262 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
1263 {
1264 struct ehci_softc *sc = bus->hci_private;
1265
1266 if (dma->block->flags & USB_DMA_RESERVE) {
1267 usb_reserve_freem(&sc->sc_dma_reserve,
1268 dma);
1269 return;
1270 }
1271 usb_freemem(&sc->sc_bus, dma);
1272 }
1273
1274 Static usbd_xfer_handle
1275 ehci_allocx(struct usbd_bus *bus)
1276 {
1277 struct ehci_softc *sc = bus->hci_private;
1278 usbd_xfer_handle xfer;
1279
1280 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
1281 if (xfer != NULL) {
1282 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1283 #ifdef DIAGNOSTIC
1284 if (xfer->busy_free != XFER_FREE) {
1285 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer,
1286 xfer->busy_free);
1287 }
1288 #endif
1289 } else {
1290 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT);
1291 }
1292 if (xfer != NULL) {
1293 memset(xfer, 0, sizeof(struct ehci_xfer));
1294 #ifdef DIAGNOSTIC
1295 EXFER(xfer)->isdone = 1;
1296 xfer->busy_free = XFER_BUSY;
1297 #endif
1298 }
1299 return (xfer);
1300 }
1301
1302 Static void
1303 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1304 {
1305 struct ehci_softc *sc = bus->hci_private;
1306
1307 #ifdef DIAGNOSTIC
1308 if (xfer->busy_free != XFER_BUSY) {
1309 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1310 xfer->busy_free);
1311 }
1312 xfer->busy_free = XFER_FREE;
1313 if (!EXFER(xfer)->isdone) {
1314 printf("ehci_freex: !isdone\n");
1315 }
1316 #endif
1317 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1318 }
1319
1320 Static void
1321 ehci_device_clear_toggle(usbd_pipe_handle pipe)
1322 {
1323 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1324
1325 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1326 epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1327 #ifdef EHCI_DEBUG
1328 if (ehcidebug)
1329 usbd_dump_pipe(pipe);
1330 #endif
1331 epipe->nexttoggle = 0;
1332 }
1333
1334 Static void
1335 ehci_noop(usbd_pipe_handle pipe)
1336 {
1337 }
1338
1339 #ifdef EHCI_DEBUG
1340 Static void
1341 ehci_dump_regs(ehci_softc_t *sc)
1342 {
1343 int i;
1344 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1345 EOREAD4(sc, EHCI_USBCMD),
1346 EOREAD4(sc, EHCI_USBSTS),
1347 EOREAD4(sc, EHCI_USBINTR));
1348 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1349 EOREAD4(sc, EHCI_FRINDEX),
1350 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1351 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1352 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1353 for (i = 1; i <= sc->sc_noport; i++)
1354 printf("port %d status=0x%08x\n", i,
1355 EOREAD4(sc, EHCI_PORTSC(i)));
1356 }
1357
1358 /*
1359 * Unused function - this is meant to be called from a kernel
1360 * debugger.
1361 */
1362 void
1363 ehci_dump(void)
1364 {
1365 ehci_dump_regs(theehci);
1366 }
1367
1368 Static void
1369 ehci_dump_link(ehci_link_t link, int type)
1370 {
1371 link = le32toh(link);
1372 printf("0x%08x", link);
1373 if (link & EHCI_LINK_TERMINATE)
1374 printf("<T>");
1375 else {
1376 printf("<");
1377 if (type) {
1378 switch (EHCI_LINK_TYPE(link)) {
1379 case EHCI_LINK_ITD: printf("ITD"); break;
1380 case EHCI_LINK_QH: printf("QH"); break;
1381 case EHCI_LINK_SITD: printf("SITD"); break;
1382 case EHCI_LINK_FSTN: printf("FSTN"); break;
1383 }
1384 }
1385 printf(">");
1386 }
1387 }
1388
1389 Static void
1390 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1391 {
1392 int i;
1393 u_int32_t stop;
1394
1395 stop = 0;
1396 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1397 ehci_dump_sqtd(sqtd);
1398 usb_syncmem(&sqtd->dma,
1399 sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1400 sizeof(sqtd->qtd),
1401 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1402 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1403 usb_syncmem(&sqtd->dma,
1404 sqtd->offs + offsetof(ehci_qtd_t, qtd_next),
1405 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1406 }
1407 if (sqtd)
1408 printf("dump aborted, too many TDs\n");
1409 }
1410
1411 Static void
1412 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1413 {
1414 usb_syncmem(&sqtd->dma, sqtd->offs,
1415 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1416 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1417 ehci_dump_qtd(&sqtd->qtd);
1418 usb_syncmem(&sqtd->dma, sqtd->offs,
1419 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD);
1420 }
1421
1422 Static void
1423 ehci_dump_qtd(ehci_qtd_t *qtd)
1424 {
1425 u_int32_t s;
1426 char sbuf[128];
1427
1428 printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1429 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1430 printf("\n");
1431 s = le32toh(qtd->qtd_status);
1432 snprintb(sbuf, sizeof(sbuf),
1433 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1434 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s));
1435 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1436 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1437 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1438 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1439 EHCI_QTD_GET_PID(s), sbuf);
1440 for (s = 0; s < 5; s++)
1441 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1442 }
1443
1444 Static void
1445 ehci_dump_sqh(ehci_soft_qh_t *sqh)
1446 {
1447 ehci_qh_t *qh = &sqh->qh;
1448 u_int32_t endp, endphub;
1449
1450 usb_syncmem(&sqh->dma, sqh->offs,
1451 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1452 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1453 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1454 endp = le32toh(qh->qh_endp);
1455 printf(" endp=0x%08x\n", endp);
1456 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1457 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1458 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1459 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1460 printf(" mpl=0x%x ctl=%d nrl=%d\n",
1461 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1462 EHCI_QH_GET_NRL(endp));
1463 endphub = le32toh(qh->qh_endphub);
1464 printf(" endphub=0x%08x\n", endphub);
1465 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1466 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1467 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1468 EHCI_QH_GET_MULT(endphub));
1469 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1470 printf("Overlay qTD:\n");
1471 ehci_dump_qtd(&qh->qh_qtd);
1472 usb_syncmem(&sqh->dma, sqh->offs,
1473 sizeof(sqh->qh), BUS_DMASYNC_PREREAD);
1474 }
1475
1476 #if notyet
1477 Static void
1478 ehci_dump_itd(struct ehci_soft_itd *itd)
1479 {
1480 ehci_isoc_trans_t t;
1481 ehci_isoc_bufr_ptr_t b, b2, b3;
1482 int i;
1483
1484 printf("ITD: next phys=%X\n", itd->itd.itd_next);
1485
1486 for (i = 0; i < 8;i++) {
1487 t = le32toh(itd->itd.itd_ctl[i]);
1488 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i,
1489 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t),
1490 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t),
1491 EHCI_ITD_GET_OFFS(t));
1492 }
1493 printf("ITDbufr: ");
1494 for (i = 0; i < 7; i++)
1495 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])));
1496
1497 b = le32toh(itd->itd.itd_bufr[0]);
1498 b2 = le32toh(itd->itd.itd_bufr[1]);
1499 b3 = le32toh(itd->itd.itd_bufr[2]);
1500 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n",
1501 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2),
1502 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3));
1503 }
1504
1505 Static void
1506 ehci_dump_sitd(struct ehci_soft_itd *itd)
1507 {
1508 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n",
1509 itd, itd->u.frame_list.next, itd->u.frame_list.prev,
1510 itd->xfer_next, itd->physaddr, itd->slot);
1511 }
1512 #endif
1513
1514 #ifdef DIAGNOSTIC
1515 Static void
1516 ehci_dump_exfer(struct ehci_xfer *ex)
1517 {
1518 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone);
1519 }
1520 #endif
1521 #endif
1522
1523 Static usbd_status
1524 ehci_open(usbd_pipe_handle pipe)
1525 {
1526 usbd_device_handle dev = pipe->device;
1527 ehci_softc_t *sc = dev->bus->hci_private;
1528 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1529 u_int8_t addr = dev->address;
1530 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1531 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1532 ehci_soft_qh_t *sqh;
1533 usbd_status err;
1534 int s;
1535 int ival, speed, naks;
1536 int hshubaddr, hshubport;
1537
1538 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1539 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1540
1541 if (dev->myhsport) {
1542 hshubaddr = dev->myhsport->parent->address;
1543 hshubport = dev->myhsport->portno;
1544 } else {
1545 hshubaddr = 0;
1546 hshubport = 0;
1547 }
1548
1549 if (sc->sc_dying)
1550 return (USBD_IOERROR);
1551
1552 epipe->nexttoggle = 0;
1553
1554 if (addr == sc->sc_addr) {
1555 switch (ed->bEndpointAddress) {
1556 case USB_CONTROL_ENDPOINT:
1557 pipe->methods = &ehci_root_ctrl_methods;
1558 break;
1559 case UE_DIR_IN | EHCI_INTR_ENDPT:
1560 pipe->methods = &ehci_root_intr_methods;
1561 break;
1562 default:
1563 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n",
1564 ed->bEndpointAddress));
1565 return (USBD_INVAL);
1566 }
1567 return (USBD_NORMAL_COMPLETION);
1568 }
1569
1570 /* XXX All this stuff is only valid for async. */
1571 switch (dev->speed) {
1572 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1573 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1574 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1575 default: panic("ehci_open: bad device speed %d", dev->speed);
1576 }
1577 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1578 aprint_error_dev(sc->sc_dev, "error opening low/full speed "
1579 "isoc endpoint.\n");
1580 aprint_normal_dev(sc->sc_dev, "a low/full speed device is "
1581 "attached to a USB2 hub, and transaction translations are "
1582 "not yet supported.\n");
1583 aprint_normal_dev(sc->sc_dev, "reattach the device to the "
1584 "root hub instead.\n");
1585 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1586 hshubaddr, hshubport));
1587 return USBD_INVAL;
1588 }
1589
1590 naks = 8; /* XXX */
1591
1592 /* Allocate sqh for everything, save isoc xfers */
1593 if (xfertype != UE_ISOCHRONOUS) {
1594 sqh = ehci_alloc_sqh(sc);
1595 if (sqh == NULL)
1596 return (USBD_NOMEM);
1597 /* qh_link filled when the QH is added */
1598 sqh->qh.qh_endp = htole32(
1599 EHCI_QH_SET_ADDR(addr) |
1600 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1601 EHCI_QH_SET_EPS(speed) |
1602 EHCI_QH_DTC |
1603 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1604 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1605 EHCI_QH_CTL : 0) |
1606 EHCI_QH_SET_NRL(naks)
1607 );
1608 sqh->qh.qh_endphub = htole32(
1609 EHCI_QH_SET_MULT(1) |
1610 EHCI_QH_SET_HUBA(hshubaddr) |
1611 EHCI_QH_SET_PORT(hshubport) |
1612 EHCI_QH_SET_CMASK(0x08) | /* XXX */
1613 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0)
1614 );
1615 sqh->qh.qh_curqtd = EHCI_NULL;
1616 /* Fill the overlay qTD */
1617 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1618 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1619 sqh->qh.qh_qtd.qtd_status = htole32(0);
1620
1621 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1622 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1623 epipe->sqh = sqh;
1624 } else {
1625 sqh = NULL;
1626 } /*xfertype == UE_ISOC*/
1627
1628 switch (xfertype) {
1629 case UE_CONTROL:
1630 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1631 0, &epipe->u.ctl.reqdma);
1632 #ifdef EHCI_DEBUG
1633 if (err)
1634 printf("ehci_open: usb_allocmem()=%d\n", err);
1635 #endif
1636 if (err)
1637 goto bad;
1638 pipe->methods = &ehci_device_ctrl_methods;
1639 s = splusb();
1640 ehci_add_qh(sqh, sc->sc_async_head);
1641 splx(s);
1642 break;
1643 case UE_BULK:
1644 pipe->methods = &ehci_device_bulk_methods;
1645 s = splusb();
1646 ehci_add_qh(sqh, sc->sc_async_head);
1647 splx(s);
1648 break;
1649 case UE_INTERRUPT:
1650 pipe->methods = &ehci_device_intr_methods;
1651 ival = pipe->interval;
1652 if (ival == USBD_DEFAULT_INTERVAL) {
1653 if (speed == EHCI_QH_SPEED_HIGH) {
1654 if (ed->bInterval > 16) {
1655 /*
1656 * illegal with high-speed, but there
1657 * were documentation bugs in the spec,
1658 * so be generous
1659 */
1660 ival = 256;
1661 } else
1662 ival = (1 << (ed->bInterval - 1)) / 8;
1663 } else
1664 ival = ed->bInterval;
1665 }
1666 err = ehci_device_setintr(sc, sqh, ival);
1667 if (err)
1668 goto bad;
1669 break;
1670 case UE_ISOCHRONOUS:
1671 pipe->methods = &ehci_device_isoc_methods;
1672 if (ed->bInterval == 0 || ed->bInterval > 16) {
1673 printf("ehci: opening pipe with invalid bInterval\n");
1674 err = USBD_INVAL;
1675 goto bad;
1676 }
1677 if (UGETW(ed->wMaxPacketSize) == 0) {
1678 printf("ehci: zero length endpoint open request\n");
1679 err = USBD_INVAL;
1680 goto bad;
1681 }
1682 epipe->u.isoc.next_frame = 0;
1683 epipe->u.isoc.cur_xfers = 0;
1684 break;
1685 default:
1686 DPRINTF(("ehci: bad xfer type %d\n", xfertype));
1687 err = USBD_INVAL;
1688 goto bad;
1689 }
1690 return (USBD_NORMAL_COMPLETION);
1691
1692 bad:
1693 if (sqh != NULL)
1694 ehci_free_sqh(sc, sqh);
1695 return (err);
1696 }
1697
1698 /*
1699 * Add an ED to the schedule. Called at splusb().
1700 */
1701 Static void
1702 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1703 {
1704 SPLUSBCHECK;
1705
1706 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
1707 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE);
1708 sqh->next = head->next;
1709 sqh->qh.qh_link = head->qh.qh_link;
1710 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
1711 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE);
1712 head->next = sqh;
1713 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1714 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link),
1715 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE);
1716
1717 #ifdef EHCI_DEBUG
1718 if (ehcidebug > 5) {
1719 printf("ehci_add_qh:\n");
1720 ehci_dump_sqh(sqh);
1721 }
1722 #endif
1723 }
1724
1725 /*
1726 * Remove an ED from the schedule. Called at splusb().
1727 */
1728 Static void
1729 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1730 {
1731 ehci_soft_qh_t *p;
1732
1733 SPLUSBCHECK;
1734 /* XXX */
1735 for (p = head; p != NULL && p->next != sqh; p = p->next)
1736 ;
1737 if (p == NULL)
1738 panic("ehci_rem_qh: ED not found");
1739 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link),
1740 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE);
1741 p->next = sqh->next;
1742 p->qh.qh_link = sqh->qh.qh_link;
1743 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link),
1744 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE);
1745
1746 ehci_sync_hc(sc);
1747 }
1748
1749 Static void
1750 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1751 {
1752 int i;
1753 u_int32_t status;
1754
1755 /* Save toggle bit and ping status. */
1756 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1757 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1758 status = sqh->qh.qh_qtd.qtd_status &
1759 htole32(EHCI_QTD_TOGGLE_MASK |
1760 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
1761 /* Set HALTED to make hw leave it alone. */
1762 sqh->qh.qh_qtd.qtd_status =
1763 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
1764 usb_syncmem(&sqh->dma,
1765 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
1766 sizeof(sqh->qh.qh_qtd.qtd_status),
1767 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1768 sqh->qh.qh_curqtd = 0;
1769 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1770 sqh->qh.qh_qtd.qtd_altnext = 0;
1771 for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
1772 sqh->qh.qh_qtd.qtd_buffer[i] = 0;
1773 sqh->sqtd = sqtd;
1774 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh),
1775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1776 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
1777 sqh->qh.qh_qtd.qtd_status = status;
1778 usb_syncmem(&sqh->dma,
1779 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
1780 sizeof(sqh->qh.qh_qtd.qtd_status),
1781 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1782 }
1783
1784 /*
1785 * Ensure that the HC has released all references to the QH. We do this
1786 * by asking for a Async Advance Doorbell interrupt and then we wait for
1787 * the interrupt.
1788 * To make this easier we first obtain exclusive use of the doorbell.
1789 */
1790 Static void
1791 ehci_sync_hc(ehci_softc_t *sc)
1792 {
1793 int s, error;
1794
1795 if (sc->sc_dying) {
1796 DPRINTFN(2,("ehci_sync_hc: dying\n"));
1797 return;
1798 }
1799 DPRINTFN(2,("ehci_sync_hc: enter\n"));
1800 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */
1801 s = splhardusb();
1802 /* ask for doorbell */
1803 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1804 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1805 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1806 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */
1807 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1808 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1809 splx(s);
1810 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */
1811 #ifdef DIAGNOSTIC
1812 if (error)
1813 printf("ehci_sync_hc: tsleep() = %d\n", error);
1814 #endif
1815 DPRINTFN(2,("ehci_sync_hc: exit\n"));
1816 }
1817
1818 /*Call at splusb*/
1819 Static void
1820 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer)
1821 {
1822 struct ehci_soft_itd *itd, *prev;
1823
1824 prev = NULL;
1825
1826 if (exfer->itdstart == NULL || exfer->itdend == NULL)
1827 panic("ehci isoc xfer being freed, but with no itd chain\n");
1828
1829 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
1830 prev = itd->u.frame_list.prev;
1831 /* Unlink itd from hardware chain, or frame array */
1832 if (prev == NULL) { /* We're at the table head */
1833 sc->sc_softitds[itd->slot] = itd->u.frame_list.next;
1834 sc->sc_flist[itd->slot] = itd->itd.itd_next;
1835 usb_syncmem(&sc->sc_fldma,
1836 sizeof(ehci_link_t) * itd->slot,
1837 sizeof(ehci_link_t),
1838 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1839
1840 if (itd->u.frame_list.next != NULL)
1841 itd->u.frame_list.next->u.frame_list.prev = NULL;
1842 } else {
1843 /* XXX this part is untested... */
1844 prev->itd.itd_next = itd->itd.itd_next;
1845 usb_syncmem(&itd->dma,
1846 itd->offs + offsetof(ehci_itd_t, itd_next),
1847 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE);
1848
1849 prev->u.frame_list.next = itd->u.frame_list.next;
1850 if (itd->u.frame_list.next != NULL)
1851 itd->u.frame_list.next->u.frame_list.prev = prev;
1852 }
1853 }
1854
1855 prev = NULL;
1856 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
1857 if (prev != NULL)
1858 ehci_free_itd(sc, prev);
1859 prev = itd;
1860 }
1861 if (prev)
1862 ehci_free_itd(sc, prev);
1863 exfer->itdstart = NULL;
1864 exfer->itdend = NULL;
1865 }
1866
1867 /***********/
1868
1869 /*
1870 * Data structures and routines to emulate the root hub.
1871 */
1872 Static usb_device_descriptor_t ehci_devd = {
1873 USB_DEVICE_DESCRIPTOR_SIZE,
1874 UDESC_DEVICE, /* type */
1875 {0x00, 0x02}, /* USB version */
1876 UDCLASS_HUB, /* class */
1877 UDSUBCLASS_HUB, /* subclass */
1878 UDPROTO_HSHUBSTT, /* protocol */
1879 64, /* max packet */
1880 {0},{0},{0x00,0x01}, /* device id */
1881 1,2,0, /* string indicies */
1882 1 /* # of configurations */
1883 };
1884
1885 Static const usb_device_qualifier_t ehci_odevd = {
1886 USB_DEVICE_DESCRIPTOR_SIZE,
1887 UDESC_DEVICE_QUALIFIER, /* type */
1888 {0x00, 0x02}, /* USB version */
1889 UDCLASS_HUB, /* class */
1890 UDSUBCLASS_HUB, /* subclass */
1891 UDPROTO_FSHUB, /* protocol */
1892 64, /* max packet */
1893 1, /* # of configurations */
1894 0
1895 };
1896
1897 Static const usb_config_descriptor_t ehci_confd = {
1898 USB_CONFIG_DESCRIPTOR_SIZE,
1899 UDESC_CONFIG,
1900 {USB_CONFIG_DESCRIPTOR_SIZE +
1901 USB_INTERFACE_DESCRIPTOR_SIZE +
1902 USB_ENDPOINT_DESCRIPTOR_SIZE},
1903 1,
1904 1,
1905 0,
1906 UC_ATTR_MBO | UC_SELF_POWERED,
1907 0 /* max power */
1908 };
1909
1910 Static const usb_interface_descriptor_t ehci_ifcd = {
1911 USB_INTERFACE_DESCRIPTOR_SIZE,
1912 UDESC_INTERFACE,
1913 0,
1914 0,
1915 1,
1916 UICLASS_HUB,
1917 UISUBCLASS_HUB,
1918 UIPROTO_HSHUBSTT,
1919 0
1920 };
1921
1922 Static const usb_endpoint_descriptor_t ehci_endpd = {
1923 USB_ENDPOINT_DESCRIPTOR_SIZE,
1924 UDESC_ENDPOINT,
1925 UE_DIR_IN | EHCI_INTR_ENDPT,
1926 UE_INTERRUPT,
1927 {8, 0}, /* max packet */
1928 12
1929 };
1930
1931 Static const usb_hub_descriptor_t ehci_hubd = {
1932 USB_HUB_DESCRIPTOR_SIZE,
1933 UDESC_HUB,
1934 0,
1935 {0,0},
1936 0,
1937 0,
1938 {""},
1939 {""},
1940 };
1941
1942 /*
1943 * Simulate a hardware hub by handling all the necessary requests.
1944 */
1945 Static usbd_status
1946 ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1947 {
1948 usbd_status err;
1949
1950 /* Insert last in queue. */
1951 err = usb_insert_transfer(xfer);
1952 if (err)
1953 return (err);
1954
1955 /* Pipe isn't running, start first */
1956 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1957 }
1958
1959 Static usbd_status
1960 ehci_root_ctrl_start(usbd_xfer_handle xfer)
1961 {
1962 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1963 usb_device_request_t *req;
1964 void *buf = NULL;
1965 int port, i;
1966 int s, len, value, index, l, totlen = 0;
1967 usb_port_status_t ps;
1968 usb_hub_descriptor_t hubd;
1969 usbd_status err;
1970 u_int32_t v;
1971
1972 if (sc->sc_dying)
1973 return (USBD_IOERROR);
1974
1975 #ifdef DIAGNOSTIC
1976 if (!(xfer->rqflags & URQ_REQUEST))
1977 /* XXX panic */
1978 return (USBD_INVAL);
1979 #endif
1980 req = &xfer->request;
1981
1982 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
1983 req->bmRequestType, req->bRequest));
1984
1985 len = UGETW(req->wLength);
1986 value = UGETW(req->wValue);
1987 index = UGETW(req->wIndex);
1988
1989 if (len != 0)
1990 buf = KERNADDR(&xfer->dmabuf, 0);
1991
1992 #define C(x,y) ((x) | ((y) << 8))
1993 switch(C(req->bRequest, req->bmRequestType)) {
1994 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1995 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1996 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1997 /*
1998 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1999 * for the integrated root hub.
2000 */
2001 break;
2002 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2003 if (len > 0) {
2004 *(u_int8_t *)buf = sc->sc_conf;
2005 totlen = 1;
2006 }
2007 break;
2008 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2009 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
2010 if (len == 0)
2011 break;
2012 switch(value >> 8) {
2013 case UDESC_DEVICE:
2014 if ((value & 0xff) != 0) {
2015 err = USBD_IOERROR;
2016 goto ret;
2017 }
2018 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2019 USETW(ehci_devd.idVendor, sc->sc_id_vendor);
2020 memcpy(buf, &ehci_devd, l);
2021 break;
2022 /*
2023 * We can't really operate at another speed, but the spec says
2024 * we need this descriptor.
2025 */
2026 case UDESC_DEVICE_QUALIFIER:
2027 if ((value & 0xff) != 0) {
2028 err = USBD_IOERROR;
2029 goto ret;
2030 }
2031 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2032 memcpy(buf, &ehci_odevd, l);
2033 break;
2034 /*
2035 * We can't really operate at another speed, but the spec says
2036 * we need this descriptor.
2037 */
2038 case UDESC_OTHER_SPEED_CONFIGURATION:
2039 case UDESC_CONFIG:
2040 if ((value & 0xff) != 0) {
2041 err = USBD_IOERROR;
2042 goto ret;
2043 }
2044 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
2045 memcpy(buf, &ehci_confd, l);
2046 ((usb_config_descriptor_t *)buf)->bDescriptorType =
2047 value >> 8;
2048 buf = (char *)buf + l;
2049 len -= l;
2050 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
2051 totlen += l;
2052 memcpy(buf, &ehci_ifcd, l);
2053 buf = (char *)buf + l;
2054 len -= l;
2055 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
2056 totlen += l;
2057 memcpy(buf, &ehci_endpd, l);
2058 break;
2059 case UDESC_STRING:
2060 #define sd ((usb_string_descriptor_t *)buf)
2061 switch (value & 0xff) {
2062 case 0: /* Language table */
2063 totlen = usb_makelangtbl(sd, len);
2064 break;
2065 case 1: /* Vendor */
2066 totlen = usb_makestrdesc(sd, len,
2067 sc->sc_vendor);
2068 break;
2069 case 2: /* Product */
2070 totlen = usb_makestrdesc(sd, len,
2071 "EHCI root hub");
2072 break;
2073 }
2074 #undef sd
2075 break;
2076 default:
2077 err = USBD_IOERROR;
2078 goto ret;
2079 }
2080 break;
2081 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2082 if (len > 0) {
2083 *(u_int8_t *)buf = 0;
2084 totlen = 1;
2085 }
2086 break;
2087 case C(UR_GET_STATUS, UT_READ_DEVICE):
2088 if (len > 1) {
2089 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
2090 totlen = 2;
2091 }
2092 break;
2093 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2094 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2095 if (len > 1) {
2096 USETW(((usb_status_t *)buf)->wStatus, 0);
2097 totlen = 2;
2098 }
2099 break;
2100 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2101 if (value >= USB_MAX_DEVICES) {
2102 err = USBD_IOERROR;
2103 goto ret;
2104 }
2105 sc->sc_addr = value;
2106 break;
2107 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2108 if (value != 0 && value != 1) {
2109 err = USBD_IOERROR;
2110 goto ret;
2111 }
2112 sc->sc_conf = value;
2113 break;
2114 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2115 break;
2116 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2117 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2118 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2119 err = USBD_IOERROR;
2120 goto ret;
2121 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2122 break;
2123 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2124 break;
2125 /* Hub requests */
2126 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2127 break;
2128 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2129 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
2130 "port=%d feature=%d\n",
2131 index, value));
2132 if (index < 1 || index > sc->sc_noport) {
2133 err = USBD_IOERROR;
2134 goto ret;
2135 }
2136 port = EHCI_PORTSC(index);
2137 v = EOREAD4(sc, port);
2138 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2139 v &= ~EHCI_PS_CLEAR;
2140 switch(value) {
2141 case UHF_PORT_ENABLE:
2142 EOWRITE4(sc, port, v &~ EHCI_PS_PE);
2143 break;
2144 case UHF_PORT_SUSPEND:
2145 if (!(v & EHCI_PS_SUSP)) /* not suspended */
2146 break;
2147 v &= ~EHCI_PS_SUSP;
2148 EOWRITE4(sc, port, v | EHCI_PS_FPR);
2149 /* see USB2 spec ch. 7.1.7.7 */
2150 usb_delay_ms(&sc->sc_bus, 20);
2151 EOWRITE4(sc, port, v);
2152 usb_delay_ms(&sc->sc_bus, 2);
2153 #ifdef DEBUG
2154 v = EOREAD4(sc, port);
2155 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP))
2156 printf("ehci: resume failed: %x\n", v);
2157 #endif
2158 break;
2159 case UHF_PORT_POWER:
2160 if (sc->sc_hasppc)
2161 EOWRITE4(sc, port, v &~ EHCI_PS_PP);
2162 break;
2163 case UHF_PORT_TEST:
2164 DPRINTFN(2,("ehci_root_ctrl_start: clear port test "
2165 "%d\n", index));
2166 break;
2167 case UHF_PORT_INDICATOR:
2168 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind "
2169 "%d\n", index));
2170 EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
2171 break;
2172 case UHF_C_PORT_CONNECTION:
2173 EOWRITE4(sc, port, v | EHCI_PS_CSC);
2174 break;
2175 case UHF_C_PORT_ENABLE:
2176 EOWRITE4(sc, port, v | EHCI_PS_PEC);
2177 break;
2178 case UHF_C_PORT_SUSPEND:
2179 /* how? */
2180 break;
2181 case UHF_C_PORT_OVER_CURRENT:
2182 EOWRITE4(sc, port, v | EHCI_PS_OCC);
2183 break;
2184 case UHF_C_PORT_RESET:
2185 sc->sc_isreset[index] = 0;
2186 break;
2187 default:
2188 err = USBD_IOERROR;
2189 goto ret;
2190 }
2191 #if 0
2192 switch(value) {
2193 case UHF_C_PORT_CONNECTION:
2194 case UHF_C_PORT_ENABLE:
2195 case UHF_C_PORT_SUSPEND:
2196 case UHF_C_PORT_OVER_CURRENT:
2197 case UHF_C_PORT_RESET:
2198 default:
2199 break;
2200 }
2201 #endif
2202 break;
2203 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2204 if (len == 0)
2205 break;
2206 if ((value & 0xff) != 0) {
2207 err = USBD_IOERROR;
2208 goto ret;
2209 }
2210 hubd = ehci_hubd;
2211 hubd.bNbrPorts = sc->sc_noport;
2212 v = EOREAD4(sc, EHCI_HCSPARAMS);
2213 USETW(hubd.wHubCharacteristics,
2214 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
2215 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
2216 ? UHD_PORT_IND : 0);
2217 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
2218 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2219 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
2220 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2221 l = min(len, hubd.bDescLength);
2222 totlen = l;
2223 memcpy(buf, &hubd, l);
2224 break;
2225 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2226 if (len != 4) {
2227 err = USBD_IOERROR;
2228 goto ret;
2229 }
2230 memset(buf, 0, len); /* ? XXX */
2231 totlen = len;
2232 break;
2233 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2234 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
2235 index));
2236 if (index < 1 || index > sc->sc_noport) {
2237 err = USBD_IOERROR;
2238 goto ret;
2239 }
2240 if (len != 4) {
2241 err = USBD_IOERROR;
2242 goto ret;
2243 }
2244 v = EOREAD4(sc, EHCI_PORTSC(index));
2245 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n",
2246 v));
2247 i = UPS_HIGH_SPEED;
2248 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
2249 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
2250 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
2251 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
2252 if (v & EHCI_PS_PR) i |= UPS_RESET;
2253 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
2254 USETW(ps.wPortStatus, i);
2255 i = 0;
2256 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
2257 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
2258 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
2259 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
2260 USETW(ps.wPortChange, i);
2261 l = min(len, sizeof ps);
2262 memcpy(buf, &ps, l);
2263 totlen = l;
2264 break;
2265 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2266 err = USBD_IOERROR;
2267 goto ret;
2268 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2269 break;
2270 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2271 if (index < 1 || index > sc->sc_noport) {
2272 err = USBD_IOERROR;
2273 goto ret;
2274 }
2275 port = EHCI_PORTSC(index);
2276 v = EOREAD4(sc, port);
2277 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
2278 v &= ~EHCI_PS_CLEAR;
2279 switch(value) {
2280 case UHF_PORT_ENABLE:
2281 EOWRITE4(sc, port, v | EHCI_PS_PE);
2282 break;
2283 case UHF_PORT_SUSPEND:
2284 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
2285 break;
2286 case UHF_PORT_RESET:
2287 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
2288 index));
2289 if (EHCI_PS_IS_LOWSPEED(v)) {
2290 /* Low speed device, give up ownership. */
2291 ehci_disown(sc, index, 1);
2292 break;
2293 }
2294 /* Start reset sequence. */
2295 v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
2296 EOWRITE4(sc, port, v | EHCI_PS_PR);
2297 /* Wait for reset to complete. */
2298 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
2299 if (sc->sc_dying) {
2300 err = USBD_IOERROR;
2301 goto ret;
2302 }
2303 /* Terminate reset sequence. */
2304 EOWRITE4(sc, port, v);
2305 /* Wait for HC to complete reset. */
2306 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
2307 if (sc->sc_dying) {
2308 err = USBD_IOERROR;
2309 goto ret;
2310 }
2311 v = EOREAD4(sc, port);
2312 DPRINTF(("ehci after reset, status=0x%08x\n", v));
2313 if (v & EHCI_PS_PR) {
2314 printf("%s: port reset timeout\n",
2315 device_xname(sc->sc_dev));
2316 return (USBD_TIMEOUT);
2317 }
2318 if (!(v & EHCI_PS_PE)) {
2319 /* Not a high speed device, give up ownership.*/
2320 ehci_disown(sc, index, 0);
2321 break;
2322 }
2323 sc->sc_isreset[index] = 1;
2324 DPRINTF(("ehci port %d reset, status = 0x%08x\n",
2325 index, v));
2326 break;
2327 case UHF_PORT_POWER:
2328 DPRINTFN(2,("ehci_root_ctrl_start: set port power "
2329 "%d (has PPC = %d)\n", index,
2330 sc->sc_hasppc));
2331 if (sc->sc_hasppc)
2332 EOWRITE4(sc, port, v | EHCI_PS_PP);
2333 break;
2334 case UHF_PORT_TEST:
2335 DPRINTFN(2,("ehci_root_ctrl_start: set port test "
2336 "%d\n", index));
2337 break;
2338 case UHF_PORT_INDICATOR:
2339 DPRINTFN(2,("ehci_root_ctrl_start: set port ind "
2340 "%d\n", index));
2341 EOWRITE4(sc, port, v | EHCI_PS_PIC);
2342 break;
2343 default:
2344 err = USBD_IOERROR;
2345 goto ret;
2346 }
2347 break;
2348 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2349 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2350 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2351 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2352 break;
2353 default:
2354 err = USBD_IOERROR;
2355 goto ret;
2356 }
2357 xfer->actlen = totlen;
2358 err = USBD_NORMAL_COMPLETION;
2359 ret:
2360 xfer->status = err;
2361 s = splusb();
2362 usb_transfer_complete(xfer);
2363 splx(s);
2364 return (USBD_IN_PROGRESS);
2365 }
2366
2367 Static void
2368 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
2369 {
2370 int port;
2371 u_int32_t v;
2372
2373 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
2374 #ifdef DIAGNOSTIC
2375 if (sc->sc_npcomp != 0) {
2376 int i = (index-1) / sc->sc_npcomp;
2377 if (i >= sc->sc_ncomp)
2378 printf("%s: strange port\n",
2379 device_xname(sc->sc_dev));
2380 else
2381 printf("%s: handing over %s speed device on "
2382 "port %d to %s\n",
2383 device_xname(sc->sc_dev),
2384 lowspeed ? "low" : "full",
2385 index, device_xname(sc->sc_comps[i]));
2386 } else {
2387 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev));
2388 }
2389 #endif
2390 port = EHCI_PORTSC(index);
2391 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2392 EOWRITE4(sc, port, v | EHCI_PS_PO);
2393 }
2394
2395 /* Abort a root control request. */
2396 Static void
2397 ehci_root_ctrl_abort(usbd_xfer_handle xfer)
2398 {
2399 /* Nothing to do, all transfers are synchronous. */
2400 }
2401
2402 /* Close the root pipe. */
2403 Static void
2404 ehci_root_ctrl_close(usbd_pipe_handle pipe)
2405 {
2406 DPRINTF(("ehci_root_ctrl_close\n"));
2407 /* Nothing to do. */
2408 }
2409
2410 Static void
2411 ehci_root_intr_done(usbd_xfer_handle xfer)
2412 {
2413 xfer->hcpriv = NULL;
2414 }
2415
2416 Static usbd_status
2417 ehci_root_intr_transfer(usbd_xfer_handle xfer)
2418 {
2419 usbd_status err;
2420
2421 /* Insert last in queue. */
2422 err = usb_insert_transfer(xfer);
2423 if (err)
2424 return (err);
2425
2426 /* Pipe isn't running, start first */
2427 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2428 }
2429
2430 Static usbd_status
2431 ehci_root_intr_start(usbd_xfer_handle xfer)
2432 {
2433 usbd_pipe_handle pipe = xfer->pipe;
2434 ehci_softc_t *sc = pipe->device->bus->hci_private;
2435
2436 if (sc->sc_dying)
2437 return (USBD_IOERROR);
2438
2439 sc->sc_intrxfer = xfer;
2440
2441 return (USBD_IN_PROGRESS);
2442 }
2443
2444 /* Abort a root interrupt request. */
2445 Static void
2446 ehci_root_intr_abort(usbd_xfer_handle xfer)
2447 {
2448 int s;
2449
2450 if (xfer->pipe->intrxfer == xfer) {
2451 DPRINTF(("ehci_root_intr_abort: remove\n"));
2452 xfer->pipe->intrxfer = NULL;
2453 }
2454 xfer->status = USBD_CANCELLED;
2455 s = splusb();
2456 usb_transfer_complete(xfer);
2457 splx(s);
2458 }
2459
2460 /* Close the root pipe. */
2461 Static void
2462 ehci_root_intr_close(usbd_pipe_handle pipe)
2463 {
2464 ehci_softc_t *sc = pipe->device->bus->hci_private;
2465
2466 DPRINTF(("ehci_root_intr_close\n"));
2467
2468 sc->sc_intrxfer = NULL;
2469 }
2470
2471 Static void
2472 ehci_root_ctrl_done(usbd_xfer_handle xfer)
2473 {
2474 xfer->hcpriv = NULL;
2475 }
2476
2477 /************************/
2478
2479 Static ehci_soft_qh_t *
2480 ehci_alloc_sqh(ehci_softc_t *sc)
2481 {
2482 ehci_soft_qh_t *sqh;
2483 usbd_status err;
2484 int i, offs;
2485 usb_dma_t dma;
2486
2487 if (sc->sc_freeqhs == NULL) {
2488 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2489 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2490 EHCI_PAGE_SIZE, &dma);
2491 #ifdef EHCI_DEBUG
2492 if (err)
2493 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2494 #endif
2495 if (err)
2496 return (NULL);
2497 for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2498 offs = i * EHCI_SQH_SIZE;
2499 sqh = KERNADDR(&dma, offs);
2500 sqh->physaddr = DMAADDR(&dma, offs);
2501 sqh->dma = dma;
2502 sqh->offs = offs;
2503 sqh->next = sc->sc_freeqhs;
2504 sc->sc_freeqhs = sqh;
2505 }
2506 }
2507 sqh = sc->sc_freeqhs;
2508 sc->sc_freeqhs = sqh->next;
2509 memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2510 sqh->next = NULL;
2511 return (sqh);
2512 }
2513
2514 Static void
2515 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2516 {
2517 sqh->next = sc->sc_freeqhs;
2518 sc->sc_freeqhs = sqh;
2519 }
2520
2521 Static ehci_soft_qtd_t *
2522 ehci_alloc_sqtd(ehci_softc_t *sc)
2523 {
2524 ehci_soft_qtd_t *sqtd;
2525 usbd_status err;
2526 int i, offs;
2527 usb_dma_t dma;
2528 int s;
2529
2530 if (sc->sc_freeqtds == NULL) {
2531 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
2532 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2533 EHCI_PAGE_SIZE, &dma);
2534 #ifdef EHCI_DEBUG
2535 if (err)
2536 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2537 #endif
2538 if (err)
2539 return (NULL);
2540 s = splusb();
2541 for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2542 offs = i * EHCI_SQTD_SIZE;
2543 sqtd = KERNADDR(&dma, offs);
2544 sqtd->physaddr = DMAADDR(&dma, offs);
2545 sqtd->dma = dma;
2546 sqtd->offs = offs;
2547 sqtd->nextqtd = sc->sc_freeqtds;
2548 sc->sc_freeqtds = sqtd;
2549 }
2550 splx(s);
2551 }
2552
2553 s = splusb();
2554 sqtd = sc->sc_freeqtds;
2555 sc->sc_freeqtds = sqtd->nextqtd;
2556 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2557 sqtd->nextqtd = NULL;
2558 sqtd->xfer = NULL;
2559 splx(s);
2560
2561 return (sqtd);
2562 }
2563
2564 Static void
2565 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2566 {
2567 int s;
2568
2569 s = splusb();
2570 sqtd->nextqtd = sc->sc_freeqtds;
2571 sc->sc_freeqtds = sqtd;
2572 splx(s);
2573 }
2574
2575 Static usbd_status
2576 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
2577 int alen, int rd, usbd_xfer_handle xfer,
2578 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2579 {
2580 ehci_soft_qtd_t *next, *cur;
2581 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
2582 u_int32_t qtdstatus;
2583 int len, curlen, mps;
2584 int i, tog;
2585 usb_dma_t *dma = &xfer->dmabuf;
2586 u_int16_t flags = xfer->flags;
2587
2588 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
2589
2590 len = alen;
2591 dataphys = DMAADDR(dma, 0);
2592 dataphyslastpage = EHCI_PAGE(dataphys + len - 1);
2593 qtdstatus = EHCI_QTD_ACTIVE |
2594 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2595 EHCI_QTD_SET_CERR(3)
2596 /* IOC set below */
2597 /* BYTES set below */
2598 ;
2599 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2600 tog = epipe->nexttoggle;
2601 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog);
2602
2603 cur = ehci_alloc_sqtd(sc);
2604 *sp = cur;
2605 if (cur == NULL)
2606 goto nomem;
2607
2608 usb_syncmem(dma, 0, alen,
2609 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2610 for (;;) {
2611 dataphyspage = EHCI_PAGE(dataphys);
2612 /* The EHCI hardware can handle at most 5 pages. */
2613 if (dataphyslastpage - dataphyspage <
2614 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) {
2615 /* we can handle it in this QTD */
2616 curlen = len;
2617 } else {
2618 /* must use multiple TDs, fill as much as possible. */
2619 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE -
2620 EHCI_PAGE_OFFSET(dataphys);
2621 #ifdef DIAGNOSTIC
2622 if (curlen > len) {
2623 printf("ehci_alloc_sqtd_chain: curlen=0x%x "
2624 "len=0x%x offs=0x%x\n", curlen, len,
2625 EHCI_PAGE_OFFSET(dataphys));
2626 printf("lastpage=0x%x page=0x%x phys=0x%x\n",
2627 dataphyslastpage, dataphyspage,
2628 dataphys);
2629 curlen = len;
2630 }
2631 #endif
2632 /* the length must be a multiple of the max size */
2633 curlen -= curlen % mps;
2634 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2635 "curlen=%d\n", curlen));
2636 #ifdef DIAGNOSTIC
2637 if (curlen == 0)
2638 panic("ehci_alloc_sqtd_chain: curlen == 0");
2639 #endif
2640 }
2641 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x "
2642 "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2643 dataphys, dataphyslastpage,
2644 len, curlen));
2645 len -= curlen;
2646
2647 /*
2648 * Allocate another transfer if there's more data left,
2649 * or if force last short transfer flag is set and we're
2650 * allocating a multiple of the max packet size.
2651 */
2652 if (len != 0 ||
2653 ((curlen % mps) == 0 && !rd && curlen != 0 &&
2654 (flags & USBD_FORCE_SHORT_XFER))) {
2655 next = ehci_alloc_sqtd(sc);
2656 if (next == NULL)
2657 goto nomem;
2658 nextphys = htole32(next->physaddr);
2659 } else {
2660 next = NULL;
2661 nextphys = EHCI_NULL;
2662 }
2663
2664 for (i = 0; i * EHCI_PAGE_SIZE <
2665 curlen + EHCI_PAGE_OFFSET(dataphys); i++) {
2666 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2667 if (i != 0) /* use offset only in first buffer */
2668 a = EHCI_PAGE(a);
2669 cur->qtd.qtd_buffer[i] = htole32(a);
2670 cur->qtd.qtd_buffer_hi[i] = 0;
2671 #ifdef DIAGNOSTIC
2672 if (i >= EHCI_QTD_NBUFFERS) {
2673 printf("ehci_alloc_sqtd_chain: i=%d\n", i);
2674 goto nomem;
2675 }
2676 #endif
2677 }
2678 cur->nextqtd = next;
2679 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
2680 cur->qtd.qtd_status =
2681 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen));
2682 cur->xfer = xfer;
2683 cur->len = curlen;
2684
2685 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n",
2686 dataphys, dataphys + curlen));
2687 /* adjust the toggle based on the number of packets in this
2688 qtd */
2689 if (((curlen + mps - 1) / mps) & 1) {
2690 tog ^= 1;
2691 qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
2692 }
2693 if (next == NULL)
2694 break;
2695 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
2696 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2697 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
2698 dataphys += curlen;
2699 cur = next;
2700 }
2701 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2702 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd),
2703 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2704 *ep = cur;
2705 epipe->nexttoggle = tog;
2706
2707 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2708 *sp, *ep));
2709
2710 return (USBD_NORMAL_COMPLETION);
2711
2712 nomem:
2713 /* XXX free chain */
2714 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
2715 return (USBD_NOMEM);
2716 }
2717
2718 Static void
2719 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
2720 ehci_soft_qtd_t *sqtdend)
2721 {
2722 ehci_soft_qtd_t *p;
2723 int i;
2724
2725 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2726 sqtd, sqtdend));
2727
2728 for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
2729 p = sqtd->nextqtd;
2730 ehci_free_sqtd(sc, sqtd);
2731 }
2732 }
2733
2734 Static ehci_soft_itd_t *
2735 ehci_alloc_itd(ehci_softc_t *sc)
2736 {
2737 struct ehci_soft_itd *itd, *freeitd;
2738 usbd_status err;
2739 int i, s, offs, frindex, previndex;
2740 usb_dma_t dma;
2741
2742 s = splusb();
2743
2744 /* Find an itd that wasn't freed this frame or last frame. This can
2745 * discard itds that were freed before frindex wrapped around
2746 * XXX - can this lead to thrashing? Could fix by enabling wrap-around
2747 * interrupt and fiddling with list when that happens */
2748 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3;
2749 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize;
2750
2751 freeitd = NULL;
2752 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) {
2753 if (itd == NULL)
2754 break;
2755 if (itd->slot != frindex && itd->slot != previndex) {
2756 freeitd = itd;
2757 break;
2758 }
2759 }
2760
2761 if (freeitd == NULL) {
2762 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n"));
2763 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK,
2764 EHCI_PAGE_SIZE, &dma);
2765
2766 if (err) {
2767 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err));
2768 return NULL;
2769 }
2770
2771 for (i = 0; i < EHCI_ITD_CHUNK; i++) {
2772 offs = i * EHCI_ITD_SIZE;
2773 itd = KERNADDR(&dma, offs);
2774 itd->physaddr = DMAADDR(&dma, offs);
2775 itd->dma = dma;
2776 itd->offs = offs;
2777 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
2778 }
2779 freeitd = LIST_FIRST(&sc->sc_freeitds);
2780 }
2781
2782 itd = freeitd;
2783 LIST_REMOVE(itd, u.free_list);
2784 memset(&itd->itd, 0, sizeof(ehci_itd_t));
2785 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next),
2786 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE |
2787 BUS_DMASYNC_PREREAD);
2788
2789 itd->u.frame_list.next = NULL;
2790 itd->u.frame_list.prev = NULL;
2791 itd->xfer_next = NULL;
2792 itd->slot = 0;
2793 splx(s);
2794
2795 return itd;
2796 }
2797
2798 Static void
2799 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd)
2800 {
2801 int s;
2802
2803 s = splusb();
2804 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list);
2805 splx(s);
2806 }
2807
2808 /****************/
2809
2810 /*
2811 * Close a reqular pipe.
2812 * Assumes that there are no pending transactions.
2813 */
2814 Static void
2815 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2816 {
2817 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
2818 ehci_softc_t *sc = pipe->device->bus->hci_private;
2819 ehci_soft_qh_t *sqh = epipe->sqh;
2820 int s;
2821
2822 s = splusb();
2823 ehci_rem_qh(sc, sqh, head);
2824 splx(s);
2825 ehci_free_sqh(sc, epipe->sqh);
2826 }
2827
2828 /*
2829 * Abort a device request.
2830 * If this routine is called at splusb() it guarantees that the request
2831 * will be removed from the hardware scheduling and that the callback
2832 * for it will be called with USBD_CANCELLED status.
2833 * It's impossible to guarantee that the requested transfer will not
2834 * have happened since the hardware runs concurrently.
2835 * If the transaction has already happened we rely on the ordinary
2836 * interrupt processing to process it.
2837 * XXX This is most probably wrong.
2838 */
2839 Static void
2840 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2841 {
2842 #define exfer EXFER(xfer)
2843 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2844 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private;
2845 ehci_soft_qh_t *sqh = epipe->sqh;
2846 ehci_soft_qtd_t *sqtd;
2847 ehci_physaddr_t cur;
2848 u_int32_t qhstatus;
2849 int s;
2850 int hit;
2851 int wake;
2852
2853 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
2854
2855 if (sc->sc_dying) {
2856 /* If we're dying, just do the software part. */
2857 s = splusb();
2858 xfer->status = status; /* make software ignore it */
2859 callout_stop(&(xfer->timeout_handle));
2860 usb_transfer_complete(xfer);
2861 splx(s);
2862 return;
2863 }
2864
2865 if (xfer->device->bus->intr_context)
2866 panic("ehci_abort_xfer: not in process context");
2867
2868 /*
2869 * If an abort is already in progress then just wait for it to
2870 * complete and return.
2871 */
2872 if (xfer->hcflags & UXFER_ABORTING) {
2873 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n"));
2874 #ifdef DIAGNOSTIC
2875 if (status == USBD_TIMEOUT)
2876 printf("ehci_abort_xfer: TIMEOUT while aborting\n");
2877 #endif
2878 /* Override the status which might be USBD_TIMEOUT. */
2879 xfer->status = status;
2880 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
2881 xfer->hcflags |= UXFER_ABORTWAIT;
2882 while (xfer->hcflags & UXFER_ABORTING)
2883 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0);
2884 return;
2885 }
2886 xfer->hcflags |= UXFER_ABORTING;
2887
2888 /*
2889 * Step 1: Make interrupt routine and hardware ignore xfer.
2890 */
2891 s = splusb();
2892 xfer->status = status; /* make software ignore it */
2893 callout_stop(&(xfer->timeout_handle));
2894
2895 usb_syncmem(&sqh->dma,
2896 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2897 sizeof(sqh->qh.qh_qtd.qtd_status),
2898 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2899 qhstatus = sqh->qh.qh_qtd.qtd_status;
2900 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
2901 usb_syncmem(&sqh->dma,
2902 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2903 sizeof(sqh->qh.qh_qtd.qtd_status),
2904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2905 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2906 usb_syncmem(&sqtd->dma,
2907 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
2908 sizeof(sqtd->qtd.qtd_status),
2909 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2910 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
2911 usb_syncmem(&sqtd->dma,
2912 sqtd->offs + offsetof(ehci_qtd_t, qtd_status),
2913 sizeof(sqtd->qtd.qtd_status),
2914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2915 if (sqtd == exfer->sqtdend)
2916 break;
2917 }
2918 splx(s);
2919
2920 /*
2921 * Step 2: Wait until we know hardware has finished any possible
2922 * use of the xfer. Also make sure the soft interrupt routine
2923 * has run.
2924 */
2925 ehci_sync_hc(sc);
2926 s = splusb();
2927 #ifdef USB_USE_SOFTINTR
2928 sc->sc_softwake = 1;
2929 #endif /* USB_USE_SOFTINTR */
2930 usb_schedsoftintr(&sc->sc_bus);
2931 #ifdef USB_USE_SOFTINTR
2932 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
2933 #endif /* USB_USE_SOFTINTR */
2934 splx(s);
2935
2936 /*
2937 * Step 3: Remove any vestiges of the xfer from the hardware.
2938 * The complication here is that the hardware may have executed
2939 * beyond the xfer we're trying to abort. So as we're scanning
2940 * the TDs of this xfer we check if the hardware points to
2941 * any of them.
2942 */
2943 s = splusb(); /* XXX why? */
2944
2945 usb_syncmem(&sqh->dma,
2946 sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
2947 sizeof(sqh->qh.qh_curqtd),
2948 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2949 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
2950 hit = 0;
2951 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2952 hit |= cur == sqtd->physaddr;
2953 if (sqtd == exfer->sqtdend)
2954 break;
2955 }
2956 sqtd = sqtd->nextqtd;
2957 /* Zap curqtd register if hardware pointed inside the xfer. */
2958 if (hit && sqtd != NULL) {
2959 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr));
2960 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
2961 usb_syncmem(&sqh->dma,
2962 sqh->offs + offsetof(ehci_qh_t, qh_curqtd),
2963 sizeof(sqh->qh.qh_curqtd),
2964 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2965 sqh->qh.qh_qtd.qtd_status = qhstatus;
2966 usb_syncmem(&sqh->dma,
2967 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status),
2968 sizeof(sqh->qh.qh_qtd.qtd_status),
2969 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2970 } else {
2971 DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
2972 }
2973
2974 /*
2975 * Step 4: Execute callback.
2976 */
2977 #ifdef DIAGNOSTIC
2978 exfer->isdone = 1;
2979 #endif
2980 wake = xfer->hcflags & UXFER_ABORTWAIT;
2981 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2982 usb_transfer_complete(xfer);
2983 if (wake)
2984 wakeup(&xfer->hcflags);
2985
2986 splx(s);
2987 #undef exfer
2988 }
2989
2990 Static void
2991 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status)
2992 {
2993 ehci_isoc_trans_t trans_status;
2994 struct ehci_pipe *epipe;
2995 struct ehci_xfer *exfer;
2996 ehci_softc_t *sc;
2997 struct ehci_soft_itd *itd;
2998 int s, i, wake;
2999
3000 epipe = (struct ehci_pipe *) xfer->pipe;
3001 exfer = EXFER(xfer);
3002 sc = epipe->pipe.device->bus->hci_private;
3003
3004 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe));
3005
3006 if (sc->sc_dying) {
3007 s = splusb();
3008 xfer->status = status;
3009 callout_stop(&(xfer->timeout_handle));
3010 usb_transfer_complete(xfer);
3011 splx(s);
3012 return;
3013 }
3014
3015 if (xfer->hcflags & UXFER_ABORTING) {
3016 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n"));
3017
3018 #ifdef DIAGNOSTIC
3019 if (status == USBD_TIMEOUT)
3020 printf("ehci_abort_xfer: TIMEOUT while aborting\n");
3021 #endif
3022
3023 xfer->status = status;
3024 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n"));
3025 xfer->hcflags |= UXFER_ABORTWAIT;
3026 while (xfer->hcflags & UXFER_ABORTING)
3027 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0);
3028 return;
3029 }
3030 xfer->hcflags |= UXFER_ABORTING;
3031
3032 xfer->status = status;
3033 callout_stop(&(xfer->timeout_handle));
3034
3035 s = splusb();
3036 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) {
3037 usb_syncmem(&itd->dma,
3038 itd->offs + offsetof(ehci_itd_t, itd_ctl),
3039 sizeof(itd->itd.itd_ctl),
3040 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3041
3042 for (i = 0; i < 8; i++) {
3043 trans_status = le32toh(itd->itd.itd_ctl[i]);
3044 trans_status &= ~EHCI_ITD_ACTIVE;
3045 itd->itd.itd_ctl[i] = htole32(trans_status);
3046 }
3047
3048 usb_syncmem(&itd->dma,
3049 itd->offs + offsetof(ehci_itd_t, itd_ctl),
3050 sizeof(itd->itd.itd_ctl),
3051 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3052 }
3053 splx(s);
3054
3055 s = splusb();
3056 #ifdef USB_USE_SOFTINTR
3057 sc->sc_softwake = 1;
3058 #endif /* USB_USE_SOFTINTR */
3059 usb_schedsoftintr(&sc->sc_bus);
3060 #ifdef USB_USE_SOFTINTR
3061 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
3062 #endif /* USB_USE_SOFTINTR */
3063 splx(s);
3064
3065 #ifdef DIAGNOSTIC
3066 exfer->isdone = 1;
3067 #endif
3068 wake = xfer->hcflags & UXFER_ABORTWAIT;
3069 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
3070 usb_transfer_complete(xfer);
3071 if (wake)
3072 wakeup(&xfer->hcflags);
3073
3074 return;
3075 }
3076
3077 Static void
3078 ehci_timeout(void *addr)
3079 {
3080 struct ehci_xfer *exfer = addr;
3081 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
3082 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private;
3083
3084 DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
3085 #ifdef EHCI_DEBUG
3086 if (ehcidebug > 1)
3087 usbd_dump_pipe(exfer->xfer.pipe);
3088 #endif
3089
3090 if (sc->sc_dying) {
3091 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
3092 return;
3093 }
3094
3095 /* Execute the abort in a process context. */
3096 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr);
3097 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task,
3098 USB_TASKQ_HC);
3099 }
3100
3101 Static void
3102 ehci_timeout_task(void *addr)
3103 {
3104 usbd_xfer_handle xfer = addr;
3105 int s;
3106
3107 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
3108
3109 s = splusb();
3110 ehci_abort_xfer(xfer, USBD_TIMEOUT);
3111 splx(s);
3112 }
3113
3114 /************************/
3115
3116 Static usbd_status
3117 ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
3118 {
3119 usbd_status err;
3120
3121 /* Insert last in queue. */
3122 err = usb_insert_transfer(xfer);
3123 if (err)
3124 return (err);
3125
3126 /* Pipe isn't running, start first */
3127 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3128 }
3129
3130 Static usbd_status
3131 ehci_device_ctrl_start(usbd_xfer_handle xfer)
3132 {
3133 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3134 usbd_status err;
3135
3136 if (sc->sc_dying)
3137 return (USBD_IOERROR);
3138
3139 #ifdef DIAGNOSTIC
3140 if (!(xfer->rqflags & URQ_REQUEST)) {
3141 /* XXX panic */
3142 printf("ehci_device_ctrl_transfer: not a request\n");
3143 return (USBD_INVAL);
3144 }
3145 #endif
3146
3147 err = ehci_device_request(xfer);
3148 if (err)
3149 return (err);
3150
3151 if (sc->sc_bus.use_polling)
3152 ehci_waitintr(sc, xfer);
3153 return (USBD_IN_PROGRESS);
3154 }
3155
3156 Static void
3157 ehci_device_ctrl_done(usbd_xfer_handle xfer)
3158 {
3159 struct ehci_xfer *ex = EXFER(xfer);
3160 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3161 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3162 usb_device_request_t *req = &xfer->request;
3163 int len = UGETW(req->wLength);
3164 int rd = req->bmRequestType & UT_READ;
3165
3166 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
3167
3168 #ifdef DIAGNOSTIC
3169 if (!(xfer->rqflags & URQ_REQUEST)) {
3170 panic("ehci_ctrl_done: not a request");
3171 }
3172 #endif
3173
3174 mutex_enter(&sc->sc_intrhead_lock);
3175 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3176 ehci_del_intr_list(sc, ex); /* remove from active list */
3177 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3178 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req,
3179 BUS_DMASYNC_POSTWRITE);
3180 if (len)
3181 usb_syncmem(&xfer->dmabuf, 0, len,
3182 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3183 }
3184 mutex_exit(&sc->sc_intrhead_lock);
3185
3186 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
3187 }
3188
3189 /* Abort a device control request. */
3190 Static void
3191 ehci_device_ctrl_abort(usbd_xfer_handle xfer)
3192 {
3193 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
3194 ehci_abort_xfer(xfer, USBD_CANCELLED);
3195 }
3196
3197 /* Close a device control pipe. */
3198 Static void
3199 ehci_device_ctrl_close(usbd_pipe_handle pipe)
3200 {
3201 ehci_softc_t *sc = pipe->device->bus->hci_private;
3202 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
3203
3204 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
3205 ehci_close_pipe(pipe, sc->sc_async_head);
3206 }
3207
3208 Static usbd_status
3209 ehci_device_request(usbd_xfer_handle xfer)
3210 {
3211 #define exfer EXFER(xfer)
3212 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3213 usb_device_request_t *req = &xfer->request;
3214 usbd_device_handle dev = epipe->pipe.device;
3215 ehci_softc_t *sc = dev->bus->hci_private;
3216 int addr = dev->address;
3217 ehci_soft_qtd_t *setup, *stat, *next;
3218 ehci_soft_qh_t *sqh;
3219 int isread;
3220 int len;
3221 usbd_status err;
3222 int s;
3223
3224 isread = req->bmRequestType & UT_READ;
3225 len = UGETW(req->wLength);
3226
3227 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
3228 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
3229 req->bmRequestType, req->bRequest, UGETW(req->wValue),
3230 UGETW(req->wIndex), len, addr,
3231 epipe->pipe.endpoint->edesc->bEndpointAddress));
3232
3233 setup = ehci_alloc_sqtd(sc);
3234 if (setup == NULL) {
3235 err = USBD_NOMEM;
3236 goto bad1;
3237 }
3238 stat = ehci_alloc_sqtd(sc);
3239 if (stat == NULL) {
3240 err = USBD_NOMEM;
3241 goto bad2;
3242 }
3243
3244 sqh = epipe->sqh;
3245 epipe->u.ctl.length = len;
3246
3247 /* Update device address and length since they may have changed
3248 during the setup of the control pipe in usbd_new_device(). */
3249 /* XXX This only needs to be done once, but it's too early in open. */
3250 /* XXXX Should not touch ED here! */
3251 sqh->qh.qh_endp =
3252 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) |
3253 htole32(
3254 EHCI_QH_SET_ADDR(addr) |
3255 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
3256 );
3257
3258 /* Set up data transaction */
3259 if (len != 0) {
3260 ehci_soft_qtd_t *end;
3261
3262 /* Start toggle at 1. */
3263 epipe->nexttoggle = 1;
3264 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3265 &next, &end);
3266 if (err)
3267 goto bad3;
3268 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
3269 end->nextqtd = stat;
3270 end->qtd.qtd_next =
3271 end->qtd.qtd_altnext = htole32(stat->physaddr);
3272 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd),
3273 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3274 } else {
3275 next = stat;
3276 }
3277
3278 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req);
3279 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
3280
3281 /* Clear toggle */
3282 setup->qtd.qtd_status = htole32(
3283 EHCI_QTD_ACTIVE |
3284 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
3285 EHCI_QTD_SET_CERR(3) |
3286 EHCI_QTD_SET_TOGGLE(0) |
3287 EHCI_QTD_SET_BYTES(sizeof *req)
3288 );
3289 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
3290 setup->qtd.qtd_buffer_hi[0] = 0;
3291 setup->nextqtd = next;
3292 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
3293 setup->xfer = xfer;
3294 setup->len = sizeof *req;
3295 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd),
3296 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3297
3298 stat->qtd.qtd_status = htole32(
3299 EHCI_QTD_ACTIVE |
3300 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
3301 EHCI_QTD_SET_CERR(3) |
3302 EHCI_QTD_SET_TOGGLE(1) |
3303 EHCI_QTD_IOC
3304 );
3305 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
3306 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
3307 stat->nextqtd = NULL;
3308 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
3309 stat->xfer = xfer;
3310 stat->len = 0;
3311 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd),
3312 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3313
3314 #ifdef EHCI_DEBUG
3315 if (ehcidebug > 5) {
3316 DPRINTF(("ehci_device_request:\n"));
3317 ehci_dump_sqh(sqh);
3318 ehci_dump_sqtds(setup);
3319 }
3320 #endif
3321
3322 exfer->sqtdstart = setup;
3323 exfer->sqtdend = stat;
3324 #ifdef DIAGNOSTIC
3325 if (!exfer->isdone) {
3326 printf("ehci_device_request: not done, exfer=%p\n", exfer);
3327 }
3328 exfer->isdone = 0;
3329 #endif
3330
3331 /* Insert qTD in QH list. */
3332 s = splusb();
3333 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */
3334 if (xfer->timeout && !sc->sc_bus.use_polling) {
3335 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)),
3336 (ehci_timeout), (xfer));
3337 }
3338 mutex_enter(&sc->sc_intrhead_lock);
3339 ehci_add_intr_list(sc, exfer);
3340 mutex_exit(&sc->sc_intrhead_lock);
3341 xfer->status = USBD_IN_PROGRESS;
3342 splx(s);
3343
3344 #ifdef EHCI_DEBUG
3345 if (ehcidebug > 10) {
3346 DPRINTF(("ehci_device_request: status=%x\n",
3347 EOREAD4(sc, EHCI_USBSTS)));
3348 delay(10000);
3349 ehci_dump_regs(sc);
3350 ehci_dump_sqh(sc->sc_async_head);
3351 ehci_dump_sqh(sqh);
3352 ehci_dump_sqtds(setup);
3353 }
3354 #endif
3355
3356 return (USBD_NORMAL_COMPLETION);
3357
3358 bad3:
3359 ehci_free_sqtd(sc, stat);
3360 bad2:
3361 ehci_free_sqtd(sc, setup);
3362 bad1:
3363 DPRINTFN(-1,("ehci_device_request: no memory\n"));
3364 xfer->status = err;
3365 usb_transfer_complete(xfer);
3366 return (err);
3367 #undef exfer
3368 }
3369
3370 /*
3371 * Some EHCI chips from VIA seem to trigger interrupts before writing back the
3372 * qTD status, or miss signalling occasionally under heavy load. If the host
3373 * machine is too fast, we we can miss transaction completion - when we scan
3374 * the active list the transaction still seems to be active. This generally
3375 * exhibits itself as a umass stall that never recovers.
3376 *
3377 * We work around this behaviour by setting up this callback after any softintr
3378 * that completes with transactions still pending, giving us another chance to
3379 * check for completion after the writeback has taken place.
3380 */
3381 Static void
3382 ehci_intrlist_timeout(void *arg)
3383 {
3384 ehci_softc_t *sc = arg;
3385 int s = splusb();
3386
3387 DPRINTF(("ehci_intrlist_timeout\n"));
3388 usb_schedsoftintr(&sc->sc_bus);
3389
3390 splx(s);
3391 }
3392
3393 /************************/
3394
3395 Static usbd_status
3396 ehci_device_bulk_transfer(usbd_xfer_handle xfer)
3397 {
3398 usbd_status err;
3399
3400 /* Insert last in queue. */
3401 err = usb_insert_transfer(xfer);
3402 if (err)
3403 return (err);
3404
3405 /* Pipe isn't running, start first */
3406 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3407 }
3408
3409 Static usbd_status
3410 ehci_device_bulk_start(usbd_xfer_handle xfer)
3411 {
3412 #define exfer EXFER(xfer)
3413 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3414 usbd_device_handle dev = epipe->pipe.device;
3415 ehci_softc_t *sc = dev->bus->hci_private;
3416 ehci_soft_qtd_t *data, *dataend;
3417 ehci_soft_qh_t *sqh;
3418 usbd_status err;
3419 int len, isread, endpt;
3420 int s;
3421
3422 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
3423 xfer, xfer->length, xfer->flags));
3424
3425 if (sc->sc_dying)
3426 return (USBD_IOERROR);
3427
3428 #ifdef DIAGNOSTIC
3429 if (xfer->rqflags & URQ_REQUEST)
3430 panic("ehci_device_bulk_start: a request");
3431 #endif
3432
3433 len = xfer->length;
3434 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3435 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3436 sqh = epipe->sqh;
3437
3438 epipe->u.bulk.length = len;
3439
3440 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3441 &dataend);
3442 if (err) {
3443 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n"));
3444 xfer->status = err;
3445 usb_transfer_complete(xfer);
3446 return (err);
3447 }
3448
3449 #ifdef EHCI_DEBUG
3450 if (ehcidebug > 5) {
3451 DPRINTF(("ehci_device_bulk_start: data(1)\n"));
3452 ehci_dump_sqh(sqh);
3453 ehci_dump_sqtds(data);
3454 }
3455 #endif
3456
3457 /* Set up interrupt info. */
3458 exfer->sqtdstart = data;
3459 exfer->sqtdend = dataend;
3460 #ifdef DIAGNOSTIC
3461 if (!exfer->isdone) {
3462 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
3463 }
3464 exfer->isdone = 0;
3465 #endif
3466
3467 s = splusb();
3468 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
3469 if (xfer->timeout && !sc->sc_bus.use_polling) {
3470 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)),
3471 (ehci_timeout), (xfer));
3472 }
3473 mutex_enter(&sc->sc_intrhead_lock);
3474 ehci_add_intr_list(sc, exfer);
3475 mutex_exit(&sc->sc_intrhead_lock);
3476 xfer->status = USBD_IN_PROGRESS;
3477 splx(s);
3478
3479 #ifdef EHCI_DEBUG
3480 if (ehcidebug > 10) {
3481 DPRINTF(("ehci_device_bulk_start: data(2)\n"));
3482 delay(10000);
3483 DPRINTF(("ehci_device_bulk_start: data(3)\n"));
3484 ehci_dump_regs(sc);
3485 #if 0
3486 printf("async_head:\n");
3487 ehci_dump_sqh(sc->sc_async_head);
3488 #endif
3489 printf("sqh:\n");
3490 ehci_dump_sqh(sqh);
3491 ehci_dump_sqtds(data);
3492 }
3493 #endif
3494
3495 if (sc->sc_bus.use_polling)
3496 ehci_waitintr(sc, xfer);
3497
3498 return (USBD_IN_PROGRESS);
3499 #undef exfer
3500 }
3501
3502 Static void
3503 ehci_device_bulk_abort(usbd_xfer_handle xfer)
3504 {
3505 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
3506 ehci_abort_xfer(xfer, USBD_CANCELLED);
3507 }
3508
3509 /*
3510 * Close a device bulk pipe.
3511 */
3512 Static void
3513 ehci_device_bulk_close(usbd_pipe_handle pipe)
3514 {
3515 ehci_softc_t *sc = pipe->device->bus->hci_private;
3516
3517 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
3518 ehci_close_pipe(pipe, sc->sc_async_head);
3519 }
3520
3521 Static void
3522 ehci_device_bulk_done(usbd_xfer_handle xfer)
3523 {
3524 struct ehci_xfer *ex = EXFER(xfer);
3525 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3526 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3527 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3528 int rd = UE_GET_DIR(endpt) == UE_DIR_IN;
3529
3530 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
3531 xfer, xfer->actlen));
3532
3533 mutex_enter(&sc->sc_intrhead_lock);
3534 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3535 ehci_del_intr_list(sc, ex); /* remove from active list */
3536 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3537 usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3538 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3539 }
3540 mutex_exit(&sc->sc_intrhead_lock);
3541
3542 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
3543 }
3544
3545 /************************/
3546
3547 Static usbd_status
3548 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
3549 {
3550 struct ehci_soft_islot *isp;
3551 int islot, lev;
3552
3553 /* Find a poll rate that is large enough. */
3554 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
3555 if (EHCI_ILEV_IVAL(lev) <= ival)
3556 break;
3557
3558 /* Pick an interrupt slot at the right level. */
3559 /* XXX could do better than picking at random */
3560 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize;
3561 islot = EHCI_IQHIDX(lev, sc->sc_rand);
3562
3563 sqh->islot = islot;
3564 isp = &sc->sc_islots[islot];
3565 ehci_add_qh(sqh, isp->sqh);
3566
3567 return (USBD_NORMAL_COMPLETION);
3568 }
3569
3570 Static usbd_status
3571 ehci_device_intr_transfer(usbd_xfer_handle xfer)
3572 {
3573 usbd_status err;
3574
3575 /* Insert last in queue. */
3576 err = usb_insert_transfer(xfer);
3577 if (err)
3578 return (err);
3579
3580 /*
3581 * Pipe isn't running (otherwise err would be USBD_INPROG),
3582 * so start it first.
3583 */
3584 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3585 }
3586
3587 Static usbd_status
3588 ehci_device_intr_start(usbd_xfer_handle xfer)
3589 {
3590 #define exfer EXFER(xfer)
3591 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3592 usbd_device_handle dev = xfer->pipe->device;
3593 ehci_softc_t *sc = dev->bus->hci_private;
3594 ehci_soft_qtd_t *data, *dataend;
3595 ehci_soft_qh_t *sqh;
3596 usbd_status err;
3597 int len, isread, endpt;
3598 int s;
3599
3600 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
3601 xfer, xfer->length, xfer->flags));
3602
3603 if (sc->sc_dying)
3604 return (USBD_IOERROR);
3605
3606 #ifdef DIAGNOSTIC
3607 if (xfer->rqflags & URQ_REQUEST)
3608 panic("ehci_device_intr_start: a request");
3609 #endif
3610
3611 len = xfer->length;
3612 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3613 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3614 sqh = epipe->sqh;
3615
3616 epipe->u.intr.length = len;
3617
3618 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3619 &dataend);
3620 if (err) {
3621 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3622 xfer->status = err;
3623 usb_transfer_complete(xfer);
3624 return (err);
3625 }
3626
3627 #ifdef EHCI_DEBUG
3628 if (ehcidebug > 5) {
3629 DPRINTF(("ehci_device_intr_start: data(1)\n"));
3630 ehci_dump_sqh(sqh);
3631 ehci_dump_sqtds(data);
3632 }
3633 #endif
3634
3635 /* Set up interrupt info. */
3636 exfer->sqtdstart = data;
3637 exfer->sqtdend = dataend;
3638 #ifdef DIAGNOSTIC
3639 if (!exfer->isdone) {
3640 printf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3641 }
3642 exfer->isdone = 0;
3643 #endif
3644
3645 s = splusb();
3646 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
3647 if (xfer->timeout && !sc->sc_bus.use_polling) {
3648 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)),
3649 (ehci_timeout), (xfer));
3650 }
3651 mutex_enter(&sc->sc_intrhead_lock);
3652 ehci_add_intr_list(sc, exfer);
3653 mutex_exit(&sc->sc_intrhead_lock);
3654 xfer->status = USBD_IN_PROGRESS;
3655 splx(s);
3656
3657 #ifdef EHCI_DEBUG
3658 if (ehcidebug > 10) {
3659 DPRINTF(("ehci_device_intr_start: data(2)\n"));
3660 delay(10000);
3661 DPRINTF(("ehci_device_intr_start: data(3)\n"));
3662 ehci_dump_regs(sc);
3663 printf("sqh:\n");
3664 ehci_dump_sqh(sqh);
3665 ehci_dump_sqtds(data);
3666 }
3667 #endif
3668
3669 if (sc->sc_bus.use_polling)
3670 ehci_waitintr(sc, xfer);
3671
3672 return (USBD_IN_PROGRESS);
3673 #undef exfer
3674 }
3675
3676 Static void
3677 ehci_device_intr_abort(usbd_xfer_handle xfer)
3678 {
3679 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
3680 if (xfer->pipe->intrxfer == xfer) {
3681 DPRINTFN(1, ("echi_device_intr_abort: remove\n"));
3682 xfer->pipe->intrxfer = NULL;
3683 }
3684 /*
3685 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance
3686 * async doorbell. That's dependant on the async list, wheras
3687 * intr xfers are periodic, should not use this?
3688 */
3689 ehci_abort_xfer(xfer, USBD_CANCELLED);
3690 }
3691
3692 Static void
3693 ehci_device_intr_close(usbd_pipe_handle pipe)
3694 {
3695 ehci_softc_t *sc = pipe->device->bus->hci_private;
3696 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3697 struct ehci_soft_islot *isp;
3698
3699 isp = &sc->sc_islots[epipe->sqh->islot];
3700 ehci_close_pipe(pipe, isp->sqh);
3701 }
3702
3703 Static void
3704 ehci_device_intr_done(usbd_xfer_handle xfer)
3705 {
3706 #define exfer EXFER(xfer)
3707 struct ehci_xfer *ex = EXFER(xfer);
3708 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3709 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3710 ehci_soft_qtd_t *data, *dataend;
3711 ehci_soft_qh_t *sqh;
3712 usbd_status err;
3713 int len, isread, endpt, s;
3714
3715 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3716 xfer, xfer->actlen));
3717
3718 mutex_enter(&sc->sc_intrhead_lock);
3719 if (xfer->pipe->repeat) {
3720 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3721
3722 len = epipe->u.intr.length;
3723 xfer->length = len;
3724 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3725 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3726 usb_syncmem(&xfer->dmabuf, 0, len,
3727 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3728 sqh = epipe->sqh;
3729
3730 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3731 &data, &dataend);
3732 if (err) {
3733 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3734 xfer->status = err;
3735 mutex_exit(&sc->sc_intrhead_lock);
3736 return;
3737 }
3738
3739 /* Set up interrupt info. */
3740 exfer->sqtdstart = data;
3741 exfer->sqtdend = dataend;
3742 #ifdef DIAGNOSTIC
3743 if (!exfer->isdone) {
3744 printf("ehci_device_intr_done: not done, ex=%p\n",
3745 exfer);
3746 }
3747 exfer->isdone = 0;
3748 #endif
3749
3750 s = splusb();
3751 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */
3752 if (xfer->timeout && !sc->sc_bus.use_polling) {
3753 callout_reset(&(xfer->timeout_handle),
3754 (mstohz(xfer->timeout)), (ehci_timeout), (xfer));
3755 }
3756 splx(s);
3757
3758 xfer->status = USBD_IN_PROGRESS;
3759 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3760 ehci_del_intr_list(sc, ex); /* remove from active list */
3761 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3762 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3763 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3764 usb_syncmem(&xfer->dmabuf, 0, xfer->length,
3765 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
3766 }
3767 mutex_exit(&sc->sc_intrhead_lock);
3768 #undef exfer
3769 }
3770
3771 /************************/
3772
3773 Static usbd_status
3774 ehci_device_isoc_transfer(usbd_xfer_handle xfer)
3775 {
3776 usbd_status err;
3777
3778 err = usb_insert_transfer(xfer);
3779 if (err && err != USBD_IN_PROGRESS)
3780 return err;
3781
3782 return ehci_device_isoc_start(xfer);
3783 }
3784
3785 Static usbd_status
3786 ehci_device_isoc_start(usbd_xfer_handle xfer)
3787 {
3788 struct ehci_pipe *epipe;
3789 usbd_device_handle dev;
3790 ehci_softc_t *sc;
3791 struct ehci_xfer *exfer;
3792 ehci_soft_itd_t *itd, *prev, *start, *stop;
3793 usb_dma_t *dma_buf;
3794 int i, j, k, frames, uframes, ufrperframe;
3795 int s, trans_count, offs, total_length;
3796 int frindex;
3797
3798 start = NULL;
3799 prev = NULL;
3800 itd = NULL;
3801 trans_count = 0;
3802 total_length = 0;
3803 exfer = (struct ehci_xfer *) xfer;
3804 sc = xfer->pipe->device->bus->hci_private;
3805 dev = xfer->pipe->device;
3806 epipe = (struct ehci_pipe *)xfer->pipe;
3807
3808 /*
3809 * To allow continuous transfers, above we start all transfers
3810 * immediately. However, we're still going to get usbd_start_next call
3811 * this when another xfer completes. So, check if this is already
3812 * in progress or not
3813 */
3814
3815 if (exfer->itdstart != NULL)
3816 return USBD_IN_PROGRESS;
3817
3818 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n",
3819 xfer, xfer->length, xfer->flags));
3820
3821 if (sc->sc_dying)
3822 return USBD_IOERROR;
3823
3824 /*
3825 * To avoid complication, don't allow a request right now that'll span
3826 * the entire frame table. To within 4 frames, to allow some leeway
3827 * on either side of where the hc currently is.
3828 */
3829 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) *
3830 xfer->nframes >= (sc->sc_flsize - 4) * 8) {
3831 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n");
3832 return USBD_INVAL;
3833 }
3834
3835 #ifdef DIAGNOSTIC
3836 if (xfer->rqflags & URQ_REQUEST)
3837 panic("ehci_device_isoc_start: request\n");
3838
3839 if (!exfer->isdone)
3840 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer);
3841 exfer->isdone = 0;
3842 #endif
3843
3844 /*
3845 * Step 1: Allocate and initialize itds, how many do we need?
3846 * One per transfer if interval >= 8 microframes, fewer if we use
3847 * multiple microframes per frame.
3848 */
3849
3850 i = epipe->pipe.endpoint->edesc->bInterval;
3851 if (i > 16 || i == 0) {
3852 /* Spec page 271 says intervals > 16 are invalid */
3853 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i));
3854 return USBD_INVAL;
3855 }
3856
3857 switch (i) {
3858 case 1:
3859 ufrperframe = 8;
3860 break;
3861 case 2:
3862 ufrperframe = 4;
3863 break;
3864 case 3:
3865 ufrperframe = 2;
3866 break;
3867 default:
3868 ufrperframe = 1;
3869 break;
3870 }
3871 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe;
3872 uframes = 8 / ufrperframe;
3873
3874 if (frames == 0) {
3875 DPRINTF(("ehci_device_isoc_start: frames == 0\n"));
3876 return USBD_INVAL;
3877 }
3878
3879 dma_buf = &xfer->dmabuf;
3880 offs = 0;
3881
3882 for (i = 0; i < frames; i++) {
3883 int froffs = offs;
3884 itd = ehci_alloc_itd(sc);
3885
3886 if (prev != NULL) {
3887 prev->itd.itd_next =
3888 htole32(itd->physaddr | EHCI_LINK_ITD);
3889 usb_syncmem(&itd->dma,
3890 itd->offs + offsetof(ehci_itd_t, itd_next),
3891 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE);
3892
3893 prev->xfer_next = itd;
3894 } else {
3895 start = itd;
3896 }
3897
3898 /*
3899 * Step 1.5, initialize uframes
3900 */
3901 for (j = 0; j < 8; j += uframes) {
3902 /* Calculate which page in the list this starts in */
3903 int addr = DMAADDR(dma_buf, froffs);
3904 addr = EHCI_PAGE_OFFSET(addr);
3905 addr += (offs - froffs);
3906 addr = EHCI_PAGE(addr);
3907 addr /= EHCI_PAGE_SIZE;
3908
3909 /* This gets the initial offset into the first page,
3910 * looks how far further along the current uframe
3911 * offset is. Works out how many pages that is.
3912 */
3913
3914 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE |
3915 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) |
3916 EHCI_ITD_SET_PG(addr) |
3917 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs))));
3918
3919 total_length += xfer->frlengths[trans_count];
3920 offs += xfer->frlengths[trans_count];
3921 trans_count++;
3922
3923 if (trans_count >= xfer->nframes) { /*Set IOC*/
3924 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC);
3925 break;
3926 }
3927 }
3928
3929 /* Step 1.75, set buffer pointers. To simplify matters, all
3930 * pointers are filled out for the next 7 hardware pages in
3931 * the dma block, so no need to worry what pages to cover
3932 * and what to not.
3933 */
3934
3935 for (j=0; j < 7; j++) {
3936 /*
3937 * Don't try to lookup a page that's past the end
3938 * of buffer
3939 */
3940 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j));
3941 if (page_offs >= dma_buf->block->size)
3942 break;
3943
3944 long long page = DMAADDR(dma_buf, page_offs);
3945 page = EHCI_PAGE(page);
3946 itd->itd.itd_bufr[j] =
3947 htole32(EHCI_ITD_SET_BPTR(page));
3948 itd->itd.itd_bufr_hi[j] =
3949 htole32(page >> 32);
3950 }
3951
3952 /*
3953 * Other special values
3954 */
3955
3956 k = epipe->pipe.endpoint->edesc->bEndpointAddress;
3957 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) |
3958 EHCI_ITD_SET_DADDR(epipe->pipe.device->address));
3959
3960 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress))
3961 ? 1 : 0;
3962 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
3963 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) |
3964 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j)));
3965
3966 /* FIXME: handle invalid trans */
3967 itd->itd.itd_bufr[2] |=
3968 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1));
3969
3970 usb_syncmem(&itd->dma,
3971 itd->offs + offsetof(ehci_itd_t, itd_next),
3972 sizeof(ehci_itd_t),
3973 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3974
3975 prev = itd;
3976 } /* End of frame */
3977
3978 stop = itd;
3979 stop->xfer_next = NULL;
3980 exfer->isoc_len = total_length;
3981
3982 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length,
3983 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3984
3985 /*
3986 * Part 2: Transfer descriptors have now been set up, now they must
3987 * be scheduled into the period frame list. Erk. Not wanting to
3988 * complicate matters, transfer is denied if the transfer spans
3989 * more than the period frame list.
3990 */
3991
3992 s = splusb();
3993
3994 /* Start inserting frames */
3995 if (epipe->u.isoc.cur_xfers > 0) {
3996 frindex = epipe->u.isoc.next_frame;
3997 } else {
3998 frindex = EOREAD4(sc, EHCI_FRINDEX);
3999 frindex = frindex >> 3; /* Erase microframe index */
4000 frindex += 2;
4001 }
4002
4003 if (frindex >= sc->sc_flsize)
4004 frindex &= (sc->sc_flsize - 1);
4005
4006 /* Whats the frame interval? */
4007 i = (1 << epipe->pipe.endpoint->edesc->bInterval);
4008 if (i / 8 == 0)
4009 i = 1;
4010 else
4011 i /= 8;
4012
4013 itd = start;
4014 for (j = 0; j < frames; j++) {
4015 if (itd == NULL)
4016 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n");
4017
4018 itd->itd.itd_next = sc->sc_flist[frindex];
4019 if (itd->itd.itd_next == 0)
4020 /* FIXME: frindex table gets initialized to NULL
4021 * or EHCI_NULL? */
4022 itd->itd.itd_next = EHCI_NULL;
4023
4024 usb_syncmem(&itd->dma,
4025 itd->offs + offsetof(ehci_itd_t, itd_next),
4026 sizeof(itd->itd.itd_next),
4027 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4028
4029 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr);
4030
4031 usb_syncmem(&sc->sc_fldma,
4032 sizeof(ehci_link_t) * frindex,
4033 sizeof(ehci_link_t),
4034 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
4035
4036 itd->u.frame_list.next = sc->sc_softitds[frindex];
4037 sc->sc_softitds[frindex] = itd;
4038 if (itd->u.frame_list.next != NULL)
4039 itd->u.frame_list.next->u.frame_list.prev = itd;
4040 itd->slot = frindex;
4041 itd->u.frame_list.prev = NULL;
4042
4043 frindex += i;
4044 if (frindex >= sc->sc_flsize)
4045 frindex -= sc->sc_flsize;
4046
4047 itd = itd->xfer_next;
4048 }
4049
4050 epipe->u.isoc.cur_xfers++;
4051 epipe->u.isoc.next_frame = frindex;
4052
4053 exfer->itdstart = start;
4054 exfer->itdend = stop;
4055 exfer->sqtdstart = NULL;
4056 exfer->sqtdstart = NULL;
4057
4058 mutex_enter(&sc->sc_intrhead_lock);
4059 ehci_add_intr_list(sc, exfer);
4060 mutex_exit(&sc->sc_intrhead_lock);
4061 xfer->status = USBD_IN_PROGRESS;
4062 xfer->done = 0;
4063 splx(s);
4064
4065 if (sc->sc_bus.use_polling) {
4066 printf("Starting ehci isoc xfer with polling. Bad idea?\n");
4067 ehci_waitintr(sc, xfer);
4068 }
4069
4070 return USBD_IN_PROGRESS;
4071 }
4072
4073 Static void
4074 ehci_device_isoc_abort(usbd_xfer_handle xfer)
4075 {
4076 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer));
4077 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED);
4078 }
4079
4080 Static void
4081 ehci_device_isoc_close(usbd_pipe_handle pipe)
4082 {
4083 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n"));
4084 }
4085
4086 Static void
4087 ehci_device_isoc_done(usbd_xfer_handle xfer)
4088 {
4089 struct ehci_xfer *exfer;
4090 ehci_softc_t *sc;
4091 struct ehci_pipe *epipe;
4092 int s;
4093
4094 exfer = EXFER(xfer);
4095 sc = xfer->pipe->device->bus->hci_private;
4096 epipe = (struct ehci_pipe *) xfer->pipe;
4097
4098 s = splusb();
4099 epipe->u.isoc.cur_xfers--;
4100 mutex_enter(&sc->sc_intrhead_lock);
4101 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) {
4102 ehci_del_intr_list(sc, exfer);
4103 ehci_rem_free_itd_chain(sc, exfer);
4104 }
4105 mutex_exit(&sc->sc_intrhead_lock);
4106 splx(s);
4107
4108 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE |
4109 BUS_DMASYNC_POSTREAD);
4110
4111 }
NetBSD on the FriendlyARM MINI2440