sys/external/isc/atheros_hal/ic/ah_osdep.h

   1 /*-
   2  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  *
  29  * $Id: ah_osdep.h,v 1.1 2008/12/11 05:37:40 alc Exp $
  30  */
  31
  32 #ifndef _ATH_AH_OSDEP_H_
  33 #define _ATH_AH_OSDEP_H_
  34 /*
  35  * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
  36  */
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/endian.h>
  40 #include <sys/bus.h>
  41
  42 #include <machine/stdarg.h>
  43
  44 /*
  45  * Delay n microseconds.
  46  */
  47 extern  void ath_hal_delay(int);
  48 #define OS_DELAY(_n)    ath_hal_delay(_n)
  49
  50 #define OS_INLINE       __inline
  51 #define OS_MEMZERO(_a, _n)      ath_hal_memzero((_a), (_n))
  52 extern void ath_hal_memzero(void *, size_t);
  53 #define OS_MEMCPY(_d, _s, _n)   ath_hal_memcpy(_d,_s,_n)
  54 extern void *ath_hal_memcpy(void *, const void *, size_t);
  55
  56 #define abs(_a)         __builtin_abs(_a)
  57
  58 struct ath_hal;
  59 extern  u_int32_t ath_hal_getuptime(struct ath_hal *);
  60 #define OS_GETUPTIME(_ah)       ath_hal_getuptime(_ah)
  61
  62 /*
  63  * WiSoC boards overload the bus tag with information about the
  64  * board layout.  We must extract the bus space tag from that
  65  * indirect structure.  For everyone else the tag is passed in
  66  * directly.
  67  * XXX cache indirect ref privately
  68  */
  69 #ifdef AH_SUPPORT_AR5312
  70 #define BUSTAG(ah) \
  71         ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
  72 #define BUSHANDLE(ah)   ((bus_space_handle_t)((ah)->ah_sh))
  73
  74 #elif defined(AH_REGOPS_FUNC)
  75 #define BUSTAG(ah)      (*(bus_space_tag_t *) (ah)->ah_st)
  76 #define BUSHANDLE(ah)   (*(bus_space_handle_t *)((ah)->ah_sh))
  77 #define HALTAG(t)       (HAL_BUS_TAG) &(t)
  78 #define HALHANDLE(h)    (HAL_BUS_HANDLE) &(h)
  79 #else
  80 #define BUSTAG(ah)      ((bus_space_tag_t) (ah)->ah_st)
  81 #define BUSHANDLE(ah)   ((bus_space_handle_t) ((ah)->ah_sh))
  82 #define HALTAG(t)       (HAL_BUS_TAG) (t)
  83 #define HALHANDLE(h)    (HAL_BUS_HANDLE) (h)
  84 #endif
  85
  86 /*
  87  * Register read/write; we assume the registers will always
  88  * be memory-mapped.  Note that register accesses are done
  89  * using target-specific functions when debugging is enabled
  90  * (ATHHAL_DEBUG) or we are explicitly configured this way.  The
  91  * latter is used on some platforms where the full i/o space
  92  * cannot be directly mapped.
  93  */
  94 #if defined(ATHHAL_DEBUG) || defined(AH_REGOPS_FUNC) || defined(ATHHAL_DEBUG_ALQ)
  95 #define OS_REG_WRITE(_ah, _reg, _val)   ath_hal_reg_write(_ah, _reg, _val)
  96 #define OS_REG_READ(_ah, _reg)          ath_hal_reg_read(_ah, _reg)
  97
  98 extern  void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
  99 extern  u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
 100 #else
 101 /*
 102  * The hardware registers are native little-endian byte order.
 103  * Big-endian hosts are handled by enabling hardware byte-swap
 104  * of register reads and writes at reset.  But the PCI clock
 105  * domain registers are not byte swapped!  Thus, on big-endian
 106  * platforms we have to byte-swap thoese registers specifically.
 107  * Most of this code is collapsed at compile time because the
 108  * register values are constants.
 109  */
 110 #define AH_LITTLE_ENDIAN        1234
 111 #define AH_BIG_ENDIAN           4321
 112
 113 #if _BYTE_ORDER == _BIG_ENDIAN
 114 #define OS_REG_WRITE(_ah, _reg, _val) do {                              \
 115         if ( (_reg) >= 0x4000 && (_reg) < 0x5000)                       \
 116                 bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh,           \
 117                         (_reg), (_val));                                \
 118         else                                                            \
 119                 bus_space_write_stream_4((_ah)->ah_st, (_ah)->ah_sh,    \
 120                         (_reg), (_val));                                \
 121 } while (0)
 122 #define OS_REG_READ(_ah, _reg)                                          \
 123         (((_reg) >= 0x4000 && (_reg) < 0x5000) ?                        \
 124                 bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)) :  \
 125                 bus_space_read_stream_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
 126 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
 127 #define OS_REG_WRITE(_ah, _reg, _val)                                   \
 128         bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
 129 #define OS_REG_READ(_ah, _reg)                                          \
 130         ((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
 131 #endif /* _BYTE_ORDER */
 132 #endif /* ATHHAL_DEBUG || AH_REGFUNC || ATHHAL_DEBUG_ALQ */
 133
 134 #ifdef ATHHAL_DEBUG_ALQ
 135 extern  void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
 136 #else
 137 #define OS_MARK(_ah, _id, _v)
 138 #endif
 139
 140 typedef void *  HAL_SOFTC;              /* pointer to driver/OS state */
 141 typedef bus_space_tag_t         HAL_BUS_TAG;    /* opaque bus i/o id tag */
 142 typedef bus_space_handle_t      HAL_BUS_HANDLE; /* opaque bus i/o handle */
 143
 144 #define OS_SET_DECLARE(set, ptype)      __link_set_decl(set, ptype)
 145 #define OS_DATA_SET(set, sym)           __link_set_add_rodata(set, sym)
 146 #define OS_SET_FOREACH(pvar, set)       __link_set_foreach(pvar, set)
 147
 148 #define __bswap16(x)                    bswap16(x)
 149 #define __bswap32(x)                    bswap32(x)
 150
 151 #endif /* _ATH_AH_OSDEP_H_ */