| blob | b0877f6eef1d3b49b18d90553574b8a33a94801a |
1 @section Relocations
2 BFD maintains relocations in much the same way it maintains
3 symbols: they are left alone until required, then read in
4 en-masse and translated into an internal form. A common
5 routine @code{bfd_perform_relocation} acts upon the
6 canonical form to do the fixup.
8 Relocations are maintained on a per section basis,
9 while symbols are maintained on a per BFD basis.
11 All that a back end has to do to fit the BFD interface is to create
12 a @code{struct reloc_cache_entry} for each relocation
13 in a particular section, and fill in the right bits of the structures.
15 @menu
16 * typedef arelent::
17 * howto manager::
18 @end menu
21 @node typedef arelent, howto manager, Relocations, Relocations
22 @subsection typedef arelent
23 This is the structure of a relocation entry:
26 @example
28 typedef enum bfd_reloc_status
29 @{
30 /* No errors detected. */
31 bfd_reloc_ok,
33 /* The relocation was performed, but there was an overflow. */
34 bfd_reloc_overflow,
36 /* The address to relocate was not within the section supplied. */
37 bfd_reloc_outofrange,
39 /* Used by special functions. */
40 bfd_reloc_continue,
42 /* Unsupported relocation size requested. */
43 bfd_reloc_notsupported,
45 /* Unused. */
46 bfd_reloc_other,
48 /* The symbol to relocate against was undefined. */
49 bfd_reloc_undefined,
51 /* The relocation was performed, but may not be ok - presently
52 generated only when linking i960 coff files with i960 b.out
53 symbols. If this type is returned, the error_message argument
54 to bfd_perform_relocation will be set. */
55 bfd_reloc_dangerous
56 @}
57 bfd_reloc_status_type;
60 typedef struct reloc_cache_entry
61 @{
62 /* A pointer into the canonical table of pointers. */
63 struct bfd_symbol **sym_ptr_ptr;
65 /* offset in section. */
66 bfd_size_type address;
68 /* addend for relocation value. */
69 bfd_vma addend;
71 /* Pointer to how to perform the required relocation. */
72 reloc_howto_type *howto;
74 @}
75 arelent;
77 @end example
78 @strong{Description}@*
79 Here is a description of each of the fields within an @code{arelent}:
81 @itemize @bullet
83 @item
84 @code{sym_ptr_ptr}
85 @end itemize
86 The symbol table pointer points to a pointer to the symbol
87 associated with the relocation request. It is the pointer
88 into the table returned by the back end's
89 @code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
90 referenced through a pointer to a pointer so that tools like
91 the linker can fix up all the symbols of the same name by
92 modifying only one pointer. The relocation routine looks in
93 the symbol and uses the base of the section the symbol is
94 attached to and the value of the symbol as the initial
95 relocation offset. If the symbol pointer is zero, then the
96 section provided is looked up.
98 @itemize @bullet
100 @item
101 @code{address}
102 @end itemize
103 The @code{address} field gives the offset in bytes from the base of
104 the section data which owns the relocation record to the first
105 byte of relocatable information. The actual data relocated
106 will be relative to this point; for example, a relocation
107 type which modifies the bottom two bytes of a four byte word
108 would not touch the first byte pointed to in a big endian
109 world.
111 @itemize @bullet
113 @item
114 @code{addend}
115 @end itemize
116 The @code{addend} is a value provided by the back end to be added (!)
117 to the relocation offset. Its interpretation is dependent upon
118 the howto. For example, on the 68k the code:
120 @example
121 char foo[];
122 main()
123 @{
124 return foo[0x12345678];
125 @}
126 @end example
128 Could be compiled into:
130 @example
131 linkw fp,#-4
132 moveb @@#12345678,d0
133 extbl d0
134 unlk fp
135 rts
136 @end example
138 This could create a reloc pointing to @code{foo}, but leave the
139 offset in the data, something like:
141 @example
142 RELOCATION RECORDS FOR [.text]:
143 offset type value
144 00000006 32 _foo
146 00000000 4e56 fffc ; linkw fp,#-4
147 00000004 1039 1234 5678 ; moveb @@#12345678,d0
148 0000000a 49c0 ; extbl d0
149 0000000c 4e5e ; unlk fp
150 0000000e 4e75 ; rts
151 @end example
153 Using coff and an 88k, some instructions don't have enough
154 space in them to represent the full address range, and
155 pointers have to be loaded in two parts. So you'd get something like:
157 @example
158 or.u r13,r0,hi16(_foo+0x12345678)
159 ld.b r2,r13,lo16(_foo+0x12345678)
160 jmp r1
161 @end example
163 This should create two relocs, both pointing to @code{_foo}, and with
164 0x12340000 in their addend field. The data would consist of:
166 @example
167 RELOCATION RECORDS FOR [.text]:
168 offset type value
169 00000002 HVRT16 _foo+0x12340000
170 00000006 LVRT16 _foo+0x12340000
172 00000000 5da05678 ; or.u r13,r0,0x5678
173 00000004 1c4d5678 ; ld.b r2,r13,0x5678
174 00000008 f400c001 ; jmp r1
175 @end example
177 The relocation routine digs out the value from the data, adds
178 it to the addend to get the original offset, and then adds the
179 value of @code{_foo}. Note that all 32 bits have to be kept around
180 somewhere, to cope with carry from bit 15 to bit 16.
182 One further example is the sparc and the a.out format. The
183 sparc has a similar problem to the 88k, in that some
184 instructions don't have room for an entire offset, but on the
185 sparc the parts are created in odd sized lumps. The designers of
186 the a.out format chose to not use the data within the section
187 for storing part of the offset; all the offset is kept within
188 the reloc. Anything in the data should be ignored.
190 @example
191 save %sp,-112,%sp
192 sethi %hi(_foo+0x12345678),%g2
193 ldsb [%g2+%lo(_foo+0x12345678)],%i0
194 ret
195 restore
196 @end example
198 Both relocs contain a pointer to @code{foo}, and the offsets
199 contain junk.
201 @example
202 RELOCATION RECORDS FOR [.text]:
203 offset type value
204 00000004 HI22 _foo+0x12345678
205 00000008 LO10 _foo+0x12345678
207 00000000 9de3bf90 ; save %sp,-112,%sp
208 00000004 05000000 ; sethi %hi(_foo+0),%g2
209 00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
210 0000000c 81c7e008 ; ret
211 00000010 81e80000 ; restore
212 @end example
214 @itemize @bullet
216 @item
217 @code{howto}
218 @end itemize
219 The @code{howto} field can be imagined as a
220 relocation instruction. It is a pointer to a structure which
221 contains information on what to do with all of the other
222 information in the reloc record and data section. A back end
223 would normally have a relocation instruction set and turn
224 relocations into pointers to the correct structure on input -
225 but it would be possible to create each howto field on demand.
227 @subsubsection @code{enum complain_overflow}
228 Indicates what sort of overflow checking should be done when
229 performing a relocation.
232 @example
234 enum complain_overflow
235 @{
236 /* Do not complain on overflow. */
237 complain_overflow_dont,
239 /* Complain if the value overflows when considered as a signed
240 number one bit larger than the field. ie. A bitfield of N bits
241 is allowed to represent -2**n to 2**n-1. */
242 complain_overflow_bitfield,
244 /* Complain if the value overflows when considered as a signed
245 number. */
246 complain_overflow_signed,
248 /* Complain if the value overflows when considered as an
249 unsigned number. */
250 complain_overflow_unsigned
251 @};
252 @end example
253 @subsubsection @code{reloc_howto_type}
254 The @code{reloc_howto_type} is a structure which contains all the
255 information that libbfd needs to know to tie up a back end's data.
258 @example
259 struct bfd_symbol; /* Forward declaration. */
261 struct reloc_howto_struct
262 @{
263 /* The type field has mainly a documentary use - the back end can
264 do what it wants with it, though normally the back end's
265 external idea of what a reloc number is stored
266 in this field. For example, a PC relative word relocation
267 in a coff environment has the type 023 - because that's
268 what the outside world calls a R_PCRWORD reloc. */
269 unsigned int type;
271 /* The value the final relocation is shifted right by. This drops
272 unwanted data from the relocation. */
273 unsigned int rightshift;
275 /* The size of the item to be relocated. This is *not* a
276 power-of-two measure. To get the number of bytes operated
277 on by a type of relocation, use bfd_get_reloc_size. */
278 int size;
280 /* The number of bits in the item to be relocated. This is used
281 when doing overflow checking. */
282 unsigned int bitsize;
284 /* Notes that the relocation is relative to the location in the
285 data section of the addend. The relocation function will
286 subtract from the relocation value the address of the location
287 being relocated. */
288 bfd_boolean pc_relative;
290 /* The bit position of the reloc value in the destination.
291 The relocated value is left shifted by this amount. */
292 unsigned int bitpos;
294 /* What type of overflow error should be checked for when
295 relocating. */
296 enum complain_overflow complain_on_overflow;
298 /* If this field is non null, then the supplied function is
299 called rather than the normal function. This allows really
300 strange relocation methods to be accommodated (e.g., i960 callj
301 instructions). */
302 bfd_reloc_status_type (*special_function)
303 (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
304 bfd *, char **);
306 /* The textual name of the relocation type. */
307 char *name;
309 /* Some formats record a relocation addend in the section contents
310 rather than with the relocation. For ELF formats this is the
311 distinction between USE_REL and USE_RELA (though the code checks
312 for USE_REL == 1/0). The value of this field is TRUE if the
313 addend is recorded with the section contents; when performing a
314 partial link (ld -r) the section contents (the data) will be
315 modified. The value of this field is FALSE if addends are
316 recorded with the relocation (in arelent.addend); when performing
317 a partial link the relocation will be modified.
318 All relocations for all ELF USE_RELA targets should set this field
319 to FALSE (values of TRUE should be looked on with suspicion).
320 However, the converse is not true: not all relocations of all ELF
321 USE_REL targets set this field to TRUE. Why this is so is peculiar
322 to each particular target. For relocs that aren't used in partial
323 links (e.g. GOT stuff) it doesn't matter what this is set to. */
324 bfd_boolean partial_inplace;
326 /* src_mask selects the part of the instruction (or data) to be used
327 in the relocation sum. If the target relocations don't have an
328 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
329 dst_mask to extract the addend from the section contents. If
330 relocations do have an addend in the reloc, eg. ELF USE_RELA, this
331 field should be zero. Non-zero values for ELF USE_RELA targets are
332 bogus as in those cases the value in the dst_mask part of the
333 section contents should be treated as garbage. */
334 bfd_vma src_mask;
336 /* dst_mask selects which parts of the instruction (or data) are
337 replaced with a relocated value. */
338 bfd_vma dst_mask;
340 /* When some formats create PC relative instructions, they leave
341 the value of the pc of the place being relocated in the offset
342 slot of the instruction, so that a PC relative relocation can
343 be made just by adding in an ordinary offset (e.g., sun3 a.out).
344 Some formats leave the displacement part of an instruction
345 empty (e.g., m88k bcs); this flag signals the fact. */
346 bfd_boolean pcrel_offset;
347 @};
349 @end example
350 @findex The HOWTO Macro
351 @subsubsection @code{The HOWTO Macro}
352 @strong{Description}@*
353 The HOWTO define is horrible and will go away.
354 @example
355 #define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
356 @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
357 @end example
359 @strong{Description}@*
360 And will be replaced with the totally magic way. But for the
361 moment, we are compatible, so do it this way.
362 @example
363 #define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
364 HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
365 NAME, FALSE, 0, 0, IN)
367 @end example
369 @strong{Description}@*
370 This is used to fill in an empty howto entry in an array.
371 @example
372 #define EMPTY_HOWTO(C) \
373 HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
374 NULL, FALSE, 0, 0, FALSE)
376 @end example
378 @strong{Description}@*
379 Helper routine to turn a symbol into a relocation value.
380 @example
381 #define HOWTO_PREPARE(relocation, symbol) \
382 @{ \
383 if (symbol != NULL) \
384 @{ \
385 if (bfd_is_com_section (symbol->section)) \
386 @{ \
387 relocation = 0; \
388 @} \
389 else \
390 @{ \
391 relocation = symbol->value; \
392 @} \
393 @} \
394 @}
396 @end example
398 @findex bfd_get_reloc_size
399 @subsubsection @code{bfd_get_reloc_size}
400 @strong{Synopsis}
401 @example
402 unsigned int bfd_get_reloc_size (reloc_howto_type *);
403 @end example
404 @strong{Description}@*
405 For a reloc_howto_type that operates on a fixed number of bytes,
406 this returns the number of bytes operated on.
408 @findex arelent_chain
409 @subsubsection @code{arelent_chain}
410 @strong{Description}@*
411 How relocs are tied together in an @code{asection}:
412 @example
413 typedef struct relent_chain
414 @{
415 arelent relent;
416 struct relent_chain *next;
417 @}
418 arelent_chain;
420 @end example
422 @findex bfd_check_overflow
423 @subsubsection @code{bfd_check_overflow}
424 @strong{Synopsis}
425 @example
426 bfd_reloc_status_type bfd_check_overflow
427 (enum complain_overflow how,
428 unsigned int bitsize,
429 unsigned int rightshift,
430 unsigned int addrsize,
431 bfd_vma relocation);
432 @end example
433 @strong{Description}@*
434 Perform overflow checking on @var{relocation} which has
435 @var{bitsize} significant bits and will be shifted right by
436 @var{rightshift} bits, on a machine with addresses containing
437 @var{addrsize} significant bits. The result is either of
438 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
440 @findex bfd_perform_relocation
441 @subsubsection @code{bfd_perform_relocation}
442 @strong{Synopsis}
443 @example
444 bfd_reloc_status_type bfd_perform_relocation
445 (bfd *abfd,
446 arelent *reloc_entry,
447 void *data,
448 asection *input_section,
449 bfd *output_bfd,
450 char **error_message);
451 @end example
452 @strong{Description}@*
453 If @var{output_bfd} is supplied to this function, the
454 generated image will be relocatable; the relocations are
455 copied to the output file after they have been changed to
456 reflect the new state of the world. There are two ways of
457 reflecting the results of partial linkage in an output file:
458 by modifying the output data in place, and by modifying the
459 relocation record. Some native formats (e.g., basic a.out and
460 basic coff) have no way of specifying an addend in the
461 relocation type, so the addend has to go in the output data.
462 This is no big deal since in these formats the output data
463 slot will always be big enough for the addend. Complex reloc
464 types with addends were invented to solve just this problem.
465 The @var{error_message} argument is set to an error message if
466 this return @code{bfd_reloc_dangerous}.
468 @findex bfd_install_relocation
469 @subsubsection @code{bfd_install_relocation}
470 @strong{Synopsis}
471 @example
472 bfd_reloc_status_type bfd_install_relocation
473 (bfd *abfd,
474 arelent *reloc_entry,
475 void *data, bfd_vma data_start,
476 asection *input_section,
477 char **error_message);
478 @end example
479 @strong{Description}@*
480 This looks remarkably like @code{bfd_perform_relocation}, except it
481 does not expect that the section contents have been filled in.
482 I.e., it's suitable for use when creating, rather than applying
483 a relocation.
485 For now, this function should be considered reserved for the
486 assembler.
489 @node howto manager, , typedef arelent, Relocations
490 @subsection The howto manager
491 When an application wants to create a relocation, but doesn't
492 know what the target machine might call it, it can find out by
493 using this bit of code.
495 @findex bfd_reloc_code_type
496 @subsubsection @code{bfd_reloc_code_type}
497 @strong{Description}@*
498 The insides of a reloc code. The idea is that, eventually, there
499 will be one enumerator for every type of relocation we ever do.
500 Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
501 return a howto pointer.
503 This does mean that the application must determine the correct
504 enumerator value; you can't get a howto pointer from a random set
505 of attributes.
507 Here are the possible values for @code{enum bfd_reloc_code_real}:
509 @deffn {} BFD_RELOC_64
510 @deffnx {} BFD_RELOC_32
511 @deffnx {} BFD_RELOC_26
512 @deffnx {} BFD_RELOC_24
513 @deffnx {} BFD_RELOC_16
514 @deffnx {} BFD_RELOC_14
515 @deffnx {} BFD_RELOC_8
516 Basic absolute relocations of N bits.
517 @end deffn
518 @deffn {} BFD_RELOC_64_PCREL
519 @deffnx {} BFD_RELOC_32_PCREL
520 @deffnx {} BFD_RELOC_24_PCREL
521 @deffnx {} BFD_RELOC_16_PCREL
522 @deffnx {} BFD_RELOC_12_PCREL
523 @deffnx {} BFD_RELOC_8_PCREL
524 PC-relative relocations. Sometimes these are relative to the address
525 of the relocation itself; sometimes they are relative to the start of
526 the section containing the relocation. It depends on the specific target.
528 The 24-bit relocation is used in some Intel 960 configurations.
529 @end deffn
530 @deffn {} BFD_RELOC_32_SECREL
531 Section relative relocations. Some targets need this for DWARF2.
532 @end deffn
533 @deffn {} BFD_RELOC_32_GOT_PCREL
534 @deffnx {} BFD_RELOC_16_GOT_PCREL
535 @deffnx {} BFD_RELOC_8_GOT_PCREL
536 @deffnx {} BFD_RELOC_32_GOTOFF
537 @deffnx {} BFD_RELOC_16_GOTOFF
538 @deffnx {} BFD_RELOC_LO16_GOTOFF
539 @deffnx {} BFD_RELOC_HI16_GOTOFF
540 @deffnx {} BFD_RELOC_HI16_S_GOTOFF
541 @deffnx {} BFD_RELOC_8_GOTOFF
542 @deffnx {} BFD_RELOC_64_PLT_PCREL
543 @deffnx {} BFD_RELOC_32_PLT_PCREL
544 @deffnx {} BFD_RELOC_24_PLT_PCREL
545 @deffnx {} BFD_RELOC_16_PLT_PCREL
546 @deffnx {} BFD_RELOC_8_PLT_PCREL
547 @deffnx {} BFD_RELOC_64_PLTOFF
548 @deffnx {} BFD_RELOC_32_PLTOFF
549 @deffnx {} BFD_RELOC_16_PLTOFF
550 @deffnx {} BFD_RELOC_LO16_PLTOFF
551 @deffnx {} BFD_RELOC_HI16_PLTOFF
552 @deffnx {} BFD_RELOC_HI16_S_PLTOFF
553 @deffnx {} BFD_RELOC_8_PLTOFF
554 For ELF.
555 @end deffn
556 @deffn {} BFD_RELOC_68K_GLOB_DAT
557 @deffnx {} BFD_RELOC_68K_JMP_SLOT
558 @deffnx {} BFD_RELOC_68K_RELATIVE
559 Relocations used by 68K ELF.
560 @end deffn
561 @deffn {} BFD_RELOC_32_BASEREL
562 @deffnx {} BFD_RELOC_16_BASEREL
563 @deffnx {} BFD_RELOC_LO16_BASEREL
564 @deffnx {} BFD_RELOC_HI16_BASEREL
565 @deffnx {} BFD_RELOC_HI16_S_BASEREL
566 @deffnx {} BFD_RELOC_8_BASEREL
567 @deffnx {} BFD_RELOC_RVA
568 Linkage-table relative.
569 @end deffn
570 @deffn {} BFD_RELOC_8_FFnn
571 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
572 @end deffn
573 @deffn {} BFD_RELOC_32_PCREL_S2
574 @deffnx {} BFD_RELOC_16_PCREL_S2
575 @deffnx {} BFD_RELOC_23_PCREL_S2
576 These PC-relative relocations are stored as word displacements --
577 i.e., byte displacements shifted right two bits. The 30-bit word
578 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
579 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
580 signed 16-bit displacement is used on the MIPS, and the 23-bit
581 displacement is used on the Alpha.
582 @end deffn
583 @deffn {} BFD_RELOC_HI22
584 @deffnx {} BFD_RELOC_LO10
585 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
586 the target word. These are used on the SPARC.
587 @end deffn
588 @deffn {} BFD_RELOC_GPREL16
589 @deffnx {} BFD_RELOC_GPREL32
590 For systems that allocate a Global Pointer register, these are
591 displacements off that register. These relocation types are
592 handled specially, because the value the register will have is
593 decided relatively late.
594 @end deffn
595 @deffn {} BFD_RELOC_I960_CALLJ
596 Reloc types used for i960/b.out.
597 @end deffn
598 @deffn {} BFD_RELOC_NONE
599 @deffnx {} BFD_RELOC_SPARC_WDISP22
600 @deffnx {} BFD_RELOC_SPARC22
601 @deffnx {} BFD_RELOC_SPARC13
602 @deffnx {} BFD_RELOC_SPARC_GOT10
603 @deffnx {} BFD_RELOC_SPARC_GOT13
604 @deffnx {} BFD_RELOC_SPARC_GOT22
605 @deffnx {} BFD_RELOC_SPARC_PC10
606 @deffnx {} BFD_RELOC_SPARC_PC22
607 @deffnx {} BFD_RELOC_SPARC_WPLT30
608 @deffnx {} BFD_RELOC_SPARC_COPY
609 @deffnx {} BFD_RELOC_SPARC_GLOB_DAT
610 @deffnx {} BFD_RELOC_SPARC_JMP_SLOT
611 @deffnx {} BFD_RELOC_SPARC_RELATIVE
612 @deffnx {} BFD_RELOC_SPARC_UA16
613 @deffnx {} BFD_RELOC_SPARC_UA32
614 @deffnx {} BFD_RELOC_SPARC_UA64
615 @deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22
616 @deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10
617 @deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22
618 @deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10
619 @deffnx {} BFD_RELOC_SPARC_GOTDATA_OP
620 SPARC ELF relocations. There is probably some overlap with other
621 relocation types already defined.
622 @end deffn
623 @deffn {} BFD_RELOC_SPARC_BASE13
624 @deffnx {} BFD_RELOC_SPARC_BASE22
625 I think these are specific to SPARC a.out (e.g., Sun 4).
626 @end deffn
627 @deffn {} BFD_RELOC_SPARC_64
628 @deffnx {} BFD_RELOC_SPARC_10
629 @deffnx {} BFD_RELOC_SPARC_11
630 @deffnx {} BFD_RELOC_SPARC_OLO10
631 @deffnx {} BFD_RELOC_SPARC_HH22
632 @deffnx {} BFD_RELOC_SPARC_HM10
633 @deffnx {} BFD_RELOC_SPARC_LM22
634 @deffnx {} BFD_RELOC_SPARC_PC_HH22
635 @deffnx {} BFD_RELOC_SPARC_PC_HM10
636 @deffnx {} BFD_RELOC_SPARC_PC_LM22
637 @deffnx {} BFD_RELOC_SPARC_WDISP16
638 @deffnx {} BFD_RELOC_SPARC_WDISP19
639 @deffnx {} BFD_RELOC_SPARC_7
640 @deffnx {} BFD_RELOC_SPARC_6
641 @deffnx {} BFD_RELOC_SPARC_5
642 @deffnx {} BFD_RELOC_SPARC_DISP64
643 @deffnx {} BFD_RELOC_SPARC_PLT32
644 @deffnx {} BFD_RELOC_SPARC_PLT64
645 @deffnx {} BFD_RELOC_SPARC_HIX22
646 @deffnx {} BFD_RELOC_SPARC_LOX10
647 @deffnx {} BFD_RELOC_SPARC_H44
648 @deffnx {} BFD_RELOC_SPARC_M44
649 @deffnx {} BFD_RELOC_SPARC_L44
650 @deffnx {} BFD_RELOC_SPARC_REGISTER
651 SPARC64 relocations
652 @end deffn
653 @deffn {} BFD_RELOC_SPARC_REV32
654 SPARC little endian relocation
655 @end deffn
656 @deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
657 @deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
658 @deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
659 @deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
660 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
661 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
662 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
663 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
664 @deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
665 @deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
666 @deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
667 @deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
668 @deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
669 @deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
670 @deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
671 @deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
672 @deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
673 @deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
674 @deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
675 @deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
676 @deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
677 @deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
678 @deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
679 @deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
680 SPARC TLS relocations
681 @end deffn
682 @deffn {} BFD_RELOC_SPU_IMM7
683 @deffnx {} BFD_RELOC_SPU_IMM8
684 @deffnx {} BFD_RELOC_SPU_IMM10
685 @deffnx {} BFD_RELOC_SPU_IMM10W
686 @deffnx {} BFD_RELOC_SPU_IMM16
687 @deffnx {} BFD_RELOC_SPU_IMM16W
688 @deffnx {} BFD_RELOC_SPU_IMM18
689 @deffnx {} BFD_RELOC_SPU_PCREL9a
690 @deffnx {} BFD_RELOC_SPU_PCREL9b
691 @deffnx {} BFD_RELOC_SPU_PCREL16
692 @deffnx {} BFD_RELOC_SPU_LO16
693 @deffnx {} BFD_RELOC_SPU_HI16
694 @deffnx {} BFD_RELOC_SPU_PPU32
695 @deffnx {} BFD_RELOC_SPU_PPU64
696 SPU Relocations.
697 @end deffn
698 @deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
699 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
700 "addend" in some special way.
701 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
702 writing; when reading, it will be the absolute section symbol. The
703 addend is the displacement in bytes of the "lda" instruction from
704 the "ldah" instruction (which is at the address of this reloc).
705 @end deffn
706 @deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
707 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
708 with GPDISP_HI16 relocs. The addend is ignored when writing the
709 relocations out, and is filled in with the file's GP value on
710 reading, for convenience.
711 @end deffn
712 @deffn {} BFD_RELOC_ALPHA_GPDISP
713 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
714 relocation except that there is no accompanying GPDISP_LO16
715 relocation.
716 @end deffn
717 @deffn {} BFD_RELOC_ALPHA_LITERAL
718 @deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
719 @deffnx {} BFD_RELOC_ALPHA_LITUSE
720 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
721 the assembler turns it into a LDQ instruction to load the address of
722 the symbol, and then fills in a register in the real instruction.
724 The LITERAL reloc, at the LDQ instruction, refers to the .lita
725 section symbol. The addend is ignored when writing, but is filled
726 in with the file's GP value on reading, for convenience, as with the
727 GPDISP_LO16 reloc.
729 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
730 It should refer to the symbol to be referenced, as with 16_GOTOFF,
731 but it generates output not based on the position within the .got
732 section, but relative to the GP value chosen for the file during the
733 final link stage.
735 The LITUSE reloc, on the instruction using the loaded address, gives
736 information to the linker that it might be able to use to optimize
737 away some literal section references. The symbol is ignored (read
738 as the absolute section symbol), and the "addend" indicates the type
739 of instruction using the register:
740 1 - "memory" fmt insn
741 2 - byte-manipulation (byte offset reg)
742 3 - jsr (target of branch)
743 @end deffn
744 @deffn {} BFD_RELOC_ALPHA_HINT
745 The HINT relocation indicates a value that should be filled into the
746 "hint" field of a jmp/jsr/ret instruction, for possible branch-
747 prediction logic which may be provided on some processors.
748 @end deffn
749 @deffn {} BFD_RELOC_ALPHA_LINKAGE
750 The LINKAGE relocation outputs a linkage pair in the object file,
751 which is filled by the linker.
752 @end deffn
753 @deffn {} BFD_RELOC_ALPHA_CODEADDR
754 The CODEADDR relocation outputs a STO_CA in the object file,
755 which is filled by the linker.
756 @end deffn
757 @deffn {} BFD_RELOC_ALPHA_GPREL_HI16
758 @deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
759 The GPREL_HI/LO relocations together form a 32-bit offset from the
760 GP register.
761 @end deffn
762 @deffn {} BFD_RELOC_ALPHA_BRSGP
763 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
764 share a common GP, and the target address is adjusted for
765 STO_ALPHA_STD_GPLOAD.
766 @end deffn
767 @deffn {} BFD_RELOC_ALPHA_TLSGD
768 @deffnx {} BFD_RELOC_ALPHA_TLSLDM
769 @deffnx {} BFD_RELOC_ALPHA_DTPMOD64
770 @deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
771 @deffnx {} BFD_RELOC_ALPHA_DTPREL64
772 @deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
773 @deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
774 @deffnx {} BFD_RELOC_ALPHA_DTPREL16
775 @deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
776 @deffnx {} BFD_RELOC_ALPHA_TPREL64
777 @deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
778 @deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
779 @deffnx {} BFD_RELOC_ALPHA_TPREL16
780 Alpha thread-local storage relocations.
781 @end deffn
782 @deffn {} BFD_RELOC_MIPS_JMP
783 Bits 27..2 of the relocation address shifted right 2 bits;
784 simple reloc otherwise.
785 @end deffn
786 @deffn {} BFD_RELOC_MIPS16_JMP
787 The MIPS16 jump instruction.
788 @end deffn
789 @deffn {} BFD_RELOC_MIPS16_GPREL
790 MIPS16 GP relative reloc.
791 @end deffn
792 @deffn {} BFD_RELOC_HI16
793 High 16 bits of 32-bit value; simple reloc.
794 @end deffn
795 @deffn {} BFD_RELOC_HI16_S
796 High 16 bits of 32-bit value but the low 16 bits will be sign
797 extended and added to form the final result. If the low 16
798 bits form a negative number, we need to add one to the high value
799 to compensate for the borrow when the low bits are added.
800 @end deffn
801 @deffn {} BFD_RELOC_LO16
802 Low 16 bits.
803 @end deffn
804 @deffn {} BFD_RELOC_HI16_PCREL
805 High 16 bits of 32-bit pc-relative value
806 @end deffn
807 @deffn {} BFD_RELOC_HI16_S_PCREL
808 High 16 bits of 32-bit pc-relative value, adjusted
809 @end deffn
810 @deffn {} BFD_RELOC_LO16_PCREL
811 Low 16 bits of pc-relative value
812 @end deffn
813 @deffn {} BFD_RELOC_MIPS16_GOT16
814 @deffnx {} BFD_RELOC_MIPS16_CALL16
815 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
816 16-bit immediate fields
817 @end deffn
818 @deffn {} BFD_RELOC_MIPS16_HI16
819 MIPS16 high 16 bits of 32-bit value.
820 @end deffn
821 @deffn {} BFD_RELOC_MIPS16_HI16_S
822 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
823 extended and added to form the final result. If the low 16
824 bits form a negative number, we need to add one to the high value
825 to compensate for the borrow when the low bits are added.
826 @end deffn
827 @deffn {} BFD_RELOC_MIPS16_LO16
828 MIPS16 low 16 bits.
829 @end deffn
830 @deffn {} BFD_RELOC_MIPS_LITERAL
831 Relocation against a MIPS literal section.
832 @end deffn
833 @deffn {} BFD_RELOC_MIPS_GOT16
834 @deffnx {} BFD_RELOC_MIPS_CALL16
835 @deffnx {} BFD_RELOC_MIPS_GOT_HI16
836 @deffnx {} BFD_RELOC_MIPS_GOT_LO16
837 @deffnx {} BFD_RELOC_MIPS_CALL_HI16
838 @deffnx {} BFD_RELOC_MIPS_CALL_LO16
839 @deffnx {} BFD_RELOC_MIPS_SUB
840 @deffnx {} BFD_RELOC_MIPS_GOT_PAGE
841 @deffnx {} BFD_RELOC_MIPS_GOT_OFST
842 @deffnx {} BFD_RELOC_MIPS_GOT_DISP
843 @deffnx {} BFD_RELOC_MIPS_SHIFT5
844 @deffnx {} BFD_RELOC_MIPS_SHIFT6
845 @deffnx {} BFD_RELOC_MIPS_INSERT_A
846 @deffnx {} BFD_RELOC_MIPS_INSERT_B
847 @deffnx {} BFD_RELOC_MIPS_DELETE
848 @deffnx {} BFD_RELOC_MIPS_HIGHEST
849 @deffnx {} BFD_RELOC_MIPS_HIGHER
850 @deffnx {} BFD_RELOC_MIPS_SCN_DISP
851 @deffnx {} BFD_RELOC_MIPS_REL16
852 @deffnx {} BFD_RELOC_MIPS_RELGOT
853 @deffnx {} BFD_RELOC_MIPS_JALR
854 @deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32
855 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32
856 @deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64
857 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64
858 @deffnx {} BFD_RELOC_MIPS_TLS_GD
859 @deffnx {} BFD_RELOC_MIPS_TLS_LDM
860 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16
861 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16
862 @deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL
863 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL32
864 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL64
865 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16
866 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16
867 MIPS ELF relocations.
868 @end deffn
869 @deffn {} BFD_RELOC_MIPS_COPY
870 @deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
871 MIPS ELF relocations (VxWorks and PLT extensions).
872 @end deffn
873 @deffn {} BFD_RELOC_FRV_LABEL16
874 @deffnx {} BFD_RELOC_FRV_LABEL24
875 @deffnx {} BFD_RELOC_FRV_LO16
876 @deffnx {} BFD_RELOC_FRV_HI16
877 @deffnx {} BFD_RELOC_FRV_GPREL12
878 @deffnx {} BFD_RELOC_FRV_GPRELU12
879 @deffnx {} BFD_RELOC_FRV_GPREL32
880 @deffnx {} BFD_RELOC_FRV_GPRELHI
881 @deffnx {} BFD_RELOC_FRV_GPRELLO
882 @deffnx {} BFD_RELOC_FRV_GOT12
883 @deffnx {} BFD_RELOC_FRV_GOTHI
884 @deffnx {} BFD_RELOC_FRV_GOTLO
885 @deffnx {} BFD_RELOC_FRV_FUNCDESC
886 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
887 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
888 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
889 @deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
890 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
891 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
892 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
893 @deffnx {} BFD_RELOC_FRV_GOTOFF12
894 @deffnx {} BFD_RELOC_FRV_GOTOFFHI
895 @deffnx {} BFD_RELOC_FRV_GOTOFFLO
896 @deffnx {} BFD_RELOC_FRV_GETTLSOFF
897 @deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE
898 @deffnx {} BFD_RELOC_FRV_GOTTLSDESC12
899 @deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI
900 @deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO
901 @deffnx {} BFD_RELOC_FRV_TLSMOFF12
902 @deffnx {} BFD_RELOC_FRV_TLSMOFFHI
903 @deffnx {} BFD_RELOC_FRV_TLSMOFFLO
904 @deffnx {} BFD_RELOC_FRV_GOTTLSOFF12
905 @deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI
906 @deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO
907 @deffnx {} BFD_RELOC_FRV_TLSOFF
908 @deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX
909 @deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX
910 @deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX
911 @deffnx {} BFD_RELOC_FRV_TLSMOFF
912 Fujitsu Frv Relocations.
913 @end deffn
914 @deffn {} BFD_RELOC_MN10300_GOTOFF24
915 This is a 24bit GOT-relative reloc for the mn10300.
916 @end deffn
917 @deffn {} BFD_RELOC_MN10300_GOT32
918 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
919 in the instruction.
920 @end deffn
921 @deffn {} BFD_RELOC_MN10300_GOT24
922 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
923 in the instruction.
924 @end deffn
925 @deffn {} BFD_RELOC_MN10300_GOT16
926 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
927 in the instruction.
928 @end deffn
929 @deffn {} BFD_RELOC_MN10300_COPY
930 Copy symbol at runtime.
931 @end deffn
932 @deffn {} BFD_RELOC_MN10300_GLOB_DAT
933 Create GOT entry.
934 @end deffn
935 @deffn {} BFD_RELOC_MN10300_JMP_SLOT
936 Create PLT entry.
937 @end deffn
938 @deffn {} BFD_RELOC_MN10300_RELATIVE
939 Adjust by program base.
940 @end deffn
941 @deffn {} BFD_RELOC_MN10300_SYM_DIFF
942 Together with another reloc targeted at the same location,
943 allows for a value that is the difference of two symbols
944 in the same section.
945 @end deffn
946 @deffn {} BFD_RELOC_MN10300_ALIGN
947 The addend of this reloc is an alignment power that must
948 be honoured at the offset's location, regardless of linker
949 relaxation.
950 @end deffn
951 @deffn {} BFD_RELOC_386_GOT32
952 @deffnx {} BFD_RELOC_386_PLT32
953 @deffnx {} BFD_RELOC_386_COPY
954 @deffnx {} BFD_RELOC_386_GLOB_DAT
955 @deffnx {} BFD_RELOC_386_JUMP_SLOT
956 @deffnx {} BFD_RELOC_386_RELATIVE
957 @deffnx {} BFD_RELOC_386_GOTOFF
958 @deffnx {} BFD_RELOC_386_GOTPC
959 @deffnx {} BFD_RELOC_386_TLS_TPOFF
960 @deffnx {} BFD_RELOC_386_TLS_IE
961 @deffnx {} BFD_RELOC_386_TLS_GOTIE
962 @deffnx {} BFD_RELOC_386_TLS_LE
963 @deffnx {} BFD_RELOC_386_TLS_GD
964 @deffnx {} BFD_RELOC_386_TLS_LDM
965 @deffnx {} BFD_RELOC_386_TLS_LDO_32
966 @deffnx {} BFD_RELOC_386_TLS_IE_32
967 @deffnx {} BFD_RELOC_386_TLS_LE_32
968 @deffnx {} BFD_RELOC_386_TLS_DTPMOD32
969 @deffnx {} BFD_RELOC_386_TLS_DTPOFF32
970 @deffnx {} BFD_RELOC_386_TLS_TPOFF32
971 @deffnx {} BFD_RELOC_386_TLS_GOTDESC
972 @deffnx {} BFD_RELOC_386_TLS_DESC_CALL
973 @deffnx {} BFD_RELOC_386_TLS_DESC
974 i386/elf relocations
975 @end deffn
976 @deffn {} BFD_RELOC_X86_64_GOT32
977 @deffnx {} BFD_RELOC_X86_64_PLT32
978 @deffnx {} BFD_RELOC_X86_64_COPY
979 @deffnx {} BFD_RELOC_X86_64_GLOB_DAT
980 @deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
981 @deffnx {} BFD_RELOC_X86_64_RELATIVE
982 @deffnx {} BFD_RELOC_X86_64_GOTPCREL
983 @deffnx {} BFD_RELOC_X86_64_32S
984 @deffnx {} BFD_RELOC_X86_64_DTPMOD64
985 @deffnx {} BFD_RELOC_X86_64_DTPOFF64
986 @deffnx {} BFD_RELOC_X86_64_TPOFF64
987 @deffnx {} BFD_RELOC_X86_64_TLSGD
988 @deffnx {} BFD_RELOC_X86_64_TLSLD
989 @deffnx {} BFD_RELOC_X86_64_DTPOFF32
990 @deffnx {} BFD_RELOC_X86_64_GOTTPOFF
991 @deffnx {} BFD_RELOC_X86_64_TPOFF32
992 @deffnx {} BFD_RELOC_X86_64_GOTOFF64
993 @deffnx {} BFD_RELOC_X86_64_GOTPC32
994 @deffnx {} BFD_RELOC_X86_64_GOT64
995 @deffnx {} BFD_RELOC_X86_64_GOTPCREL64
996 @deffnx {} BFD_RELOC_X86_64_GOTPC64
997 @deffnx {} BFD_RELOC_X86_64_GOTPLT64
998 @deffnx {} BFD_RELOC_X86_64_PLTOFF64
999 @deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
1000 @deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
1001 @deffnx {} BFD_RELOC_X86_64_TLSDESC
1002 x86-64/elf relocations
1003 @end deffn
1004 @deffn {} BFD_RELOC_NS32K_IMM_8
1005 @deffnx {} BFD_RELOC_NS32K_IMM_16
1006 @deffnx {} BFD_RELOC_NS32K_IMM_32
1007 @deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
1008 @deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
1009 @deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
1010 @deffnx {} BFD_RELOC_NS32K_DISP_8
1011 @deffnx {} BFD_RELOC_NS32K_DISP_16
1012 @deffnx {} BFD_RELOC_NS32K_DISP_32
1013 @deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
1014 @deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
1015 @deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
1016 ns32k relocations
1017 @end deffn
1018 @deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
1019 @deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
1020 PDP11 relocations
1021 @end deffn
1022 @deffn {} BFD_RELOC_PJ_CODE_HI16
1023 @deffnx {} BFD_RELOC_PJ_CODE_LO16
1024 @deffnx {} BFD_RELOC_PJ_CODE_DIR16
1025 @deffnx {} BFD_RELOC_PJ_CODE_DIR32
1026 @deffnx {} BFD_RELOC_PJ_CODE_REL16
1027 @deffnx {} BFD_RELOC_PJ_CODE_REL32
1028 Picojava relocs. Not all of these appear in object files.
1029 @end deffn
1030 @deffn {} BFD_RELOC_PPC_B26
1031 @deffnx {} BFD_RELOC_PPC_BA26
1032 @deffnx {} BFD_RELOC_PPC_TOC16
1033 @deffnx {} BFD_RELOC_PPC_B16
1034 @deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
1035 @deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
1036 @deffnx {} BFD_RELOC_PPC_BA16
1037 @deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
1038 @deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
1039 @deffnx {} BFD_RELOC_PPC_COPY
1040 @deffnx {} BFD_RELOC_PPC_GLOB_DAT
1041 @deffnx {} BFD_RELOC_PPC_JMP_SLOT
1042 @deffnx {} BFD_RELOC_PPC_RELATIVE
1043 @deffnx {} BFD_RELOC_PPC_LOCAL24PC
1044 @deffnx {} BFD_RELOC_PPC_EMB_NADDR32
1045 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16
1046 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
1047 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
1048 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
1049 @deffnx {} BFD_RELOC_PPC_EMB_SDAI16
1050 @deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
1051 @deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
1052 @deffnx {} BFD_RELOC_PPC_EMB_SDA21
1053 @deffnx {} BFD_RELOC_PPC_EMB_MRKREF
1054 @deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
1055 @deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
1056 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
1057 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
1058 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
1059 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA
1060 @deffnx {} BFD_RELOC_PPC64_HIGHER
1061 @deffnx {} BFD_RELOC_PPC64_HIGHER_S
1062 @deffnx {} BFD_RELOC_PPC64_HIGHEST
1063 @deffnx {} BFD_RELOC_PPC64_HIGHEST_S
1064 @deffnx {} BFD_RELOC_PPC64_TOC16_LO
1065 @deffnx {} BFD_RELOC_PPC64_TOC16_HI
1066 @deffnx {} BFD_RELOC_PPC64_TOC16_HA
1067 @deffnx {} BFD_RELOC_PPC64_TOC
1068 @deffnx {} BFD_RELOC_PPC64_PLTGOT16
1069 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
1070 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
1071 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
1072 @deffnx {} BFD_RELOC_PPC64_ADDR16_DS
1073 @deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
1074 @deffnx {} BFD_RELOC_PPC64_GOT16_DS
1075 @deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
1076 @deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
1077 @deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
1078 @deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
1079 @deffnx {} BFD_RELOC_PPC64_TOC16_DS
1080 @deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
1081 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
1082 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
1083 Power(rs6000) and PowerPC relocations.
1084 @end deffn
1085 @deffn {} BFD_RELOC_PPC_TLS
1086 @deffnx {} BFD_RELOC_PPC_DTPMOD
1087 @deffnx {} BFD_RELOC_PPC_TPREL16
1088 @deffnx {} BFD_RELOC_PPC_TPREL16_LO
1089 @deffnx {} BFD_RELOC_PPC_TPREL16_HI
1090 @deffnx {} BFD_RELOC_PPC_TPREL16_HA
1091 @deffnx {} BFD_RELOC_PPC_TPREL
1092 @deffnx {} BFD_RELOC_PPC_DTPREL16
1093 @deffnx {} BFD_RELOC_PPC_DTPREL16_LO
1094 @deffnx {} BFD_RELOC_PPC_DTPREL16_HI
1095 @deffnx {} BFD_RELOC_PPC_DTPREL16_HA
1096 @deffnx {} BFD_RELOC_PPC_DTPREL
1097 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
1098 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
1099 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
1100 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
1101 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
1102 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
1103 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
1104 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
1105 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16
1106 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
1107 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
1108 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
1109 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
1110 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
1111 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
1112 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
1113 @deffnx {} BFD_RELOC_PPC64_TPREL16_DS
1114 @deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
1115 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
1116 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
1117 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
1118 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
1119 @deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
1120 @deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
1121 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
1122 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
1123 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
1124 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
1125 PowerPC and PowerPC64 thread-local storage relocations.
1126 @end deffn
1127 @deffn {} BFD_RELOC_I370_D12
1128 IBM 370/390 relocations
1129 @end deffn
1130 @deffn {} BFD_RELOC_CTOR
1131 The type of reloc used to build a constructor table - at the moment
1132 probably a 32 bit wide absolute relocation, but the target can choose.
1133 It generally does map to one of the other relocation types.
1134 @end deffn
1135 @deffn {} BFD_RELOC_ARM_PCREL_BRANCH
1136 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
1137 not stored in the instruction.
1138 @end deffn
1139 @deffn {} BFD_RELOC_ARM_PCREL_BLX
1140 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
1141 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
1142 field in the instruction.
1143 @end deffn
1144 @deffn {} BFD_RELOC_THUMB_PCREL_BLX
1145 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
1146 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
1147 field in the instruction.
1148 @end deffn
1149 @deffn {} BFD_RELOC_ARM_PCREL_CALL
1150 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
1151 @end deffn
1152 @deffn {} BFD_RELOC_ARM_PCREL_JUMP
1153 ARM 26-bit pc-relative branch for B or conditional BL instruction.
1154 @end deffn
1155 @deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7
1156 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9
1157 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1158 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20
1159 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1160 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25
1161 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
1162 The lowest bit must be zero and is not stored in the instruction.
1163 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
1164 "nn" one smaller in all cases. Note further that BRANCH23
1165 corresponds to R_ARM_THM_CALL.
1166 @end deffn
1167 @deffn {} BFD_RELOC_ARM_OFFSET_IMM
1168 12-bit immediate offset, used in ARM-format ldr and str instructions.
1169 @end deffn
1170 @deffn {} BFD_RELOC_ARM_THUMB_OFFSET
1171 5-bit immediate offset, used in Thumb-format ldr and str instructions.
1172 @end deffn
1173 @deffn {} BFD_RELOC_ARM_TARGET1
1174 Pc-relative or absolute relocation depending on target. Used for
1175 entries in .init_array sections.
1176 @end deffn
1177 @deffn {} BFD_RELOC_ARM_ROSEGREL32
1178 Read-only segment base relative address.
1179 @end deffn
1180 @deffn {} BFD_RELOC_ARM_SBREL32
1181 Data segment base relative address.
1182 @end deffn
1183 @deffn {} BFD_RELOC_ARM_TARGET2
1184 This reloc is used for references to RTTI data from exception handling
1185 tables. The actual definition depends on the target. It may be a
1186 pc-relative or some form of GOT-indirect relocation.
1187 @end deffn
1188 @deffn {} BFD_RELOC_ARM_PREL31
1189 31-bit PC relative address.
1190 @end deffn
1191 @deffn {} BFD_RELOC_ARM_MOVW
1192 @deffnx {} BFD_RELOC_ARM_MOVT
1193 @deffnx {} BFD_RELOC_ARM_MOVW_PCREL
1194 @deffnx {} BFD_RELOC_ARM_MOVT_PCREL
1195 @deffnx {} BFD_RELOC_ARM_THUMB_MOVW
1196 @deffnx {} BFD_RELOC_ARM_THUMB_MOVT
1197 @deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL
1198 @deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL
1199 Low and High halfword relocations for MOVW and MOVT instructions.
1200 @end deffn
1201 @deffn {} BFD_RELOC_ARM_JUMP_SLOT
1202 @deffnx {} BFD_RELOC_ARM_GLOB_DAT
1203 @deffnx {} BFD_RELOC_ARM_GOT32
1204 @deffnx {} BFD_RELOC_ARM_PLT32
1205 @deffnx {} BFD_RELOC_ARM_RELATIVE
1206 @deffnx {} BFD_RELOC_ARM_GOTOFF
1207 @deffnx {} BFD_RELOC_ARM_GOTPC
1208 Relocations for setting up GOTs and PLTs for shared libraries.
1209 @end deffn
1210 @deffn {} BFD_RELOC_ARM_TLS_GD32
1211 @deffnx {} BFD_RELOC_ARM_TLS_LDO32
1212 @deffnx {} BFD_RELOC_ARM_TLS_LDM32
1213 @deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32
1214 @deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32
1215 @deffnx {} BFD_RELOC_ARM_TLS_TPOFF32
1216 @deffnx {} BFD_RELOC_ARM_TLS_IE32
1217 @deffnx {} BFD_RELOC_ARM_TLS_LE32
1218 ARM thread-local storage relocations.
1219 @end deffn
1220 @deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC
1221 @deffnx {} BFD_RELOC_ARM_ALU_PC_G0
1222 @deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC
1223 @deffnx {} BFD_RELOC_ARM_ALU_PC_G1
1224 @deffnx {} BFD_RELOC_ARM_ALU_PC_G2
1225 @deffnx {} BFD_RELOC_ARM_LDR_PC_G0
1226 @deffnx {} BFD_RELOC_ARM_LDR_PC_G1
1227 @deffnx {} BFD_RELOC_ARM_LDR_PC_G2
1228 @deffnx {} BFD_RELOC_ARM_LDRS_PC_G0
1229 @deffnx {} BFD_RELOC_ARM_LDRS_PC_G1
1230 @deffnx {} BFD_RELOC_ARM_LDRS_PC_G2
1231 @deffnx {} BFD_RELOC_ARM_LDC_PC_G0
1232 @deffnx {} BFD_RELOC_ARM_LDC_PC_G1
1233 @deffnx {} BFD_RELOC_ARM_LDC_PC_G2
1234 @deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC
1235 @deffnx {} BFD_RELOC_ARM_ALU_SB_G0
1236 @deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC
1237 @deffnx {} BFD_RELOC_ARM_ALU_SB_G1
1238 @deffnx {} BFD_RELOC_ARM_ALU_SB_G2
1239 @deffnx {} BFD_RELOC_ARM_LDR_SB_G0
1240 @deffnx {} BFD_RELOC_ARM_LDR_SB_G1
1241 @deffnx {} BFD_RELOC_ARM_LDR_SB_G2
1242 @deffnx {} BFD_RELOC_ARM_LDRS_SB_G0
1243 @deffnx {} BFD_RELOC_ARM_LDRS_SB_G1
1244 @deffnx {} BFD_RELOC_ARM_LDRS_SB_G2
1245 @deffnx {} BFD_RELOC_ARM_LDC_SB_G0
1246 @deffnx {} BFD_RELOC_ARM_LDC_SB_G1
1247 @deffnx {} BFD_RELOC_ARM_LDC_SB_G2
1248 ARM group relocations.
1249 @end deffn
1250 @deffn {} BFD_RELOC_ARM_V4BX
1251 Annotation of BX instructions.
1252 @end deffn
1253 @deffn {} BFD_RELOC_ARM_IMMEDIATE
1254 @deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
1255 @deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
1256 @deffnx {} BFD_RELOC_ARM_T32_ADD_IMM
1257 @deffnx {} BFD_RELOC_ARM_T32_IMM12
1258 @deffnx {} BFD_RELOC_ARM_T32_ADD_PC12
1259 @deffnx {} BFD_RELOC_ARM_SHIFT_IMM
1260 @deffnx {} BFD_RELOC_ARM_SMC
1261 @deffnx {} BFD_RELOC_ARM_SWI
1262 @deffnx {} BFD_RELOC_ARM_MULTI
1263 @deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
1264 @deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
1265 @deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM
1266 @deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
1267 @deffnx {} BFD_RELOC_ARM_ADR_IMM
1268 @deffnx {} BFD_RELOC_ARM_LDR_IMM
1269 @deffnx {} BFD_RELOC_ARM_LITERAL
1270 @deffnx {} BFD_RELOC_ARM_IN_POOL
1271 @deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
1272 @deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8
1273 @deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM
1274 @deffnx {} BFD_RELOC_ARM_HWLITERAL
1275 @deffnx {} BFD_RELOC_ARM_THUMB_ADD
1276 @deffnx {} BFD_RELOC_ARM_THUMB_IMM
1277 @deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
1278 These relocs are only used within the ARM assembler. They are not
1279 (at present) written to any object files.
1280 @end deffn
1281 @deffn {} BFD_RELOC_SH_PCDISP8BY2
1282 @deffnx {} BFD_RELOC_SH_PCDISP12BY2
1283 @deffnx {} BFD_RELOC_SH_IMM3
1284 @deffnx {} BFD_RELOC_SH_IMM3U
1285 @deffnx {} BFD_RELOC_SH_DISP12
1286 @deffnx {} BFD_RELOC_SH_DISP12BY2
1287 @deffnx {} BFD_RELOC_SH_DISP12BY4
1288 @deffnx {} BFD_RELOC_SH_DISP12BY8
1289 @deffnx {} BFD_RELOC_SH_DISP20
1290 @deffnx {} BFD_RELOC_SH_DISP20BY8
1291 @deffnx {} BFD_RELOC_SH_IMM4
1292 @deffnx {} BFD_RELOC_SH_IMM4BY2
1293 @deffnx {} BFD_RELOC_SH_IMM4BY4
1294 @deffnx {} BFD_RELOC_SH_IMM8
1295 @deffnx {} BFD_RELOC_SH_IMM8BY2
1296 @deffnx {} BFD_RELOC_SH_IMM8BY4
1297 @deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
1298 @deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
1299 @deffnx {} BFD_RELOC_SH_SWITCH16
1300 @deffnx {} BFD_RELOC_SH_SWITCH32
1301 @deffnx {} BFD_RELOC_SH_USES
1302 @deffnx {} BFD_RELOC_SH_COUNT
1303 @deffnx {} BFD_RELOC_SH_ALIGN
1304 @deffnx {} BFD_RELOC_SH_CODE
1305 @deffnx {} BFD_RELOC_SH_DATA
1306 @deffnx {} BFD_RELOC_SH_LABEL
1307 @deffnx {} BFD_RELOC_SH_LOOP_START
1308 @deffnx {} BFD_RELOC_SH_LOOP_END
1309 @deffnx {} BFD_RELOC_SH_COPY
1310 @deffnx {} BFD_RELOC_SH_GLOB_DAT
1311 @deffnx {} BFD_RELOC_SH_JMP_SLOT
1312 @deffnx {} BFD_RELOC_SH_RELATIVE
1313 @deffnx {} BFD_RELOC_SH_GOTPC
1314 @deffnx {} BFD_RELOC_SH_GOT_LOW16
1315 @deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
1316 @deffnx {} BFD_RELOC_SH_GOT_MEDHI16
1317 @deffnx {} BFD_RELOC_SH_GOT_HI16
1318 @deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
1319 @deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
1320 @deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
1321 @deffnx {} BFD_RELOC_SH_GOTPLT_HI16
1322 @deffnx {} BFD_RELOC_SH_PLT_LOW16
1323 @deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
1324 @deffnx {} BFD_RELOC_SH_PLT_MEDHI16
1325 @deffnx {} BFD_RELOC_SH_PLT_HI16
1326 @deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
1327 @deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
1328 @deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1329 @deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1330 @deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1331 @deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1332 @deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1333 @deffnx {} BFD_RELOC_SH_GOTPC_HI16
1334 @deffnx {} BFD_RELOC_SH_COPY64
1335 @deffnx {} BFD_RELOC_SH_GLOB_DAT64
1336 @deffnx {} BFD_RELOC_SH_JMP_SLOT64
1337 @deffnx {} BFD_RELOC_SH_RELATIVE64
1338 @deffnx {} BFD_RELOC_SH_GOT10BY4
1339 @deffnx {} BFD_RELOC_SH_GOT10BY8
1340 @deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1341 @deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1342 @deffnx {} BFD_RELOC_SH_GOTPLT32
1343 @deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1344 @deffnx {} BFD_RELOC_SH_IMMU5
1345 @deffnx {} BFD_RELOC_SH_IMMS6
1346 @deffnx {} BFD_RELOC_SH_IMMS6BY32
1347 @deffnx {} BFD_RELOC_SH_IMMU6
1348 @deffnx {} BFD_RELOC_SH_IMMS10
1349 @deffnx {} BFD_RELOC_SH_IMMS10BY2
1350 @deffnx {} BFD_RELOC_SH_IMMS10BY4
1351 @deffnx {} BFD_RELOC_SH_IMMS10BY8
1352 @deffnx {} BFD_RELOC_SH_IMMS16
1353 @deffnx {} BFD_RELOC_SH_IMMU16
1354 @deffnx {} BFD_RELOC_SH_IMM_LOW16
1355 @deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1356 @deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1357 @deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1358 @deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1359 @deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1360 @deffnx {} BFD_RELOC_SH_IMM_HI16
1361 @deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1362 @deffnx {} BFD_RELOC_SH_PT_16
1363 @deffnx {} BFD_RELOC_SH_TLS_GD_32
1364 @deffnx {} BFD_RELOC_SH_TLS_LD_32
1365 @deffnx {} BFD_RELOC_SH_TLS_LDO_32
1366 @deffnx {} BFD_RELOC_SH_TLS_IE_32
1367 @deffnx {} BFD_RELOC_SH_TLS_LE_32
1368 @deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
1369 @deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
1370 @deffnx {} BFD_RELOC_SH_TLS_TPOFF32
1371 Renesas / SuperH SH relocs. Not all of these appear in object files.
1372 @end deffn
1373 @deffn {} BFD_RELOC_ARC_B22_PCREL
1374 ARC Cores relocs.
1375 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
1376 not stored in the instruction. The high 20 bits are installed in bits 26
1377 through 7 of the instruction.
1378 @end deffn
1379 @deffn {} BFD_RELOC_ARC_B26
1380 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
1381 stored in the instruction. The high 24 bits are installed in bits 23
1382 through 0.
1383 @end deffn
1384 @deffn {} BFD_RELOC_BFIN_16_IMM
1385 ADI Blackfin 16 bit immediate absolute reloc.
1386 @end deffn
1387 @deffn {} BFD_RELOC_BFIN_16_HIGH
1388 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
1389 @end deffn
1390 @deffn {} BFD_RELOC_BFIN_4_PCREL
1391 ADI Blackfin 'a' part of LSETUP.
1392 @end deffn
1393 @deffn {} BFD_RELOC_BFIN_5_PCREL
1394 ADI Blackfin.
1395 @end deffn
1396 @deffn {} BFD_RELOC_BFIN_16_LOW
1397 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
1398 @end deffn
1399 @deffn {} BFD_RELOC_BFIN_10_PCREL
1400 ADI Blackfin.
1401 @end deffn
1402 @deffn {} BFD_RELOC_BFIN_11_PCREL
1403 ADI Blackfin 'b' part of LSETUP.
1404 @end deffn
1405 @deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP
1406 ADI Blackfin.
1407 @end deffn
1408 @deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S
1409 ADI Blackfin Short jump, pcrel.
1410 @end deffn
1411 @deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X
1412 ADI Blackfin Call.x not implemented.
1413 @end deffn
1414 @deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L
1415 ADI Blackfin Long Jump pcrel.
1416 @end deffn
1417 @deffn {} BFD_RELOC_BFIN_GOT17M4
1418 @deffnx {} BFD_RELOC_BFIN_GOTHI
1419 @deffnx {} BFD_RELOC_BFIN_GOTLO
1420 @deffnx {} BFD_RELOC_BFIN_FUNCDESC
1421 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4
1422 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI
1423 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO
1424 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE
1425 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
1426 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
1427 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
1428 @deffnx {} BFD_RELOC_BFIN_GOTOFF17M4
1429 @deffnx {} BFD_RELOC_BFIN_GOTOFFHI
1430 @deffnx {} BFD_RELOC_BFIN_GOTOFFLO
1431 ADI Blackfin FD-PIC relocations.
1432 @end deffn
1433 @deffn {} BFD_RELOC_BFIN_GOT
1434 ADI Blackfin GOT relocation.
1435 @end deffn
1436 @deffn {} BFD_RELOC_BFIN_PLTPC
1437 ADI Blackfin PLTPC relocation.
1438 @end deffn
1439 @deffn {} BFD_ARELOC_BFIN_PUSH
1440 ADI Blackfin arithmetic relocation.
1441 @end deffn
1442 @deffn {} BFD_ARELOC_BFIN_CONST
1443 ADI Blackfin arithmetic relocation.
1444 @end deffn
1445 @deffn {} BFD_ARELOC_BFIN_ADD
1446 ADI Blackfin arithmetic relocation.
1447 @end deffn
1448 @deffn {} BFD_ARELOC_BFIN_SUB
1449 ADI Blackfin arithmetic relocation.
1450 @end deffn
1451 @deffn {} BFD_ARELOC_BFIN_MULT
1452 ADI Blackfin arithmetic relocation.
1453 @end deffn
1454 @deffn {} BFD_ARELOC_BFIN_DIV
1455 ADI Blackfin arithmetic relocation.
1456 @end deffn
1457 @deffn {} BFD_ARELOC_BFIN_MOD
1458 ADI Blackfin arithmetic relocation.
1459 @end deffn
1460 @deffn {} BFD_ARELOC_BFIN_LSHIFT
1461 ADI Blackfin arithmetic relocation.
1462 @end deffn
1463 @deffn {} BFD_ARELOC_BFIN_RSHIFT
1464 ADI Blackfin arithmetic relocation.
1465 @end deffn
1466 @deffn {} BFD_ARELOC_BFIN_AND
1467 ADI Blackfin arithmetic relocation.
1468 @end deffn
1469 @deffn {} BFD_ARELOC_BFIN_OR
1470 ADI Blackfin arithmetic relocation.
1471 @end deffn
1472 @deffn {} BFD_ARELOC_BFIN_XOR
1473 ADI Blackfin arithmetic relocation.
1474 @end deffn
1475 @deffn {} BFD_ARELOC_BFIN_LAND
1476 ADI Blackfin arithmetic relocation.
1477 @end deffn
1478 @deffn {} BFD_ARELOC_BFIN_LOR
1479 ADI Blackfin arithmetic relocation.
1480 @end deffn
1481 @deffn {} BFD_ARELOC_BFIN_LEN
1482 ADI Blackfin arithmetic relocation.
1483 @end deffn
1484 @deffn {} BFD_ARELOC_BFIN_NEG
1485 ADI Blackfin arithmetic relocation.
1486 @end deffn
1487 @deffn {} BFD_ARELOC_BFIN_COMP
1488 ADI Blackfin arithmetic relocation.
1489 @end deffn
1490 @deffn {} BFD_ARELOC_BFIN_PAGE
1491 ADI Blackfin arithmetic relocation.
1492 @end deffn
1493 @deffn {} BFD_ARELOC_BFIN_HWPAGE
1494 ADI Blackfin arithmetic relocation.
1495 @end deffn
1496 @deffn {} BFD_ARELOC_BFIN_ADDR
1497 ADI Blackfin arithmetic relocation.
1498 @end deffn
1499 @deffn {} BFD_RELOC_D10V_10_PCREL_R
1500 Mitsubishi D10V relocs.
1501 This is a 10-bit reloc with the right 2 bits
1502 assumed to be 0.
1503 @end deffn
1504 @deffn {} BFD_RELOC_D10V_10_PCREL_L
1505 Mitsubishi D10V relocs.
1506 This is a 10-bit reloc with the right 2 bits
1507 assumed to be 0. This is the same as the previous reloc
1508 except it is in the left container, i.e.,
1509 shifted left 15 bits.
1510 @end deffn
1511 @deffn {} BFD_RELOC_D10V_18
1512 This is an 18-bit reloc with the right 2 bits
1513 assumed to be 0.
1514 @end deffn
1515 @deffn {} BFD_RELOC_D10V_18_PCREL
1516 This is an 18-bit reloc with the right 2 bits
1517 assumed to be 0.
1518 @end deffn
1519 @deffn {} BFD_RELOC_D30V_6
1520 Mitsubishi D30V relocs.
1521 This is a 6-bit absolute reloc.
1522 @end deffn
1523 @deffn {} BFD_RELOC_D30V_9_PCREL
1524 This is a 6-bit pc-relative reloc with
1525 the right 3 bits assumed to be 0.
1526 @end deffn
1527 @deffn {} BFD_RELOC_D30V_9_PCREL_R
1528 This is a 6-bit pc-relative reloc with
1529 the right 3 bits assumed to be 0. Same
1530 as the previous reloc but on the right side
1531 of the container.
1532 @end deffn
1533 @deffn {} BFD_RELOC_D30V_15
1534 This is a 12-bit absolute reloc with the
1535 right 3 bitsassumed to be 0.
1536 @end deffn
1537 @deffn {} BFD_RELOC_D30V_15_PCREL
1538 This is a 12-bit pc-relative reloc with
1539 the right 3 bits assumed to be 0.
1540 @end deffn
1541 @deffn {} BFD_RELOC_D30V_15_PCREL_R
1542 This is a 12-bit pc-relative reloc with
1543 the right 3 bits assumed to be 0. Same
1544 as the previous reloc but on the right side
1545 of the container.
1546 @end deffn
1547 @deffn {} BFD_RELOC_D30V_21
1548 This is an 18-bit absolute reloc with
1549 the right 3 bits assumed to be 0.
1550 @end deffn
1551 @deffn {} BFD_RELOC_D30V_21_PCREL
1552 This is an 18-bit pc-relative reloc with
1553 the right 3 bits assumed to be 0.
1554 @end deffn
1555 @deffn {} BFD_RELOC_D30V_21_PCREL_R
1556 This is an 18-bit pc-relative reloc with
1557 the right 3 bits assumed to be 0. Same
1558 as the previous reloc but on the right side
1559 of the container.
1560 @end deffn
1561 @deffn {} BFD_RELOC_D30V_32
1562 This is a 32-bit absolute reloc.
1563 @end deffn
1564 @deffn {} BFD_RELOC_D30V_32_PCREL
1565 This is a 32-bit pc-relative reloc.
1566 @end deffn
1567 @deffn {} BFD_RELOC_DLX_HI16_S
1568 DLX relocs
1569 @end deffn
1570 @deffn {} BFD_RELOC_DLX_LO16
1571 DLX relocs
1572 @end deffn
1573 @deffn {} BFD_RELOC_DLX_JMP26
1574 DLX relocs
1575 @end deffn
1576 @deffn {} BFD_RELOC_M32C_HI8
1577 @deffnx {} BFD_RELOC_M32C_RL_JUMP
1578 @deffnx {} BFD_RELOC_M32C_RL_1ADDR
1579 @deffnx {} BFD_RELOC_M32C_RL_2ADDR
1580 Renesas M16C/M32C Relocations.
1581 @end deffn
1582 @deffn {} BFD_RELOC_M32R_24
1583 Renesas M32R (formerly Mitsubishi M32R) relocs.
1584 This is a 24 bit absolute address.
1585 @end deffn
1586 @deffn {} BFD_RELOC_M32R_10_PCREL
1587 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1588 @end deffn
1589 @deffn {} BFD_RELOC_M32R_18_PCREL
1590 This is an 18-bit reloc with the right 2 bits assumed to be 0.
1591 @end deffn
1592 @deffn {} BFD_RELOC_M32R_26_PCREL
1593 This is a 26-bit reloc with the right 2 bits assumed to be 0.
1594 @end deffn
1595 @deffn {} BFD_RELOC_M32R_HI16_ULO
1596 This is a 16-bit reloc containing the high 16 bits of an address
1597 used when the lower 16 bits are treated as unsigned.
1598 @end deffn
1599 @deffn {} BFD_RELOC_M32R_HI16_SLO
1600 This is a 16-bit reloc containing the high 16 bits of an address
1601 used when the lower 16 bits are treated as signed.
1602 @end deffn
1603 @deffn {} BFD_RELOC_M32R_LO16
1604 This is a 16-bit reloc containing the lower 16 bits of an address.
1605 @end deffn
1606 @deffn {} BFD_RELOC_M32R_SDA16
1607 This is a 16-bit reloc containing the small data area offset for use in
1608 add3, load, and store instructions.
1609 @end deffn
1610 @deffn {} BFD_RELOC_M32R_GOT24
1611 @deffnx {} BFD_RELOC_M32R_26_PLTREL
1612 @deffnx {} BFD_RELOC_M32R_COPY
1613 @deffnx {} BFD_RELOC_M32R_GLOB_DAT
1614 @deffnx {} BFD_RELOC_M32R_JMP_SLOT
1615 @deffnx {} BFD_RELOC_M32R_RELATIVE
1616 @deffnx {} BFD_RELOC_M32R_GOTOFF
1617 @deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
1618 @deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
1619 @deffnx {} BFD_RELOC_M32R_GOTOFF_LO
1620 @deffnx {} BFD_RELOC_M32R_GOTPC24
1621 @deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
1622 @deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
1623 @deffnx {} BFD_RELOC_M32R_GOT16_LO
1624 @deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
1625 @deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
1626 @deffnx {} BFD_RELOC_M32R_GOTPC_LO
1627 For PIC.
1628 @end deffn
1629 @deffn {} BFD_RELOC_V850_9_PCREL
1630 This is a 9-bit reloc
1631 @end deffn
1632 @deffn {} BFD_RELOC_V850_22_PCREL
1633 This is a 22-bit reloc
1634 @end deffn
1635 @deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1636 This is a 16 bit offset from the short data area pointer.
1637 @end deffn
1638 @deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1639 This is a 16 bit offset (of which only 15 bits are used) from the
1640 short data area pointer.
1641 @end deffn
1642 @deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1643 This is a 16 bit offset from the zero data area pointer.
1644 @end deffn
1645 @deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1646 This is a 16 bit offset (of which only 15 bits are used) from the
1647 zero data area pointer.
1648 @end deffn
1649 @deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1650 This is an 8 bit offset (of which only 6 bits are used) from the
1651 tiny data area pointer.
1652 @end deffn
1653 @deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1654 This is an 8bit offset (of which only 7 bits are used) from the tiny
1655 data area pointer.
1656 @end deffn
1657 @deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1658 This is a 7 bit offset from the tiny data area pointer.
1659 @end deffn
1660 @deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1661 This is a 16 bit offset from the tiny data area pointer.
1662 @end deffn
1663 @deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1664 This is a 5 bit offset (of which only 4 bits are used) from the tiny
1665 data area pointer.
1666 @end deffn
1667 @deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1668 This is a 4 bit offset from the tiny data area pointer.
1669 @end deffn
1670 @deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1671 This is a 16 bit offset from the short data area pointer, with the
1672 bits placed non-contiguously in the instruction.
1673 @end deffn
1674 @deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1675 This is a 16 bit offset from the zero data area pointer, with the
1676 bits placed non-contiguously in the instruction.
1677 @end deffn
1678 @deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1679 This is a 6 bit offset from the call table base pointer.
1680 @end deffn
1681 @deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1682 This is a 16 bit offset from the call table base pointer.
1683 @end deffn
1684 @deffn {} BFD_RELOC_V850_LONGCALL
1685 Used for relaxing indirect function calls.
1686 @end deffn
1687 @deffn {} BFD_RELOC_V850_LONGJUMP
1688 Used for relaxing indirect jumps.
1689 @end deffn
1690 @deffn {} BFD_RELOC_V850_ALIGN
1691 Used to maintain alignment whilst relaxing.
1692 @end deffn
1693 @deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET
1694 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
1695 instructions.
1696 @end deffn
1697 @deffn {} BFD_RELOC_MN10300_32_PCREL
1698 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1699 instruction.
1700 @end deffn
1701 @deffn {} BFD_RELOC_MN10300_16_PCREL
1702 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1703 instruction.
1704 @end deffn
1705 @deffn {} BFD_RELOC_TIC30_LDP
1706 This is a 8bit DP reloc for the tms320c30, where the most
1707 significant 8 bits of a 24 bit word are placed into the least
1708 significant 8 bits of the opcode.
1709 @end deffn
1710 @deffn {} BFD_RELOC_TIC54X_PARTLS7
1711 This is a 7bit reloc for the tms320c54x, where the least
1712 significant 7 bits of a 16 bit word are placed into the least
1713 significant 7 bits of the opcode.
1714 @end deffn
1715 @deffn {} BFD_RELOC_TIC54X_PARTMS9
1716 This is a 9bit DP reloc for the tms320c54x, where the most
1717 significant 9 bits of a 16 bit word are placed into the least
1718 significant 9 bits of the opcode.
1719 @end deffn
1720 @deffn {} BFD_RELOC_TIC54X_23
1721 This is an extended address 23-bit reloc for the tms320c54x.
1722 @end deffn
1723 @deffn {} BFD_RELOC_TIC54X_16_OF_23
1724 This is a 16-bit reloc for the tms320c54x, where the least
1725 significant 16 bits of a 23-bit extended address are placed into
1726 the opcode.
1727 @end deffn
1728 @deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1729 This is a reloc for the tms320c54x, where the most
1730 significant 7 bits of a 23-bit extended address are placed into
1731 the opcode.
1732 @end deffn
1733 @deffn {} BFD_RELOC_FR30_48
1734 This is a 48 bit reloc for the FR30 that stores 32 bits.
1735 @end deffn
1736 @deffn {} BFD_RELOC_FR30_20
1737 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1738 two sections.
1739 @end deffn
1740 @deffn {} BFD_RELOC_FR30_6_IN_4
1741 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1742 4 bits.
1743 @end deffn
1744 @deffn {} BFD_RELOC_FR30_8_IN_8
1745 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1746 into 8 bits.
1747 @end deffn
1748 @deffn {} BFD_RELOC_FR30_9_IN_8
1749 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1750 into 8 bits.
1751 @end deffn
1752 @deffn {} BFD_RELOC_FR30_10_IN_8
1753 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1754 into 8 bits.
1755 @end deffn
1756 @deffn {} BFD_RELOC_FR30_9_PCREL
1757 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1758 short offset into 8 bits.
1759 @end deffn
1760 @deffn {} BFD_RELOC_FR30_12_PCREL
1761 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1762 short offset into 11 bits.
1763 @end deffn
1764 @deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1765 @deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1766 @deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1767 @deffnx {} BFD_RELOC_MCORE_PCREL_32
1768 @deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1769 @deffnx {} BFD_RELOC_MCORE_RVA
1770 Motorola Mcore relocations.
1771 @end deffn
1772 @deffn {} BFD_RELOC_MEP_8
1773 @deffnx {} BFD_RELOC_MEP_16
1774 @deffnx {} BFD_RELOC_MEP_32
1775 @deffnx {} BFD_RELOC_MEP_PCREL8A2
1776 @deffnx {} BFD_RELOC_MEP_PCREL12A2
1777 @deffnx {} BFD_RELOC_MEP_PCREL17A2
1778 @deffnx {} BFD_RELOC_MEP_PCREL24A2
1779 @deffnx {} BFD_RELOC_MEP_PCABS24A2
1780 @deffnx {} BFD_RELOC_MEP_LOW16
1781 @deffnx {} BFD_RELOC_MEP_HI16U
1782 @deffnx {} BFD_RELOC_MEP_HI16S
1783 @deffnx {} BFD_RELOC_MEP_GPREL
1784 @deffnx {} BFD_RELOC_MEP_TPREL
1785 @deffnx {} BFD_RELOC_MEP_TPREL7
1786 @deffnx {} BFD_RELOC_MEP_TPREL7A2
1787 @deffnx {} BFD_RELOC_MEP_TPREL7A4
1788 @deffnx {} BFD_RELOC_MEP_UIMM24
1789 @deffnx {} BFD_RELOC_MEP_ADDR24A4
1790 @deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT
1791 @deffnx {} BFD_RELOC_MEP_GNU_VTENTRY
1792 Toshiba Media Processor Relocations.
1793 @end deffn
1794 @deffn {} BFD_RELOC_MMIX_GETA
1795 @deffnx {} BFD_RELOC_MMIX_GETA_1
1796 @deffnx {} BFD_RELOC_MMIX_GETA_2
1797 @deffnx {} BFD_RELOC_MMIX_GETA_3
1798 These are relocations for the GETA instruction.
1799 @end deffn
1800 @deffn {} BFD_RELOC_MMIX_CBRANCH
1801 @deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1802 @deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1803 @deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1804 @deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1805 These are relocations for a conditional branch instruction.
1806 @end deffn
1807 @deffn {} BFD_RELOC_MMIX_PUSHJ
1808 @deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1809 @deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1810 @deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1811 @deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
1812 These are relocations for the PUSHJ instruction.
1813 @end deffn
1814 @deffn {} BFD_RELOC_MMIX_JMP
1815 @deffnx {} BFD_RELOC_MMIX_JMP_1
1816 @deffnx {} BFD_RELOC_MMIX_JMP_2
1817 @deffnx {} BFD_RELOC_MMIX_JMP_3
1818 These are relocations for the JMP instruction.
1819 @end deffn
1820 @deffn {} BFD_RELOC_MMIX_ADDR19
1821 This is a relocation for a relative address as in a GETA instruction or
1822 a branch.
1823 @end deffn
1824 @deffn {} BFD_RELOC_MMIX_ADDR27
1825 This is a relocation for a relative address as in a JMP instruction.
1826 @end deffn
1827 @deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1828 This is a relocation for an instruction field that may be a general
1829 register or a value 0..255.
1830 @end deffn
1831 @deffn {} BFD_RELOC_MMIX_REG
1832 This is a relocation for an instruction field that may be a general
1833 register.
1834 @end deffn
1835 @deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1836 This is a relocation for two instruction fields holding a register and
1837 an offset, the equivalent of the relocation.
1838 @end deffn
1839 @deffn {} BFD_RELOC_MMIX_LOCAL
1840 This relocation is an assertion that the expression is not allocated as
1841 a global register. It does not modify contents.
1842 @end deffn
1843 @deffn {} BFD_RELOC_AVR_7_PCREL
1844 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1845 short offset into 7 bits.
1846 @end deffn
1847 @deffn {} BFD_RELOC_AVR_13_PCREL
1848 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1849 short offset into 12 bits.
1850 @end deffn
1851 @deffn {} BFD_RELOC_AVR_16_PM
1852 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1853 program memory address) into 16 bits.
1854 @end deffn
1855 @deffn {} BFD_RELOC_AVR_LO8_LDI
1856 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1857 data memory address) into 8 bit immediate value of LDI insn.
1858 @end deffn
1859 @deffn {} BFD_RELOC_AVR_HI8_LDI
1860 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1861 of data memory address) into 8 bit immediate value of LDI insn.
1862 @end deffn
1863 @deffn {} BFD_RELOC_AVR_HH8_LDI
1864 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1865 of program memory address) into 8 bit immediate value of LDI insn.
1866 @end deffn
1867 @deffn {} BFD_RELOC_AVR_MS8_LDI
1868 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1869 of 32 bit value) into 8 bit immediate value of LDI insn.
1870 @end deffn
1871 @deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1872 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1873 (usually data memory address) into 8 bit immediate value of SUBI insn.
1874 @end deffn
1875 @deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1876 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1877 (high 8 bit of data memory address) into 8 bit immediate value of
1878 SUBI insn.
1879 @end deffn
1880 @deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1881 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1882 (most high 8 bit of program memory address) into 8 bit immediate value
1883 of LDI or SUBI insn.
1884 @end deffn
1885 @deffn {} BFD_RELOC_AVR_MS8_LDI_NEG
1886 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
1887 of 32 bit value) into 8 bit immediate value of LDI insn.
1888 @end deffn
1889 @deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1890 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1891 command address) into 8 bit immediate value of LDI insn.
1892 @end deffn
1893 @deffn {} BFD_RELOC_AVR_LO8_LDI_GS
1894 This is a 16 bit reloc for the AVR that stores 8 bit value
1895 (command address) into 8 bit immediate value of LDI insn. If the address
1896 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1897 in the lower 128k.
1898 @end deffn
1899 @deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1900 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1901 of command address) into 8 bit immediate value of LDI insn.
1902 @end deffn
1903 @deffn {} BFD_RELOC_AVR_HI8_LDI_GS
1904 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1905 of command address) into 8 bit immediate value of LDI insn. If the address
1906 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1907 below 128k.
1908 @end deffn
1909 @deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1910 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1911 of command address) into 8 bit immediate value of LDI insn.
1912 @end deffn
1913 @deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1914 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1915 (usually command address) into 8 bit immediate value of SUBI insn.
1916 @end deffn
1917 @deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1918 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1919 (high 8 bit of 16 bit command address) into 8 bit immediate value
1920 of SUBI insn.
1921 @end deffn
1922 @deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1923 This is a 16 bit reloc for the AVR that stores negated 8 bit value
1924 (high 6 bit of 22 bit command address) into 8 bit immediate
1925 value of SUBI insn.
1926 @end deffn
1927 @deffn {} BFD_RELOC_AVR_CALL
1928 This is a 32 bit reloc for the AVR that stores 23 bit value
1929 into 22 bits.
1930 @end deffn
1931 @deffn {} BFD_RELOC_AVR_LDI
1932 This is a 16 bit reloc for the AVR that stores all needed bits
1933 for absolute addressing with ldi with overflow check to linktime
1934 @end deffn
1935 @deffn {} BFD_RELOC_AVR_6
1936 This is a 6 bit reloc for the AVR that stores offset for ldd/std
1937 instructions
1938 @end deffn
1939 @deffn {} BFD_RELOC_AVR_6_ADIW
1940 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
1941 instructions
1942 @end deffn
1943 @deffn {} BFD_RELOC_390_12
1944 Direct 12 bit.
1945 @end deffn
1946 @deffn {} BFD_RELOC_390_GOT12
1947 12 bit GOT offset.
1948 @end deffn
1949 @deffn {} BFD_RELOC_390_PLT32
1950 32 bit PC relative PLT address.
1951 @end deffn
1952 @deffn {} BFD_RELOC_390_COPY
1953 Copy symbol at runtime.
1954 @end deffn
1955 @deffn {} BFD_RELOC_390_GLOB_DAT
1956 Create GOT entry.
1957 @end deffn
1958 @deffn {} BFD_RELOC_390_JMP_SLOT
1959 Create PLT entry.
1960 @end deffn
1961 @deffn {} BFD_RELOC_390_RELATIVE
1962 Adjust by program base.
1963 @end deffn
1964 @deffn {} BFD_RELOC_390_GOTPC
1965 32 bit PC relative offset to GOT.
1966 @end deffn
1967 @deffn {} BFD_RELOC_390_GOT16
1968 16 bit GOT offset.
1969 @end deffn
1970 @deffn {} BFD_RELOC_390_PC16DBL
1971 PC relative 16 bit shifted by 1.
1972 @end deffn
1973 @deffn {} BFD_RELOC_390_PLT16DBL
1974 16 bit PC rel. PLT shifted by 1.
1975 @end deffn
1976 @deffn {} BFD_RELOC_390_PC32DBL
1977 PC relative 32 bit shifted by 1.
1978 @end deffn
1979 @deffn {} BFD_RELOC_390_PLT32DBL
1980 32 bit PC rel. PLT shifted by 1.
1981 @end deffn
1982 @deffn {} BFD_RELOC_390_GOTPCDBL
1983 32 bit PC rel. GOT shifted by 1.
1984 @end deffn
1985 @deffn {} BFD_RELOC_390_GOT64
1986 64 bit GOT offset.
1987 @end deffn
1988 @deffn {} BFD_RELOC_390_PLT64
1989 64 bit PC relative PLT address.
1990 @end deffn
1991 @deffn {} BFD_RELOC_390_GOTENT
1992 32 bit rel. offset to GOT entry.
1993 @end deffn
1994 @deffn {} BFD_RELOC_390_GOTOFF64
1995 64 bit offset to GOT.
1996 @end deffn
1997 @deffn {} BFD_RELOC_390_GOTPLT12
1998 12-bit offset to symbol-entry within GOT, with PLT handling.
1999 @end deffn
2000 @deffn {} BFD_RELOC_390_GOTPLT16
2001 16-bit offset to symbol-entry within GOT, with PLT handling.
2002 @end deffn
2003 @deffn {} BFD_RELOC_390_GOTPLT32
2004 32-bit offset to symbol-entry within GOT, with PLT handling.
2005 @end deffn
2006 @deffn {} BFD_RELOC_390_GOTPLT64
2007 64-bit offset to symbol-entry within GOT, with PLT handling.
2008 @end deffn
2009 @deffn {} BFD_RELOC_390_GOTPLTENT
2010 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
2011 @end deffn
2012 @deffn {} BFD_RELOC_390_PLTOFF16
2013 16-bit rel. offset from the GOT to a PLT entry.
2014 @end deffn
2015 @deffn {} BFD_RELOC_390_PLTOFF32
2016 32-bit rel. offset from the GOT to a PLT entry.
2017 @end deffn
2018 @deffn {} BFD_RELOC_390_PLTOFF64
2019 64-bit rel. offset from the GOT to a PLT entry.
2020 @end deffn
2021 @deffn {} BFD_RELOC_390_TLS_LOAD
2022 @deffnx {} BFD_RELOC_390_TLS_GDCALL
2023 @deffnx {} BFD_RELOC_390_TLS_LDCALL
2024 @deffnx {} BFD_RELOC_390_TLS_GD32
2025 @deffnx {} BFD_RELOC_390_TLS_GD64
2026 @deffnx {} BFD_RELOC_390_TLS_GOTIE12
2027 @deffnx {} BFD_RELOC_390_TLS_GOTIE32
2028 @deffnx {} BFD_RELOC_390_TLS_GOTIE64
2029 @deffnx {} BFD_RELOC_390_TLS_LDM32
2030 @deffnx {} BFD_RELOC_390_TLS_LDM64
2031 @deffnx {} BFD_RELOC_390_TLS_IE32
2032 @deffnx {} BFD_RELOC_390_TLS_IE64
2033 @deffnx {} BFD_RELOC_390_TLS_IEENT
2034 @deffnx {} BFD_RELOC_390_TLS_LE32
2035 @deffnx {} BFD_RELOC_390_TLS_LE64
2036 @deffnx {} BFD_RELOC_390_TLS_LDO32
2037 @deffnx {} BFD_RELOC_390_TLS_LDO64
2038 @deffnx {} BFD_RELOC_390_TLS_DTPMOD
2039 @deffnx {} BFD_RELOC_390_TLS_DTPOFF
2040 @deffnx {} BFD_RELOC_390_TLS_TPOFF
2041 s390 tls relocations.
2042 @end deffn
2043 @deffn {} BFD_RELOC_390_20
2044 @deffnx {} BFD_RELOC_390_GOT20
2045 @deffnx {} BFD_RELOC_390_GOTPLT20
2046 @deffnx {} BFD_RELOC_390_TLS_GOTIE20
2047 Long displacement extension.
2048 @end deffn
2049 @deffn {} BFD_RELOC_SCORE_DUMMY1
2050 Score relocations
2051 @end deffn
2052 @deffn {} BFD_RELOC_SCORE_GPREL15
2053 Low 16 bit for load/store
2054 @end deffn
2055 @deffn {} BFD_RELOC_SCORE_DUMMY2
2056 @deffnx {} BFD_RELOC_SCORE_JMP
2057 This is a 24-bit reloc with the right 1 bit assumed to be 0
2058 @end deffn
2059 @deffn {} BFD_RELOC_SCORE_BRANCH
2060 This is a 19-bit reloc with the right 1 bit assumed to be 0
2061 @end deffn
2062 @deffn {} BFD_RELOC_SCORE16_JMP
2063 This is a 11-bit reloc with the right 1 bit assumed to be 0
2064 @end deffn
2065 @deffn {} BFD_RELOC_SCORE16_BRANCH
2066 This is a 8-bit reloc with the right 1 bit assumed to be 0
2067 @end deffn
2068 @deffn {} BFD_RELOC_SCORE_GOT15
2069 @deffnx {} BFD_RELOC_SCORE_GOT_LO16
2070 @deffnx {} BFD_RELOC_SCORE_CALL15
2071 @deffnx {} BFD_RELOC_SCORE_DUMMY_HI16
2072 Undocumented Score relocs
2073 @end deffn
2074 @deffn {} BFD_RELOC_IP2K_FR9
2075 Scenix IP2K - 9-bit register number / data address
2076 @end deffn
2077 @deffn {} BFD_RELOC_IP2K_BANK
2078 Scenix IP2K - 4-bit register/data bank number
2079 @end deffn
2080 @deffn {} BFD_RELOC_IP2K_ADDR16CJP
2081 Scenix IP2K - low 13 bits of instruction word address
2082 @end deffn
2083 @deffn {} BFD_RELOC_IP2K_PAGE3
2084 Scenix IP2K - high 3 bits of instruction word address
2085 @end deffn
2086 @deffn {} BFD_RELOC_IP2K_LO8DATA
2087 @deffnx {} BFD_RELOC_IP2K_HI8DATA
2088 @deffnx {} BFD_RELOC_IP2K_EX8DATA
2089 Scenix IP2K - ext/low/high 8 bits of data address
2090 @end deffn
2091 @deffn {} BFD_RELOC_IP2K_LO8INSN
2092 @deffnx {} BFD_RELOC_IP2K_HI8INSN
2093 Scenix IP2K - low/high 8 bits of instruction word address
2094 @end deffn
2095 @deffn {} BFD_RELOC_IP2K_PC_SKIP
2096 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
2097 @end deffn
2098 @deffn {} BFD_RELOC_IP2K_TEXT
2099 Scenix IP2K - 16 bit word address in text section.
2100 @end deffn
2101 @deffn {} BFD_RELOC_IP2K_FR_OFFSET
2102 Scenix IP2K - 7-bit sp or dp offset
2103 @end deffn
2104 @deffn {} BFD_RELOC_VPE4KMATH_DATA
2105 @deffnx {} BFD_RELOC_VPE4KMATH_INSN
2106 Scenix VPE4K coprocessor - data/insn-space addressing
2107 @end deffn
2108 @deffn {} BFD_RELOC_VTABLE_INHERIT
2109 @deffnx {} BFD_RELOC_VTABLE_ENTRY
2110 These two relocations are used by the linker to determine which of
2111 the entries in a C++ virtual function table are actually used. When
2112 the --gc-sections option is given, the linker will zero out the entries
2113 that are not used, so that the code for those functions need not be
2114 included in the output.
2116 VTABLE_INHERIT is a zero-space relocation used to describe to the
2117 linker the inheritance tree of a C++ virtual function table. The
2118 relocation's symbol should be the parent class' vtable, and the
2119 relocation should be located at the child vtable.
2121 VTABLE_ENTRY is a zero-space relocation that describes the use of a
2122 virtual function table entry. The reloc's symbol should refer to the
2123 table of the class mentioned in the code. Off of that base, an offset
2124 describes the entry that is being used. For Rela hosts, this offset
2125 is stored in the reloc's addend. For Rel hosts, we are forced to put
2126 this offset in the reloc's section offset.
2127 @end deffn
2128 @deffn {} BFD_RELOC_IA64_IMM14
2129 @deffnx {} BFD_RELOC_IA64_IMM22
2130 @deffnx {} BFD_RELOC_IA64_IMM64
2131 @deffnx {} BFD_RELOC_IA64_DIR32MSB
2132 @deffnx {} BFD_RELOC_IA64_DIR32LSB
2133 @deffnx {} BFD_RELOC_IA64_DIR64MSB
2134 @deffnx {} BFD_RELOC_IA64_DIR64LSB
2135 @deffnx {} BFD_RELOC_IA64_GPREL22
2136 @deffnx {} BFD_RELOC_IA64_GPREL64I
2137 @deffnx {} BFD_RELOC_IA64_GPREL32MSB
2138 @deffnx {} BFD_RELOC_IA64_GPREL32LSB
2139 @deffnx {} BFD_RELOC_IA64_GPREL64MSB
2140 @deffnx {} BFD_RELOC_IA64_GPREL64LSB
2141 @deffnx {} BFD_RELOC_IA64_LTOFF22
2142 @deffnx {} BFD_RELOC_IA64_LTOFF64I
2143 @deffnx {} BFD_RELOC_IA64_PLTOFF22
2144 @deffnx {} BFD_RELOC_IA64_PLTOFF64I
2145 @deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
2146 @deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
2147 @deffnx {} BFD_RELOC_IA64_FPTR64I
2148 @deffnx {} BFD_RELOC_IA64_FPTR32MSB
2149 @deffnx {} BFD_RELOC_IA64_FPTR32LSB
2150 @deffnx {} BFD_RELOC_IA64_FPTR64MSB
2151 @deffnx {} BFD_RELOC_IA64_FPTR64LSB
2152 @deffnx {} BFD_RELOC_IA64_PCREL21B
2153 @deffnx {} BFD_RELOC_IA64_PCREL21BI
2154 @deffnx {} BFD_RELOC_IA64_PCREL21M
2155 @deffnx {} BFD_RELOC_IA64_PCREL21F
2156 @deffnx {} BFD_RELOC_IA64_PCREL22
2157 @deffnx {} BFD_RELOC_IA64_PCREL60B
2158 @deffnx {} BFD_RELOC_IA64_PCREL64I
2159 @deffnx {} BFD_RELOC_IA64_PCREL32MSB
2160 @deffnx {} BFD_RELOC_IA64_PCREL32LSB
2161 @deffnx {} BFD_RELOC_IA64_PCREL64MSB
2162 @deffnx {} BFD_RELOC_IA64_PCREL64LSB
2163 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
2164 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
2165 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
2166 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
2167 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
2168 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
2169 @deffnx {} BFD_RELOC_IA64_SEGREL32MSB
2170 @deffnx {} BFD_RELOC_IA64_SEGREL32LSB
2171 @deffnx {} BFD_RELOC_IA64_SEGREL64MSB
2172 @deffnx {} BFD_RELOC_IA64_SEGREL64LSB
2173 @deffnx {} BFD_RELOC_IA64_SECREL32MSB
2174 @deffnx {} BFD_RELOC_IA64_SECREL32LSB
2175 @deffnx {} BFD_RELOC_IA64_SECREL64MSB
2176 @deffnx {} BFD_RELOC_IA64_SECREL64LSB
2177 @deffnx {} BFD_RELOC_IA64_REL32MSB
2178 @deffnx {} BFD_RELOC_IA64_REL32LSB
2179 @deffnx {} BFD_RELOC_IA64_REL64MSB
2180 @deffnx {} BFD_RELOC_IA64_REL64LSB
2181 @deffnx {} BFD_RELOC_IA64_LTV32MSB
2182 @deffnx {} BFD_RELOC_IA64_LTV32LSB
2183 @deffnx {} BFD_RELOC_IA64_LTV64MSB
2184 @deffnx {} BFD_RELOC_IA64_LTV64LSB
2185 @deffnx {} BFD_RELOC_IA64_IPLTMSB
2186 @deffnx {} BFD_RELOC_IA64_IPLTLSB
2187 @deffnx {} BFD_RELOC_IA64_COPY
2188 @deffnx {} BFD_RELOC_IA64_LTOFF22X
2189 @deffnx {} BFD_RELOC_IA64_LDXMOV
2190 @deffnx {} BFD_RELOC_IA64_TPREL14
2191 @deffnx {} BFD_RELOC_IA64_TPREL22
2192 @deffnx {} BFD_RELOC_IA64_TPREL64I
2193 @deffnx {} BFD_RELOC_IA64_TPREL64MSB
2194 @deffnx {} BFD_RELOC_IA64_TPREL64LSB
2195 @deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
2196 @deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
2197 @deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
2198 @deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
2199 @deffnx {} BFD_RELOC_IA64_DTPREL14
2200 @deffnx {} BFD_RELOC_IA64_DTPREL22
2201 @deffnx {} BFD_RELOC_IA64_DTPREL64I
2202 @deffnx {} BFD_RELOC_IA64_DTPREL32MSB
2203 @deffnx {} BFD_RELOC_IA64_DTPREL32LSB
2204 @deffnx {} BFD_RELOC_IA64_DTPREL64MSB
2205 @deffnx {} BFD_RELOC_IA64_DTPREL64LSB
2206 @deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
2207 Intel IA64 Relocations.
2208 @end deffn
2209 @deffn {} BFD_RELOC_M68HC11_HI8
2210 Motorola 68HC11 reloc.
2211 This is the 8 bit high part of an absolute address.
2212 @end deffn
2213 @deffn {} BFD_RELOC_M68HC11_LO8
2214 Motorola 68HC11 reloc.
2215 This is the 8 bit low part of an absolute address.
2216 @end deffn
2217 @deffn {} BFD_RELOC_M68HC11_3B
2218 Motorola 68HC11 reloc.
2219 This is the 3 bit of a value.
2220 @end deffn
2221 @deffn {} BFD_RELOC_M68HC11_RL_JUMP
2222 Motorola 68HC11 reloc.
2223 This reloc marks the beginning of a jump/call instruction.
2224 It is used for linker relaxation to correctly identify beginning
2225 of instruction and change some branches to use PC-relative
2226 addressing mode.
2227 @end deffn
2228 @deffn {} BFD_RELOC_M68HC11_RL_GROUP
2229 Motorola 68HC11 reloc.
2230 This reloc marks a group of several instructions that gcc generates
2231 and for which the linker relaxation pass can modify and/or remove
2232 some of them.
2233 @end deffn
2234 @deffn {} BFD_RELOC_M68HC11_LO16
2235 Motorola 68HC11 reloc.
2236 This is the 16-bit lower part of an address. It is used for 'call'
2237 instruction to specify the symbol address without any special
2238 transformation (due to memory bank window).
2239 @end deffn
2240 @deffn {} BFD_RELOC_M68HC11_PAGE
2241 Motorola 68HC11 reloc.
2242 This is a 8-bit reloc that specifies the page number of an address.
2243 It is used by 'call' instruction to specify the page number of
2244 the symbol.
2245 @end deffn
2246 @deffn {} BFD_RELOC_M68HC11_24
2247 Motorola 68HC11 reloc.
2248 This is a 24-bit reloc that represents the address with a 16-bit
2249 value and a 8-bit page number. The symbol address is transformed
2250 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
2251 @end deffn
2252 @deffn {} BFD_RELOC_M68HC12_5B
2253 Motorola 68HC12 reloc.
2254 This is the 5 bits of a value.
2255 @end deffn
2256 @deffn {} BFD_RELOC_16C_NUM08
2257 @deffnx {} BFD_RELOC_16C_NUM08_C
2258 @deffnx {} BFD_RELOC_16C_NUM16
2259 @deffnx {} BFD_RELOC_16C_NUM16_C
2260 @deffnx {} BFD_RELOC_16C_NUM32
2261 @deffnx {} BFD_RELOC_16C_NUM32_C
2262 @deffnx {} BFD_RELOC_16C_DISP04
2263 @deffnx {} BFD_RELOC_16C_DISP04_C
2264 @deffnx {} BFD_RELOC_16C_DISP08
2265 @deffnx {} BFD_RELOC_16C_DISP08_C
2266 @deffnx {} BFD_RELOC_16C_DISP16
2267 @deffnx {} BFD_RELOC_16C_DISP16_C
2268 @deffnx {} BFD_RELOC_16C_DISP24
2269 @deffnx {} BFD_RELOC_16C_DISP24_C
2270 @deffnx {} BFD_RELOC_16C_DISP24a
2271 @deffnx {} BFD_RELOC_16C_DISP24a_C
2272 @deffnx {} BFD_RELOC_16C_REG04
2273 @deffnx {} BFD_RELOC_16C_REG04_C
2274 @deffnx {} BFD_RELOC_16C_REG04a
2275 @deffnx {} BFD_RELOC_16C_REG04a_C
2276 @deffnx {} BFD_RELOC_16C_REG14
2277 @deffnx {} BFD_RELOC_16C_REG14_C
2278 @deffnx {} BFD_RELOC_16C_REG16
2279 @deffnx {} BFD_RELOC_16C_REG16_C
2280 @deffnx {} BFD_RELOC_16C_REG20
2281 @deffnx {} BFD_RELOC_16C_REG20_C
2282 @deffnx {} BFD_RELOC_16C_ABS20
2283 @deffnx {} BFD_RELOC_16C_ABS20_C
2284 @deffnx {} BFD_RELOC_16C_ABS24
2285 @deffnx {} BFD_RELOC_16C_ABS24_C
2286 @deffnx {} BFD_RELOC_16C_IMM04
2287 @deffnx {} BFD_RELOC_16C_IMM04_C
2288 @deffnx {} BFD_RELOC_16C_IMM16
2289 @deffnx {} BFD_RELOC_16C_IMM16_C
2290 @deffnx {} BFD_RELOC_16C_IMM20
2291 @deffnx {} BFD_RELOC_16C_IMM20_C
2292 @deffnx {} BFD_RELOC_16C_IMM24
2293 @deffnx {} BFD_RELOC_16C_IMM24_C
2294 @deffnx {} BFD_RELOC_16C_IMM32
2295 @deffnx {} BFD_RELOC_16C_IMM32_C
2296 NS CR16C Relocations.
2297 @end deffn
2298 @deffn {} BFD_RELOC_CR16_NUM8
2299 @deffnx {} BFD_RELOC_CR16_NUM16
2300 @deffnx {} BFD_RELOC_CR16_NUM32
2301 @deffnx {} BFD_RELOC_CR16_NUM32a
2302 @deffnx {} BFD_RELOC_CR16_REGREL0
2303 @deffnx {} BFD_RELOC_CR16_REGREL4
2304 @deffnx {} BFD_RELOC_CR16_REGREL4a
2305 @deffnx {} BFD_RELOC_CR16_REGREL14
2306 @deffnx {} BFD_RELOC_CR16_REGREL14a
2307 @deffnx {} BFD_RELOC_CR16_REGREL16
2308 @deffnx {} BFD_RELOC_CR16_REGREL20
2309 @deffnx {} BFD_RELOC_CR16_REGREL20a
2310 @deffnx {} BFD_RELOC_CR16_ABS20
2311 @deffnx {} BFD_RELOC_CR16_ABS24
2312 @deffnx {} BFD_RELOC_CR16_IMM4
2313 @deffnx {} BFD_RELOC_CR16_IMM8
2314 @deffnx {} BFD_RELOC_CR16_IMM16
2315 @deffnx {} BFD_RELOC_CR16_IMM20
2316 @deffnx {} BFD_RELOC_CR16_IMM24
2317 @deffnx {} BFD_RELOC_CR16_IMM32
2318 @deffnx {} BFD_RELOC_CR16_IMM32a
2319 @deffnx {} BFD_RELOC_CR16_DISP4
2320 @deffnx {} BFD_RELOC_CR16_DISP8
2321 @deffnx {} BFD_RELOC_CR16_DISP16
2322 @deffnx {} BFD_RELOC_CR16_DISP20
2323 @deffnx {} BFD_RELOC_CR16_DISP24
2324 @deffnx {} BFD_RELOC_CR16_DISP24a
2325 @deffnx {} BFD_RELOC_CR16_SWITCH8
2326 @deffnx {} BFD_RELOC_CR16_SWITCH16
2327 @deffnx {} BFD_RELOC_CR16_SWITCH32
2328 NS CR16 Relocations.
2329 @end deffn
2330 @deffn {} BFD_RELOC_CRX_REL4
2331 @deffnx {} BFD_RELOC_CRX_REL8
2332 @deffnx {} BFD_RELOC_CRX_REL8_CMP
2333 @deffnx {} BFD_RELOC_CRX_REL16
2334 @deffnx {} BFD_RELOC_CRX_REL24
2335 @deffnx {} BFD_RELOC_CRX_REL32
2336 @deffnx {} BFD_RELOC_CRX_REGREL12
2337 @deffnx {} BFD_RELOC_CRX_REGREL22
2338 @deffnx {} BFD_RELOC_CRX_REGREL28
2339 @deffnx {} BFD_RELOC_CRX_REGREL32
2340 @deffnx {} BFD_RELOC_CRX_ABS16
2341 @deffnx {} BFD_RELOC_CRX_ABS32
2342 @deffnx {} BFD_RELOC_CRX_NUM8
2343 @deffnx {} BFD_RELOC_CRX_NUM16
2344 @deffnx {} BFD_RELOC_CRX_NUM32
2345 @deffnx {} BFD_RELOC_CRX_IMM16
2346 @deffnx {} BFD_RELOC_CRX_IMM32
2347 @deffnx {} BFD_RELOC_CRX_SWITCH8
2348 @deffnx {} BFD_RELOC_CRX_SWITCH16
2349 @deffnx {} BFD_RELOC_CRX_SWITCH32
2350 NS CRX Relocations.
2351 @end deffn
2352 @deffn {} BFD_RELOC_CRIS_BDISP8
2353 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
2354 @deffnx {} BFD_RELOC_CRIS_SIGNED_6
2355 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
2356 @deffnx {} BFD_RELOC_CRIS_SIGNED_8
2357 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_8
2358 @deffnx {} BFD_RELOC_CRIS_SIGNED_16
2359 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_16
2360 @deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET
2361 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
2362 These relocs are only used within the CRIS assembler. They are not
2363 (at present) written to any object files.
2364 @end deffn
2365 @deffn {} BFD_RELOC_CRIS_COPY
2366 @deffnx {} BFD_RELOC_CRIS_GLOB_DAT
2367 @deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
2368 @deffnx {} BFD_RELOC_CRIS_RELATIVE
2369 Relocs used in ELF shared libraries for CRIS.
2370 @end deffn
2371 @deffn {} BFD_RELOC_CRIS_32_GOT
2372 32-bit offset to symbol-entry within GOT.
2373 @end deffn
2374 @deffn {} BFD_RELOC_CRIS_16_GOT
2375 16-bit offset to symbol-entry within GOT.
2376 @end deffn
2377 @deffn {} BFD_RELOC_CRIS_32_GOTPLT
2378 32-bit offset to symbol-entry within GOT, with PLT handling.
2379 @end deffn
2380 @deffn {} BFD_RELOC_CRIS_16_GOTPLT
2381 16-bit offset to symbol-entry within GOT, with PLT handling.
2382 @end deffn
2383 @deffn {} BFD_RELOC_CRIS_32_GOTREL
2384 32-bit offset to symbol, relative to GOT.
2385 @end deffn
2386 @deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
2387 32-bit offset to symbol with PLT entry, relative to GOT.
2388 @end deffn
2389 @deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
2390 32-bit offset to symbol with PLT entry, relative to this relocation.
2391 @end deffn
2392 @deffn {} BFD_RELOC_860_COPY
2393 @deffnx {} BFD_RELOC_860_GLOB_DAT
2394 @deffnx {} BFD_RELOC_860_JUMP_SLOT
2395 @deffnx {} BFD_RELOC_860_RELATIVE
2396 @deffnx {} BFD_RELOC_860_PC26
2397 @deffnx {} BFD_RELOC_860_PLT26
2398 @deffnx {} BFD_RELOC_860_PC16
2399 @deffnx {} BFD_RELOC_860_LOW0
2400 @deffnx {} BFD_RELOC_860_SPLIT0
2401 @deffnx {} BFD_RELOC_860_LOW1
2402 @deffnx {} BFD_RELOC_860_SPLIT1
2403 @deffnx {} BFD_RELOC_860_LOW2
2404 @deffnx {} BFD_RELOC_860_SPLIT2
2405 @deffnx {} BFD_RELOC_860_LOW3
2406 @deffnx {} BFD_RELOC_860_LOGOT0
2407 @deffnx {} BFD_RELOC_860_SPGOT0
2408 @deffnx {} BFD_RELOC_860_LOGOT1
2409 @deffnx {} BFD_RELOC_860_SPGOT1
2410 @deffnx {} BFD_RELOC_860_LOGOTOFF0
2411 @deffnx {} BFD_RELOC_860_SPGOTOFF0
2412 @deffnx {} BFD_RELOC_860_LOGOTOFF1
2413 @deffnx {} BFD_RELOC_860_SPGOTOFF1
2414 @deffnx {} BFD_RELOC_860_LOGOTOFF2
2415 @deffnx {} BFD_RELOC_860_LOGOTOFF3
2416 @deffnx {} BFD_RELOC_860_LOPC
2417 @deffnx {} BFD_RELOC_860_HIGHADJ
2418 @deffnx {} BFD_RELOC_860_HAGOT
2419 @deffnx {} BFD_RELOC_860_HAGOTOFF
2420 @deffnx {} BFD_RELOC_860_HAPC
2421 @deffnx {} BFD_RELOC_860_HIGH
2422 @deffnx {} BFD_RELOC_860_HIGOT
2423 @deffnx {} BFD_RELOC_860_HIGOTOFF
2424 Intel i860 Relocations.
2425 @end deffn
2426 @deffn {} BFD_RELOC_OPENRISC_ABS_26
2427 @deffnx {} BFD_RELOC_OPENRISC_REL_26
2428 OpenRISC Relocations.
2429 @end deffn
2430 @deffn {} BFD_RELOC_H8_DIR16A8
2431 @deffnx {} BFD_RELOC_H8_DIR16R8
2432 @deffnx {} BFD_RELOC_H8_DIR24A8
2433 @deffnx {} BFD_RELOC_H8_DIR24R8
2434 @deffnx {} BFD_RELOC_H8_DIR32A16
2435 H8 elf Relocations.
2436 @end deffn
2437 @deffn {} BFD_RELOC_XSTORMY16_REL_12
2438 @deffnx {} BFD_RELOC_XSTORMY16_12
2439 @deffnx {} BFD_RELOC_XSTORMY16_24
2440 @deffnx {} BFD_RELOC_XSTORMY16_FPTR16
2441 Sony Xstormy16 Relocations.
2442 @end deffn
2443 @deffn {} BFD_RELOC_RELC
2444 Self-describing complex relocations.
2445 @end deffn
2446 @deffn {} BFD_RELOC_XC16X_PAG
2447 @deffnx {} BFD_RELOC_XC16X_POF
2448 @deffnx {} BFD_RELOC_XC16X_SEG
2449 @deffnx {} BFD_RELOC_XC16X_SOF
2450 Infineon Relocations.
2451 @end deffn
2452 @deffn {} BFD_RELOC_VAX_GLOB_DAT
2453 @deffnx {} BFD_RELOC_VAX_JMP_SLOT
2454 @deffnx {} BFD_RELOC_VAX_RELATIVE
2455 Relocations used by VAX ELF.
2456 @end deffn
2457 @deffn {} BFD_RELOC_MT_PC16
2458 Morpho MT - 16 bit immediate relocation.
2459 @end deffn
2460 @deffn {} BFD_RELOC_MT_HI16
2461 Morpho MT - Hi 16 bits of an address.
2462 @end deffn
2463 @deffn {} BFD_RELOC_MT_LO16
2464 Morpho MT - Low 16 bits of an address.
2465 @end deffn
2466 @deffn {} BFD_RELOC_MT_GNU_VTINHERIT
2467 Morpho MT - Used to tell the linker which vtable entries are used.
2468 @end deffn
2469 @deffn {} BFD_RELOC_MT_GNU_VTENTRY
2470 Morpho MT - Used to tell the linker which vtable entries are used.
2471 @end deffn
2472 @deffn {} BFD_RELOC_MT_PCINSN8
2473 Morpho MT - 8 bit immediate relocation.
2474 @end deffn
2475 @deffn {} BFD_RELOC_MSP430_10_PCREL
2476 @deffnx {} BFD_RELOC_MSP430_16_PCREL
2477 @deffnx {} BFD_RELOC_MSP430_16
2478 @deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
2479 @deffnx {} BFD_RELOC_MSP430_16_BYTE
2480 @deffnx {} BFD_RELOC_MSP430_2X_PCREL
2481 @deffnx {} BFD_RELOC_MSP430_RL_PCREL
2482 msp430 specific relocation codes
2483 @end deffn
2484 @deffn {} BFD_RELOC_IQ2000_OFFSET_16
2485 @deffnx {} BFD_RELOC_IQ2000_OFFSET_21
2486 @deffnx {} BFD_RELOC_IQ2000_UHI16
2487 IQ2000 Relocations.
2488 @end deffn
2489 @deffn {} BFD_RELOC_XTENSA_RTLD
2490 Special Xtensa relocation used only by PLT entries in ELF shared
2491 objects to indicate that the runtime linker should set the value
2492 to one of its own internal functions or data structures.
2493 @end deffn
2494 @deffn {} BFD_RELOC_XTENSA_GLOB_DAT
2495 @deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
2496 @deffnx {} BFD_RELOC_XTENSA_RELATIVE
2497 Xtensa relocations for ELF shared objects.
2498 @end deffn
2499 @deffn {} BFD_RELOC_XTENSA_PLT
2500 Xtensa relocation used in ELF object files for symbols that may require
2501 PLT entries. Otherwise, this is just a generic 32-bit relocation.
2502 @end deffn
2503 @deffn {} BFD_RELOC_XTENSA_DIFF8
2504 @deffnx {} BFD_RELOC_XTENSA_DIFF16
2505 @deffnx {} BFD_RELOC_XTENSA_DIFF32
2506 Xtensa relocations to mark the difference of two local symbols.
2507 These are only needed to support linker relaxation and can be ignored
2508 when not relaxing. The field is set to the value of the difference
2509 assuming no relaxation. The relocation encodes the position of the
2510 first symbol so the linker can determine whether to adjust the field
2511 value.
2512 @end deffn
2513 @deffn {} BFD_RELOC_XTENSA_SLOT0_OP
2514 @deffnx {} BFD_RELOC_XTENSA_SLOT1_OP
2515 @deffnx {} BFD_RELOC_XTENSA_SLOT2_OP
2516 @deffnx {} BFD_RELOC_XTENSA_SLOT3_OP
2517 @deffnx {} BFD_RELOC_XTENSA_SLOT4_OP
2518 @deffnx {} BFD_RELOC_XTENSA_SLOT5_OP
2519 @deffnx {} BFD_RELOC_XTENSA_SLOT6_OP
2520 @deffnx {} BFD_RELOC_XTENSA_SLOT7_OP
2521 @deffnx {} BFD_RELOC_XTENSA_SLOT8_OP
2522 @deffnx {} BFD_RELOC_XTENSA_SLOT9_OP
2523 @deffnx {} BFD_RELOC_XTENSA_SLOT10_OP
2524 @deffnx {} BFD_RELOC_XTENSA_SLOT11_OP
2525 @deffnx {} BFD_RELOC_XTENSA_SLOT12_OP
2526 @deffnx {} BFD_RELOC_XTENSA_SLOT13_OP
2527 @deffnx {} BFD_RELOC_XTENSA_SLOT14_OP
2528 Generic Xtensa relocations for instruction operands. Only the slot
2529 number is encoded in the relocation. The relocation applies to the
2530 last PC-relative immediate operand, or if there are no PC-relative
2531 immediates, to the last immediate operand.
2532 @end deffn
2533 @deffn {} BFD_RELOC_XTENSA_SLOT0_ALT
2534 @deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT
2535 @deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT
2536 @deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT
2537 @deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT
2538 @deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT
2539 @deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT
2540 @deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT
2541 @deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT
2542 @deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT
2543 @deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT
2544 @deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT
2545 @deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT
2546 @deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT
2547 @deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT
2548 Alternate Xtensa relocations. Only the slot is encoded in the
2549 relocation. The meaning of these relocations is opcode-specific.
2550 @end deffn
2551 @deffn {} BFD_RELOC_XTENSA_OP0
2552 @deffnx {} BFD_RELOC_XTENSA_OP1
2553 @deffnx {} BFD_RELOC_XTENSA_OP2
2554 Xtensa relocations for backward compatibility. These have all been
2555 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
2556 @end deffn
2557 @deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
2558 Xtensa relocation to mark that the assembler expanded the
2559 instructions from an original target. The expansion size is
2560 encoded in the reloc size.
2561 @end deffn
2562 @deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
2563 Xtensa relocation to mark that the linker should simplify
2564 assembler-expanded instructions. This is commonly used
2565 internally by the linker after analysis of a
2566 BFD_RELOC_XTENSA_ASM_EXPAND.
2567 @end deffn
2568 @deffn {} BFD_RELOC_XTENSA_TLSDESC_FN
2569 @deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG
2570 @deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF
2571 @deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF
2572 @deffnx {} BFD_RELOC_XTENSA_TLS_FUNC
2573 @deffnx {} BFD_RELOC_XTENSA_TLS_ARG
2574 @deffnx {} BFD_RELOC_XTENSA_TLS_CALL
2575 Xtensa TLS relocations.
2576 @end deffn
2577 @deffn {} BFD_RELOC_Z80_DISP8
2578 8 bit signed offset in (ix+d) or (iy+d).
2579 @end deffn
2580 @deffn {} BFD_RELOC_Z8K_DISP7
2581 DJNZ offset.
2582 @end deffn
2583 @deffn {} BFD_RELOC_Z8K_CALLR
2584 CALR offset.
2585 @end deffn
2586 @deffn {} BFD_RELOC_Z8K_IMM4L
2587 4 bit value.
2588 @end deffn
2590 @example
2592 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
2593 @end example
2594 @findex bfd_reloc_type_lookup
2595 @subsubsection @code{bfd_reloc_type_lookup}
2596 @strong{Synopsis}
2597 @example
2598 reloc_howto_type *bfd_reloc_type_lookup
2599 (bfd *abfd, bfd_reloc_code_real_type code);
2600 reloc_howto_type *bfd_reloc_name_lookup
2601 (bfd *abfd, const char *reloc_name);
2602 @end example
2603 @strong{Description}@*
2604 Return a pointer to a howto structure which, when
2605 invoked, will perform the relocation @var{code} on data from the
2606 architecture noted.
2608 @findex bfd_default_reloc_type_lookup
2609 @subsubsection @code{bfd_default_reloc_type_lookup}
2610 @strong{Synopsis}
2611 @example
2612 reloc_howto_type *bfd_default_reloc_type_lookup
2613 (bfd *abfd, bfd_reloc_code_real_type code);
2614 @end example
2615 @strong{Description}@*
2616 Provides a default relocation lookup routine for any architecture.
2618 @findex bfd_get_reloc_code_name
2619 @subsubsection @code{bfd_get_reloc_code_name}
2620 @strong{Synopsis}
2621 @example
2622 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
2623 @end example
2624 @strong{Description}@*
2625 Provides a printable name for the supplied relocation code.
2626 Useful mainly for printing error messages.
2628 @findex bfd_generic_relax_section
2629 @subsubsection @code{bfd_generic_relax_section}
2630 @strong{Synopsis}
2631 @example
2632 bfd_boolean bfd_generic_relax_section
2633 (bfd *abfd,
2634 asection *section,
2635 struct bfd_link_info *,
2636 bfd_boolean *);
2637 @end example
2638 @strong{Description}@*
2639 Provides default handling for relaxing for back ends which
2640 don't do relaxing.
2642 @findex bfd_generic_gc_sections
2643 @subsubsection @code{bfd_generic_gc_sections}
2644 @strong{Synopsis}
2645 @example
2646 bfd_boolean bfd_generic_gc_sections
2647 (bfd *, struct bfd_link_info *);
2648 @end example
2649 @strong{Description}@*
2650 Provides default handling for relaxing for back ends which
2651 don't do section gc -- i.e., does nothing.
2653 @findex bfd_generic_merge_sections
2654 @subsubsection @code{bfd_generic_merge_sections}
2655 @strong{Synopsis}
2656 @example
2657 bfd_boolean bfd_generic_merge_sections
2658 (bfd *, struct bfd_link_info *);
2659 @end example
2660 @strong{Description}@*
2661 Provides default handling for SEC_MERGE section merging for back ends
2662 which don't have SEC_MERGE support -- i.e., does nothing.
2664 @findex bfd_generic_get_relocated_section_contents
2665 @subsubsection @code{bfd_generic_get_relocated_section_contents}
2666 @strong{Synopsis}
2667 @example
2668 bfd_byte *bfd_generic_get_relocated_section_contents
2669 (bfd *abfd,
2670 struct bfd_link_info *link_info,
2671 struct bfd_link_order *link_order,
2672 bfd_byte *data,
2673 bfd_boolean relocatable,
2674 asymbol **symbols);
2675 @end example
2676 @strong{Description}@*
2677 Provides default handling of relocation effort for back ends
2678 which can't be bothered to do it efficiently.