gnu/dist/gcc4/gcc/testsuite/gcc.dg/i386-cpuid.h

   1 /* Helper file for i386 platform.  Runtime check for MMX/SSE/SSE2 support.
   2    Used by 20020523-2.c and i386-sse-6.c, and possibly others.  */
   3 /* Plagarized from 20020523-2.c.  */
   4
   5 #define bit_CMOV (1 << 15)
   6 #define bit_MMX (1 << 23)
   7 #define bit_SSE (1 << 25)
   8 #define bit_SSE2 (1 << 26)
   9
  10 #ifndef NOINLINE
  11 #define NOINLINE __attribute__ ((noinline))
  12 #endif
  13
  14 unsigned int i386_cpuid (void) NOINLINE;
  15
  16 unsigned int NOINLINE
  17 i386_cpuid (void)
  18 {
  19   int fl1, fl2;
  20
  21 #ifndef __x86_64__
  22   /* See if we can use cpuid.  On AMD64 we always can.  */
  23   __asm__ ("pushfl; pushfl; popl %0; movl %0,%1; xorl %2,%0;"
  24            "pushl %0; popfl; pushfl; popl %0; popfl"
  25            : "=&r" (fl1), "=&r" (fl2)
  26            : "i" (0x00200000));
  27   if (((fl1 ^ fl2) & 0x00200000) == 0)
  28     return (0);
  29 #endif
  30
  31   /* Host supports cpuid.  See if cpuid gives capabilities, try
  32      CPUID(0).  Preserve %ebx and %ecx; cpuid insn clobbers these, we
  33      don't need their CPUID values here, and %ebx may be the PIC
  34      register.  */
  35 #ifdef __x86_64__
  36   __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx"
  37            : "=a" (fl1) : "0" (0) : "rdx", "cc");
  38 #else
  39   __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
  40            : "=a" (fl1) : "0" (0) : "edx", "cc");
  41 #endif
  42   if (fl1 == 0)
  43     return (0);
  44
  45   /* Invoke CPUID(1), return %edx; caller can examine bits to
  46      determine what's supported.  */
  47 #ifdef __x86_64__
  48   __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx"
  49            : "=d" (fl2), "=a" (fl1) : "1" (1) : "cc");
  50 #else
  51   __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
  52            : "=d" (fl2), "=a" (fl1) : "1" (1) : "cc");
  53 #endif
  54
  55   return fl2;
  56 }