gnu/dist/gdb6/gdb/ia64-linux-nat.c

   1 /* Functions specific to running gdb native on IA-64 running
   2    GNU/Linux.
   3
   4    Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
   5    Free Software Foundation, Inc.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 2 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22    Boston, MA 02110-1301, USA.  */
  23
  24 #include "defs.h"
  25 #include "gdb_string.h"
  26 #include "inferior.h"
  27 #include "target.h"
  28 #include "gdbcore.h"
  29 #include "regcache.h"
  30 #include "ia64-tdep.h"
  31 #include "linux-nat.h"
  32
  33 #include <signal.h>
  34 #include <sys/ptrace.h>
  35 #include "gdb_wait.h"
  36 #ifdef HAVE_SYS_REG_H
  37 #include <sys/reg.h>
  38 #endif
  39 #include <sys/syscall.h>
  40 #include <sys/user.h>
  41
  42 #include <asm/ptrace_offsets.h>
  43 #include <sys/procfs.h>
  44
  45 /* Prototypes for supply_gregset etc. */
  46 #include "gregset.h"
  47
  48 /* These must match the order of the register names.
  49
  50    Some sort of lookup table is needed because the offsets associated
  51    with the registers are all over the board.  */
  52
  53 static int u_offsets[] =
  54   {
  55     /* general registers */
  56     -1,         /* gr0 not available; i.e, it's always zero */
  57     PT_R1,
  58     PT_R2,
  59     PT_R3,
  60     PT_R4,
  61     PT_R5,
  62     PT_R6,
  63     PT_R7,
  64     PT_R8,
  65     PT_R9,
  66     PT_R10,
  67     PT_R11,
  68     PT_R12,
  69     PT_R13,
  70     PT_R14,
  71     PT_R15,
  72     PT_R16,
  73     PT_R17,
  74     PT_R18,
  75     PT_R19,
  76     PT_R20,
  77     PT_R21,
  78     PT_R22,
  79     PT_R23,
  80     PT_R24,
  81     PT_R25,
  82     PT_R26,
  83     PT_R27,
  84     PT_R28,
  85     PT_R29,
  86     PT_R30,
  87     PT_R31,
  88     /* gr32 through gr127 not directly available via the ptrace interface */
  89     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  90     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  91     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  92     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  93     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  94     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
  95     /* Floating point registers */
  96     -1, -1,     /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
  97     PT_F2,
  98     PT_F3,
  99     PT_F4,
 100     PT_F5,
 101     PT_F6,
 102     PT_F7,
 103     PT_F8,
 104     PT_F9,
 105     PT_F10,
 106     PT_F11,
 107     PT_F12,
 108     PT_F13,
 109     PT_F14,
 110     PT_F15,
 111     PT_F16,
 112     PT_F17,
 113     PT_F18,
 114     PT_F19,
 115     PT_F20,
 116     PT_F21,
 117     PT_F22,
 118     PT_F23,
 119     PT_F24,
 120     PT_F25,
 121     PT_F26,
 122     PT_F27,
 123     PT_F28,
 124     PT_F29,
 125     PT_F30,
 126     PT_F31,
 127     PT_F32,
 128     PT_F33,
 129     PT_F34,
 130     PT_F35,
 131     PT_F36,
 132     PT_F37,
 133     PT_F38,
 134     PT_F39,
 135     PT_F40,
 136     PT_F41,
 137     PT_F42,
 138     PT_F43,
 139     PT_F44,
 140     PT_F45,
 141     PT_F46,
 142     PT_F47,
 143     PT_F48,
 144     PT_F49,
 145     PT_F50,
 146     PT_F51,
 147     PT_F52,
 148     PT_F53,
 149     PT_F54,
 150     PT_F55,
 151     PT_F56,
 152     PT_F57,
 153     PT_F58,
 154     PT_F59,
 155     PT_F60,
 156     PT_F61,
 157     PT_F62,
 158     PT_F63,
 159     PT_F64,
 160     PT_F65,
 161     PT_F66,
 162     PT_F67,
 163     PT_F68,
 164     PT_F69,
 165     PT_F70,
 166     PT_F71,
 167     PT_F72,
 168     PT_F73,
 169     PT_F74,
 170     PT_F75,
 171     PT_F76,
 172     PT_F77,
 173     PT_F78,
 174     PT_F79,
 175     PT_F80,
 176     PT_F81,
 177     PT_F82,
 178     PT_F83,
 179     PT_F84,
 180     PT_F85,
 181     PT_F86,
 182     PT_F87,
 183     PT_F88,
 184     PT_F89,
 185     PT_F90,
 186     PT_F91,
 187     PT_F92,
 188     PT_F93,
 189     PT_F94,
 190     PT_F95,
 191     PT_F96,
 192     PT_F97,
 193     PT_F98,
 194     PT_F99,
 195     PT_F100,
 196     PT_F101,
 197     PT_F102,
 198     PT_F103,
 199     PT_F104,
 200     PT_F105,
 201     PT_F106,
 202     PT_F107,
 203     PT_F108,
 204     PT_F109,
 205     PT_F110,
 206     PT_F111,
 207     PT_F112,
 208     PT_F113,
 209     PT_F114,
 210     PT_F115,
 211     PT_F116,
 212     PT_F117,
 213     PT_F118,
 214     PT_F119,
 215     PT_F120,
 216     PT_F121,
 217     PT_F122,
 218     PT_F123,
 219     PT_F124,
 220     PT_F125,
 221     PT_F126,
 222     PT_F127,
 223     /* predicate registers - we don't fetch these individually */
 224     -1, -1, -1, -1, -1, -1, -1, -1,
 225     -1, -1, -1, -1, -1, -1, -1, -1,
 226     -1, -1, -1, -1, -1, -1, -1, -1,
 227     -1, -1, -1, -1, -1, -1, -1, -1,
 228     -1, -1, -1, -1, -1, -1, -1, -1,
 229     -1, -1, -1, -1, -1, -1, -1, -1,
 230     -1, -1, -1, -1, -1, -1, -1, -1,
 231     -1, -1, -1, -1, -1, -1, -1, -1,
 232     /* branch registers */
 233     PT_B0,
 234     PT_B1,
 235     PT_B2,
 236     PT_B3,
 237     PT_B4,
 238     PT_B5,
 239     PT_B6,
 240     PT_B7,
 241     /* virtual frame pointer and virtual return address pointer */
 242     -1, -1,
 243     /* other registers */
 244     PT_PR,
 245     PT_CR_IIP,  /* ip */
 246     PT_CR_IPSR, /* psr */
 247     PT_CFM,     /* cfm */
 248     /* kernel registers not visible via ptrace interface (?) */
 249     -1, -1, -1, -1, -1, -1, -1, -1,
 250     /* hole */
 251     -1, -1, -1, -1, -1, -1, -1, -1,
 252     PT_AR_RSC,
 253     PT_AR_BSP,
 254     PT_AR_BSPSTORE,
 255     PT_AR_RNAT,
 256     -1,
 257     -1,         /* Not available: FCR, IA32 floating control register */
 258     -1, -1,
 259     -1,         /* Not available: EFLAG */
 260     -1,         /* Not available: CSD */
 261     -1,         /* Not available: SSD */
 262     -1,         /* Not available: CFLG */
 263     -1,         /* Not available: FSR */
 264     -1,         /* Not available: FIR */
 265     -1,         /* Not available: FDR */
 266     -1,
 267     PT_AR_CCV,
 268     -1, -1, -1,
 269     PT_AR_UNAT,
 270     -1, -1, -1,
 271     PT_AR_FPSR,
 272     -1, -1, -1,
 273     -1,         /* Not available: ITC */
 274     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 275     -1, -1, -1, -1, -1, -1, -1, -1, -1,
 276     PT_AR_PFS,
 277     PT_AR_LC,
 278     -1,         /* Not available: EC, the Epilog Count register */
 279     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 280     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 281     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 282     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 283     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 284     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
 285     -1,
 286     /* nat bits - not fetched directly; instead we obtain these bits from
 287        either rnat or unat or from memory. */
 288     -1, -1, -1, -1, -1, -1, -1, -1,
 289     -1, -1, -1, -1, -1, -1, -1, -1,
 290     -1, -1, -1, -1, -1, -1, -1, -1,
 291     -1, -1, -1, -1, -1, -1, -1, -1,
 292     -1, -1, -1, -1, -1, -1, -1, -1,
 293     -1, -1, -1, -1, -1, -1, -1, -1,
 294     -1, -1, -1, -1, -1, -1, -1, -1,
 295     -1, -1, -1, -1, -1, -1, -1, -1,
 296     -1, -1, -1, -1, -1, -1, -1, -1,
 297     -1, -1, -1, -1, -1, -1, -1, -1,
 298     -1, -1, -1, -1, -1, -1, -1, -1,
 299     -1, -1, -1, -1, -1, -1, -1, -1,
 300     -1, -1, -1, -1, -1, -1, -1, -1,
 301     -1, -1, -1, -1, -1, -1, -1, -1,
 302     -1, -1, -1, -1, -1, -1, -1, -1,
 303     -1, -1, -1, -1, -1, -1, -1, -1,
 304   };
 305
 306 CORE_ADDR
 307 register_addr (int regno, CORE_ADDR blockend)
 308 {
 309   CORE_ADDR addr;
 310
 311   if (regno < 0 || regno >= NUM_REGS)
 312     error (_("Invalid register number %d."), regno);
 313
 314   if (u_offsets[regno] == -1)
 315     addr = 0;
 316   else
 317     addr = (CORE_ADDR) u_offsets[regno];
 318
 319   return addr;
 320 }
 321
 322 int ia64_cannot_fetch_register (regno)
 323      int regno;
 324 {
 325   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1;
 326 }
 327
 328 int ia64_cannot_store_register (regno)
 329      int regno;
 330 {
 331   /* Rationale behind not permitting stores to bspstore...
 332
 333      The IA-64 architecture provides bspstore and bsp which refer
 334      memory locations in the RSE's backing store.  bspstore is the
 335      next location which will be written when the RSE needs to write
 336      to memory.  bsp is the address at which r32 in the current frame
 337      would be found if it were written to the backing store.
 338
 339      The IA-64 architecture provides read-only access to bsp and
 340      read/write access to bspstore (but only when the RSE is in
 341      the enforced lazy mode).  It should be noted that stores
 342      to bspstore also affect the value of bsp.  Changing bspstore
 343      does not affect the number of dirty entries between bspstore
 344      and bsp, so changing bspstore by N words will also cause bsp
 345      to be changed by (roughly) N as well.  (It could be N-1 or N+1
 346      depending upon where the NaT collection bits fall.)
 347
 348      OTOH, the Linux kernel provides read/write access to bsp (and
 349      currently read/write access to bspstore as well).  But it
 350      is definitely the case that if you change one, the other
 351      will change at the same time.  It is more useful to gdb to
 352      be able to change bsp.  So in order to prevent strange and
 353      undesirable things from happening when a dummy stack frame
 354      is popped (after calling an inferior function), we allow
 355      bspstore to be read, but not written.  (Note that popping
 356      a (generic) dummy stack frame causes all registers that
 357      were previously read from the inferior process to be written
 358      back.)  */
 359
 360   return regno < 0 || regno >= NUM_REGS || u_offsets[regno] == -1
 361          || regno == IA64_BSPSTORE_REGNUM;
 362 }
 363
 364 void
 365 supply_gregset (gregset_t *gregsetp)
 366 {
 367   int regi;
 368   greg_t *regp = (greg_t *) gregsetp;
 369
 370   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 371     {
 372       regcache_raw_supply (current_regcache, regi,
 373                            (char *) (regp + (regi - IA64_GR0_REGNUM)));
 374     }
 375
 376   /* FIXME: NAT collection bits are at index 32; gotta deal with these
 377      somehow... */
 378
 379   regcache_raw_supply (current_regcache, IA64_PR_REGNUM, (char *) (regp + 33));
 380
 381   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 382     {
 383       regcache_raw_supply (current_regcache, regi,
 384                            (char *) (regp + 34 + (regi - IA64_BR0_REGNUM)));
 385     }
 386
 387   regcache_raw_supply (current_regcache, IA64_IP_REGNUM,
 388                        (char *) (regp + 42));
 389   regcache_raw_supply (current_regcache, IA64_CFM_REGNUM,
 390                        (char *) (regp + 43));
 391   regcache_raw_supply (current_regcache, IA64_PSR_REGNUM,
 392                        (char *) (regp + 44));
 393   regcache_raw_supply (current_regcache, IA64_RSC_REGNUM,
 394                        (char *) (regp + 45));
 395   regcache_raw_supply (current_regcache, IA64_BSP_REGNUM,
 396                        (char *) (regp + 46));
 397   regcache_raw_supply (current_regcache, IA64_BSPSTORE_REGNUM,
 398                        (char *) (regp + 47));
 399   regcache_raw_supply (current_regcache, IA64_RNAT_REGNUM,
 400                        (char *) (regp + 48));
 401   regcache_raw_supply (current_regcache, IA64_CCV_REGNUM,
 402                        (char *) (regp + 49));
 403   regcache_raw_supply (current_regcache, IA64_UNAT_REGNUM,
 404                        (char *) (regp + 50));
 405   regcache_raw_supply (current_regcache, IA64_FPSR_REGNUM,
 406                        (char *) (regp + 51));
 407   regcache_raw_supply (current_regcache, IA64_PFS_REGNUM,
 408                        (char *) (regp + 52));
 409   regcache_raw_supply (current_regcache, IA64_LC_REGNUM,
 410                        (char *) (regp + 53));
 411   regcache_raw_supply (current_regcache, IA64_EC_REGNUM,
 412                        (char *) (regp + 54));
 413 }
 414
 415 void
 416 fill_gregset (gregset_t *gregsetp, int regno)
 417 {
 418   int regi;
 419   greg_t *regp = (greg_t *) gregsetp;
 420
 421 #define COPY_REG(_idx_,_regi_) \
 422   if ((regno == -1) || regno == _regi_) \
 423     regcache_raw_collect (current_regcache, _regi_, regp + _idx_)
 424
 425   for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
 426     {
 427       COPY_REG (regi - IA64_GR0_REGNUM, regi);
 428     }
 429
 430   /* FIXME: NAT collection bits at index 32? */
 431
 432   COPY_REG (33, IA64_PR_REGNUM);
 433
 434   for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
 435     {
 436       COPY_REG (34 + (regi - IA64_BR0_REGNUM), regi);
 437     }
 438
 439   COPY_REG (42, IA64_IP_REGNUM);
 440   COPY_REG (43, IA64_CFM_REGNUM);
 441   COPY_REG (44, IA64_PSR_REGNUM);
 442   COPY_REG (45, IA64_RSC_REGNUM);
 443   COPY_REG (46, IA64_BSP_REGNUM);
 444   COPY_REG (47, IA64_BSPSTORE_REGNUM);
 445   COPY_REG (48, IA64_RNAT_REGNUM);
 446   COPY_REG (49, IA64_CCV_REGNUM);
 447   COPY_REG (50, IA64_UNAT_REGNUM);
 448   COPY_REG (51, IA64_FPSR_REGNUM);
 449   COPY_REG (52, IA64_PFS_REGNUM);
 450   COPY_REG (53, IA64_LC_REGNUM);
 451   COPY_REG (54, IA64_EC_REGNUM);
 452 }
 453
 454 /*  Given a pointer to a floating point register set in /proc format
 455    (fpregset_t *), unpack the register contents and supply them as gdb's
 456    idea of the current floating point register values. */
 457
 458 void
 459 supply_fpregset (fpregset_t *fpregsetp)
 460 {
 461   int regi;
 462   char *from;
 463
 464   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 465     {
 466       from = (char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
 467       regcache_raw_supply (current_regcache, regi, from);
 468     }
 469 }
 470
 471 /*  Given a pointer to a floating point register set in /proc format
 472    (fpregset_t *), update the register specified by REGNO from gdb's idea
 473    of the current floating point register set.  If REGNO is -1, update
 474    them all. */
 475
 476 void
 477 fill_fpregset (fpregset_t *fpregsetp, int regno)
 478 {
 479   int regi;
 480
 481   for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
 482     {
 483       if ((regno == -1) || (regno == regi))
 484         regcache_raw_collect (current_regcache, regi,
 485                               &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
 486     }
 487 }
 488
 489 #define IA64_PSR_DB (1UL << 24)
 490 #define IA64_PSR_DD (1UL << 39)
 491
 492 static void
 493 enable_watchpoints_in_psr (ptid_t ptid)
 494 {
 495   CORE_ADDR psr;
 496
 497   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 498   if (!(psr & IA64_PSR_DB))
 499     {
 500       psr |= IA64_PSR_DB;       /* Set the db bit - this enables hardware
 501                                    watchpoints and breakpoints. */
 502       write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 503     }
 504 }
 505
 506 static long
 507 fetch_debug_register (ptid_t ptid, int idx)
 508 {
 509   long val;
 510   int tid;
 511
 512   tid = TIDGET (ptid);
 513   if (tid == 0)
 514     tid = PIDGET (ptid);
 515
 516   val = ptrace (PT_READ_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), 0);
 517
 518   return val;
 519 }
 520
 521 static void
 522 store_debug_register (ptid_t ptid, int idx, long val)
 523 {
 524   int tid;
 525
 526   tid = TIDGET (ptid);
 527   if (tid == 0)
 528     tid = PIDGET (ptid);
 529
 530   (void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
 531 }
 532
 533 static void
 534 fetch_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 535 {
 536   if (dbr_addr)
 537     *dbr_addr = fetch_debug_register (ptid, 2 * idx);
 538   if (dbr_mask)
 539     *dbr_mask = fetch_debug_register (ptid, 2 * idx + 1);
 540 }
 541
 542 static void
 543 store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
 544 {
 545   if (dbr_addr)
 546     store_debug_register (ptid, 2 * idx, *dbr_addr);
 547   if (dbr_mask)
 548     store_debug_register (ptid, 2 * idx + 1, *dbr_mask);
 549 }
 550
 551 static int
 552 is_power_of_2 (int val)
 553 {
 554   int i, onecount;
 555
 556   onecount = 0;
 557   for (i = 0; i < 8 * sizeof (val); i++)
 558     if (val & (1 << i))
 559       onecount++;
 560
 561   return onecount <= 1;
 562 }
 563
 564 int
 565 ia64_linux_insert_watchpoint (ptid_t ptid, CORE_ADDR addr, int len, int rw)
 566 {
 567   int idx;
 568   long dbr_addr, dbr_mask;
 569   int max_watchpoints = 4;
 570
 571   if (len <= 0 || !is_power_of_2 (len))
 572     return -1;
 573
 574   for (idx = 0; idx < max_watchpoints; idx++)
 575     {
 576       fetch_debug_register_pair (ptid, idx, NULL, &dbr_mask);
 577       if ((dbr_mask & (0x3UL << 62)) == 0)
 578         {
 579           /* Exit loop if both r and w bits clear */
 580           break;
 581         }
 582     }
 583
 584   if (idx == max_watchpoints)
 585     return -1;
 586
 587   dbr_addr = (long) addr;
 588   dbr_mask = (~(len - 1) & 0x00ffffffffffffffL);  /* construct mask to match */
 589   dbr_mask |= 0x0800000000000000L;           /* Only match privilege level 3 */
 590   switch (rw)
 591     {
 592     case hw_write:
 593       dbr_mask |= (1L << 62);                   /* Set w bit */
 594       break;
 595     case hw_read:
 596       dbr_mask |= (1L << 63);                   /* Set r bit */
 597       break;
 598     case hw_access:
 599       dbr_mask |= (3L << 62);                   /* Set both r and w bits */
 600       break;
 601     default:
 602       return -1;
 603     }
 604
 605   store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 606   enable_watchpoints_in_psr (ptid);
 607
 608   return 0;
 609 }
 610
 611 int
 612 ia64_linux_remove_watchpoint (ptid_t ptid, CORE_ADDR addr, int len)
 613 {
 614   int idx;
 615   long dbr_addr, dbr_mask;
 616   int max_watchpoints = 4;
 617
 618   if (len <= 0 || !is_power_of_2 (len))
 619     return -1;
 620
 621   for (idx = 0; idx < max_watchpoints; idx++)
 622     {
 623       fetch_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 624       if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
 625         {
 626           dbr_addr = 0;
 627           dbr_mask = 0;
 628           store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
 629           return 0;
 630         }
 631     }
 632   return -1;
 633 }
 634
 635 int
 636 ia64_linux_stopped_data_address (CORE_ADDR *addr_p)
 637 {
 638   CORE_ADDR psr;
 639   int tid;
 640   struct siginfo siginfo;
 641   ptid_t ptid = inferior_ptid;
 642
 643   tid = TIDGET(ptid);
 644   if (tid == 0)
 645     tid = PIDGET (ptid);
 646
 647   errno = 0;
 648   ptrace (PTRACE_GETSIGINFO, tid, (PTRACE_TYPE_ARG3) 0, &siginfo);
 649
 650   if (errno != 0 || siginfo.si_signo != SIGTRAP ||
 651       (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
 652     return 0;
 653
 654   psr = read_register_pid (IA64_PSR_REGNUM, ptid);
 655   psr |= IA64_PSR_DD;   /* Set the dd bit - this will disable the watchpoint
 656                            for the next instruction */
 657   write_register_pid (IA64_PSR_REGNUM, psr, ptid);
 658
 659   *addr_p = (CORE_ADDR)siginfo.si_addr;
 660   return 1;
 661 }
 662
 663 int
 664 ia64_linux_stopped_by_watchpoint (void)
 665 {
 666   CORE_ADDR addr;
 667   return ia64_linux_stopped_data_address (&addr);
 668 }
 669
 670 static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
 671                                       const char *, gdb_byte *, const gdb_byte *,
 672                                       ULONGEST, LONGEST);
 673
 674 static LONGEST
 675 ia64_linux_xfer_partial (struct target_ops *ops,
 676                          enum target_object object,
 677                          const char *annex,
 678                          gdb_byte *readbuf, const gdb_byte *writebuf,
 679                          ULONGEST offset, LONGEST len)
 680 {
 681   if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
 682     return syscall (__NR_getunwind, readbuf, len);
 683
 684   return super_xfer_partial (ops, object, annex, readbuf, writebuf,
 685                              offset, len);
 686 }
 687
 688 void _initialize_ia64_linux_nat (void);
 689
 690 void
 691 _initialize_ia64_linux_nat (void)
 692 {
 693   struct target_ops *t = linux_target ();
 694
 695   /* Fill in the generic GNU/Linux methods.  */
 696   t = linux_target ();
 697
 698   /* Override the default to_xfer_partial.  */
 699   super_xfer_partial = t->to_xfer_partial;
 700   t->to_xfer_partial = ia64_linux_xfer_partial;
 701
 702   /* Register the target.  */
 703   linux_nat_add_target (t);
 704 }