gnu/dist/gdb6/sim/cris/cpuv32.h

   1 /* CPU family header for crisv32f.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #ifndef CPU_CRISV32F_H
  26 #define CPU_CRISV32F_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 1
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) \
  43 do { \
  44 CPU (h_pc) = ANDSI ((x), (~ (1)));\
  45 ;} while (0)
  46   /* General purpose registers */
  47   SI h_gr_acr[16];
  48 #define GET_H_GR_ACR(a1) CPU (h_gr_acr)[a1]
  49 #define SET_H_GR_ACR(a1, x) (CPU (h_gr_acr)[a1] = (x))
  50   /* Special registers for v32 */
  51   SI h_sr_v32[16];
  52 #define GET_H_SR_V32(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (32) : (((index) == (((UINT) 13)))) ? (ORSI (ANDSI (CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), ORSI (SLLSI (ZEXTBISI (CPU (h_rbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_sbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_mbit)), 30), ORSI (SLLSI (ZEXTBISI (CPU (h_qbit)), 31), 0)))))))))))))) : (((index) == (((UINT) 14)))) ? (((GET_H_UBIT ()) ? (CPU (h_gr_acr[((UINT) 14)])) : (CPU (h_sr_v32[((UINT) 14)])))) : (CPU (h_sr_v32[index]))
  53 #define SET_H_SR_V32(index, x) \
  54 do { \
  55 if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
  56 ((void) 0); /*nop*/\
  57 }\
  58  else if ((((index)) == (((UINT) 13)))) {\
  59 {\
  60 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
  61 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
  62 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
  63 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
  64 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
  65 SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
  66 SET_H_SBIT (((NESI (ANDSI ((x), ((1) << (9))), 0)) ? (1) : (0)));\
  67 SET_H_MBIT (((NESI (ANDSI ((x), ((1) << (30))), 0)) ? (1) : (0)));\
  68 CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
  69 CPU (h_rbit) = ((NESI (ANDSI ((x), ((1) << (8))), 0)) ? (1) : (0));\
  70 SET_H_QBIT (((NESI (ANDSI ((x), ((1) << (31))), 0)) ? (1) : (0)));\
  71 SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
  72 CPU (h_sr_v32[(index)]) = (x);\
  73 }\
  74 }\
  75  else if ((((index)) == (((UINT) 14)))) {\
  76 {\
  77 if (GET_H_UBIT ()) {\
  78 CPU (h_gr_acr[((UINT) 14)]) = (x);\
  79 }\
  80 CPU (h_sr_v32[((UINT) 14)]) = (x);\
  81 }\
  82 }\
  83  else if ((((index)) == (((UINT) 3)))) {\
  84 if (NOTBI (GET_H_UBIT ())) {\
  85 CPU (h_sr_v32[((UINT) 3)]) = (x);\
  86 }\
  87 }\
  88  else if ((((index)) == (((UINT) 9)))) {\
  89 if (NOTBI (GET_H_UBIT ())) {\
  90 CPU (h_sr_v32[((UINT) 9)]) = (x);\
  91 }\
  92 }\
  93  else if ((((index)) == (((UINT) 2)))) {\
  94 if (NOTBI (GET_H_UBIT ())) {\
  95 {\
  96 crisv32f_write_pid_handler (current_cpu, (x));\
  97 CPU (h_sr_v32[((UINT) 2)]) = (x);\
  98 }\
  99 }\
 100 }\
 101  else if ((((index)) == (((UINT) 15)))) {\
 102 if (NOTBI (GET_H_UBIT ())) {\
 103 CPU (h_sr_v32[((UINT) 15)]) = (x);\
 104 }\
 105 }\
 106  else {\
 107 CPU (h_sr_v32[(index)]) = (x);\
 108 }\
 109 ;} while (0)
 110   /* carry bit */
 111   BI h_cbit;
 112 #define GET_H_CBIT() CPU (h_cbit)
 113 #define SET_H_CBIT(x) (CPU (h_cbit) = (x))
 114   /* overflow bit */
 115   BI h_vbit;
 116 #define GET_H_VBIT() CPU (h_vbit)
 117 #define SET_H_VBIT(x) (CPU (h_vbit) = (x))
 118   /* zero bit */
 119   BI h_zbit;
 120 #define GET_H_ZBIT() CPU (h_zbit)
 121 #define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
 122   /* sign bit */
 123   BI h_nbit;
 124 #define GET_H_NBIT() CPU (h_nbit)
 125 #define SET_H_NBIT(x) (CPU (h_nbit) = (x))
 126   /* extended-arithmetic bit */
 127   BI h_xbit;
 128 #define GET_H_XBIT() CPU (h_xbit)
 129 #define SET_H_XBIT(x) (CPU (h_xbit) = (x))
 130   /* sequence-broken bit */
 131   BI h_pbit;
 132 #define GET_H_PBIT() CPU (h_pbit)
 133 #define SET_H_PBIT(x) (CPU (h_pbit) = (x))
 134   /* carry bit for MCP+restore-p bit */
 135   BI h_rbit;
 136 #define GET_H_RBIT() CPU (h_rbit)
 137 #define SET_H_RBIT(x) (CPU (h_rbit) = (x))
 138   /* guru mode bit */
 139   BI h_gbit;
 140 #define GET_H_GBIT() CPU (h_gbit)
 141 #define SET_H_GBIT(x) (CPU (h_gbit) = (x))
 142   /* Kernel stack pointer during user mode */
 143   SI h_kernel_sp;
 144 #define GET_H_KERNEL_SP() CPU (h_kernel_sp)
 145 #define SET_H_KERNEL_SP(x) (CPU (h_kernel_sp) = (x))
 146   /* User mode bit */
 147   BI h_ubit_v32;
 148 #define GET_H_UBIT_V32() CPU (h_ubit_v32)
 149 #define SET_H_UBIT_V32(x) \
 150 do { \
 151 {\
 152 if (ANDIF ((x), NOTBI (CPU (h_ubit_v32)))) {\
 153 {\
 154 CPU (h_kernel_sp) = CPU (h_gr_acr[((UINT) 14)]);\
 155 CPU (h_gr_acr[((UINT) 14)]) = CPU (h_sr_v32[((UINT) 14)]);\
 156 CPU (h_ubit_v32) = (x);\
 157 crisv32f_usermode_enabled (current_cpu);\
 158 }\
 159 }\
 160 }\
 161 ;} while (0)
 162   /* Interrupt-enable bit */
 163   BI h_ibit_v32;
 164 #define GET_H_IBIT_V32() CPU (h_ibit_v32)
 165 #define SET_H_IBIT_V32(x) \
 166 do { \
 167 {\
 168 if (NOTBI (GET_H_UBIT ())) {\
 169 {\
 170   BI tmp_enabled;\
 171   tmp_enabled = ANDIF ((x), NOTBI (CPU (h_ibit_v32)));\
 172 CPU (h_ibit_v32) = (x);\
 173 if (tmp_enabled) {\
 174 crisv32f_interrupts_enabled (current_cpu);\
 175 }\
 176 }\
 177 }\
 178 }\
 179 ;} while (0)
 180   /* NMI enable bit */
 181   BI h_mbit;
 182 #define GET_H_MBIT() CPU (h_mbit)
 183 #define SET_H_MBIT(x) \
 184 do { \
 185 {\
 186 if (ANDIF ((x), ANDIF (NOTBI (CPU (h_mbit)), NOTBI (GET_H_UBIT ())))) {\
 187 {\
 188 CPU (h_mbit) = 1;\
 189 crisv32f_nmi_enabled (current_cpu);\
 190 }\
 191 }\
 192 }\
 193 ;} while (0)
 194   /* Pending single-step bit */
 195   BI h_qbit;
 196 #define GET_H_QBIT() CPU (h_qbit)
 197 #define SET_H_QBIT(x) \
 198 do { \
 199 {\
 200 if (NOTBI (GET_H_UBIT ())) {\
 201 CPU (h_qbit) = (x);\
 202 }\
 203 }\
 204 ;} while (0)
 205   /* Cause single step exception on ... [see CRISv32 ref] bit */
 206   BI h_sbit;
 207 #define GET_H_SBIT() CPU (h_sbit)
 208 #define SET_H_SBIT(x) \
 209 do { \
 210 {\
 211 if (NOTBI (GET_H_UBIT ())) {\
 212 {\
 213   BI tmp_enabled;\
 214   tmp_enabled = ANDIF ((x), NOTBI (CPU (h_sbit)));\
 215 CPU (h_sbit) = (x);\
 216 if (tmp_enabled) {\
 217 crisv32f_single_step_enabled (current_cpu);\
 218 }\
 219 }\
 220 }\
 221 }\
 222 ;} while (0)
 223   } hardware;
 224 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 225 } CRISV32F_CPU_DATA;
 226
 227 /* Virtual regs.  */
 228
 229 #define GET_H_V32_V32() 1
 230 #define SET_H_V32_V32(x) \
 231 do { \
 232 cgen_rtx_error (current_cpu, "Can't set h-v32");\
 233 ;} while (0)
 234 #define GET_H_GR(index) CPU (h_gr_acr[index])
 235 #define SET_H_GR(index, x) \
 236 do { \
 237 CPU (h_gr_acr[(index)]) = (x);\
 238 ;} while (0)
 239 #define GET_H_RAW_GR_ACR(index) CPU (h_gr_acr[index])
 240 #define SET_H_RAW_GR_ACR(index, x) \
 241 do { \
 242 CPU (h_gr_acr[(index)]) = (x);\
 243 ;} while (0)
 244 #define GET_H_SR(index) GET_H_SR_V32 (index)
 245 #define SET_H_SR(index, x) \
 246 do { \
 247 SET_H_SR_V32 ((index), (x));\
 248 ;} while (0)
 249 #define GET_H_SUPR(index) crisv32f_read_supr (current_cpu, index)
 250 #define SET_H_SUPR(index, x) \
 251 do { \
 252 crisv32f_write_supr (current_cpu, (index), (x));\
 253 ;} while (0)
 254 #define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_V32 ()
 255 #define SET_H_CBIT_MOVE(x) \
 256 do { \
 257 SET_H_CBIT_MOVE_V32 ((x));\
 258 ;} while (0)
 259 #define GET_H_CBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-cbit-move on CRISv32"), 0)
 260 #define SET_H_CBIT_MOVE_V32(x) \
 261 do { \
 262 ((void) 0); /*nop*/\
 263 ;} while (0)
 264 #define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_V32 ()
 265 #define SET_H_VBIT_MOVE(x) \
 266 do { \
 267 SET_H_VBIT_MOVE_V32 ((x));\
 268 ;} while (0)
 269 #define GET_H_VBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-vbit-move on CRISv32"), 0)
 270 #define SET_H_VBIT_MOVE_V32(x) \
 271 do { \
 272 ((void) 0); /*nop*/\
 273 ;} while (0)
 274 #define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_V32 ()
 275 #define SET_H_ZBIT_MOVE(x) \
 276 do { \
 277 SET_H_ZBIT_MOVE_V32 ((x));\
 278 ;} while (0)
 279 #define GET_H_ZBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-zbit-move on CRISv32"), 0)
 280 #define SET_H_ZBIT_MOVE_V32(x) \
 281 do { \
 282 ((void) 0); /*nop*/\
 283 ;} while (0)
 284 #define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_V32 ()
 285 #define SET_H_NBIT_MOVE(x) \
 286 do { \
 287 SET_H_NBIT_MOVE_V32 ((x));\
 288 ;} while (0)
 289 #define GET_H_NBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-nbit-move on CRISv32"), 0)
 290 #define SET_H_NBIT_MOVE_V32(x) \
 291 do { \
 292 ((void) 0); /*nop*/\
 293 ;} while (0)
 294 #define GET_H_IBIT() CPU (h_ibit_v32)
 295 #define SET_H_IBIT(x) \
 296 do { \
 297 SET_H_IBIT_V32 ((x));\
 298 ;} while (0)
 299 #define GET_H_UBIT() CPU (h_ubit_v32)
 300 #define SET_H_UBIT(x) \
 301 do { \
 302 SET_H_UBIT_V32 ((x));\
 303 ;} while (0)
 304 #define GET_H_INSN_PREFIXED_P() GET_H_INSN_PREFIXED_P_V32 ()
 305 #define SET_H_INSN_PREFIXED_P(x) \
 306 do { \
 307 SET_H_INSN_PREFIXED_P_V32 ((x));\
 308 ;} while (0)
 309 #define GET_H_INSN_PREFIXED_P_V32() 0
 310 #define SET_H_INSN_PREFIXED_P_V32(x) \
 311 do { \
 312 ((void) 0); /*nop*/\
 313 ;} while (0)
 314 #define GET_H_PREFIXREG_V32() GET_H_GR (((UINT) 15))
 315 #define SET_H_PREFIXREG_V32(x) \
 316 do { \
 317 SET_H_GR (((UINT) 15), (x));\
 318 ;} while (0)
 319
 320 /* Cover fns for register access.  */
 321 BI crisv32f_h_v32_v32_get (SIM_CPU *);
 322 void crisv32f_h_v32_v32_set (SIM_CPU *, BI);
 323 USI crisv32f_h_pc_get (SIM_CPU *);
 324 void crisv32f_h_pc_set (SIM_CPU *, USI);
 325 SI crisv32f_h_gr_get (SIM_CPU *, UINT);
 326 void crisv32f_h_gr_set (SIM_CPU *, UINT, SI);
 327 SI crisv32f_h_gr_acr_get (SIM_CPU *, UINT);
 328 void crisv32f_h_gr_acr_set (SIM_CPU *, UINT, SI);
 329 SI crisv32f_h_raw_gr_acr_get (SIM_CPU *, UINT);
 330 void crisv32f_h_raw_gr_acr_set (SIM_CPU *, UINT, SI);
 331 SI crisv32f_h_sr_get (SIM_CPU *, UINT);
 332 void crisv32f_h_sr_set (SIM_CPU *, UINT, SI);
 333 SI crisv32f_h_sr_v32_get (SIM_CPU *, UINT);
 334 void crisv32f_h_sr_v32_set (SIM_CPU *, UINT, SI);
 335 SI crisv32f_h_supr_get (SIM_CPU *, UINT);
 336 void crisv32f_h_supr_set (SIM_CPU *, UINT, SI);
 337 BI crisv32f_h_cbit_get (SIM_CPU *);
 338 void crisv32f_h_cbit_set (SIM_CPU *, BI);
 339 BI crisv32f_h_cbit_move_get (SIM_CPU *);
 340 void crisv32f_h_cbit_move_set (SIM_CPU *, BI);
 341 BI crisv32f_h_cbit_move_v32_get (SIM_CPU *);
 342 void crisv32f_h_cbit_move_v32_set (SIM_CPU *, BI);
 343 BI crisv32f_h_vbit_get (SIM_CPU *);
 344 void crisv32f_h_vbit_set (SIM_CPU *, BI);
 345 BI crisv32f_h_vbit_move_get (SIM_CPU *);
 346 void crisv32f_h_vbit_move_set (SIM_CPU *, BI);
 347 BI crisv32f_h_vbit_move_v32_get (SIM_CPU *);
 348 void crisv32f_h_vbit_move_v32_set (SIM_CPU *, BI);
 349 BI crisv32f_h_zbit_get (SIM_CPU *);
 350 void crisv32f_h_zbit_set (SIM_CPU *, BI);
 351 BI crisv32f_h_zbit_move_get (SIM_CPU *);
 352 void crisv32f_h_zbit_move_set (SIM_CPU *, BI);
 353 BI crisv32f_h_zbit_move_v32_get (SIM_CPU *);
 354 void crisv32f_h_zbit_move_v32_set (SIM_CPU *, BI);
 355 BI crisv32f_h_nbit_get (SIM_CPU *);
 356 void crisv32f_h_nbit_set (SIM_CPU *, BI);
 357 BI crisv32f_h_nbit_move_get (SIM_CPU *);
 358 void crisv32f_h_nbit_move_set (SIM_CPU *, BI);
 359 BI crisv32f_h_nbit_move_v32_get (SIM_CPU *);
 360 void crisv32f_h_nbit_move_v32_set (SIM_CPU *, BI);
 361 BI crisv32f_h_xbit_get (SIM_CPU *);
 362 void crisv32f_h_xbit_set (SIM_CPU *, BI);
 363 BI crisv32f_h_ibit_get (SIM_CPU *);
 364 void crisv32f_h_ibit_set (SIM_CPU *, BI);
 365 BI crisv32f_h_pbit_get (SIM_CPU *);
 366 void crisv32f_h_pbit_set (SIM_CPU *, BI);
 367 BI crisv32f_h_rbit_get (SIM_CPU *);
 368 void crisv32f_h_rbit_set (SIM_CPU *, BI);
 369 BI crisv32f_h_ubit_get (SIM_CPU *);
 370 void crisv32f_h_ubit_set (SIM_CPU *, BI);
 371 BI crisv32f_h_gbit_get (SIM_CPU *);
 372 void crisv32f_h_gbit_set (SIM_CPU *, BI);
 373 SI crisv32f_h_kernel_sp_get (SIM_CPU *);
 374 void crisv32f_h_kernel_sp_set (SIM_CPU *, SI);
 375 BI crisv32f_h_ubit_v32_get (SIM_CPU *);
 376 void crisv32f_h_ubit_v32_set (SIM_CPU *, BI);
 377 BI crisv32f_h_ibit_v32_get (SIM_CPU *);
 378 void crisv32f_h_ibit_v32_set (SIM_CPU *, BI);
 379 BI crisv32f_h_mbit_get (SIM_CPU *);
 380 void crisv32f_h_mbit_set (SIM_CPU *, BI);
 381 BI crisv32f_h_qbit_get (SIM_CPU *);
 382 void crisv32f_h_qbit_set (SIM_CPU *, BI);
 383 BI crisv32f_h_sbit_get (SIM_CPU *);
 384 void crisv32f_h_sbit_set (SIM_CPU *, BI);
 385 BI crisv32f_h_insn_prefixed_p_get (SIM_CPU *);
 386 void crisv32f_h_insn_prefixed_p_set (SIM_CPU *, BI);
 387 BI crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *);
 388 void crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *, BI);
 389 SI crisv32f_h_prefixreg_v32_get (SIM_CPU *);
 390 void crisv32f_h_prefixreg_v32_set (SIM_CPU *, SI);
 391
 392 /* These must be hand-written.  */
 393 extern CPUREG_FETCH_FN crisv32f_fetch_register;
 394 extern CPUREG_STORE_FN crisv32f_store_register;
 395
 396 typedef struct {
 397   UINT prev_prev_prev_modf_regs;
 398   UINT prev_prev_modf_regs;
 399   UINT prev_modf_regs;
 400   UINT modf_regs;
 401   UINT prev_prev_prev_movem_dest_regs;
 402   UINT prev_prev_movem_dest_regs;
 403   UINT prev_movem_dest_regs;
 404   UINT movem_dest_regs;
 405 } MODEL_CRISV32_DATA;
 406
 407 /* Instruction argument buffer.  */
 408
 409 union sem_fields {
 410   struct { /* no operands */
 411     int empty;
 412   } fmt_empty;
 413   struct { /*  */
 414     UINT f_u4;
 415   } sfmt_break;
 416   struct { /*  */
 417     UINT f_dstsrc;
 418   } sfmt_setf;
 419   struct { /*  */
 420     IADDR i_o_word_pcrel;
 421     UINT f_operand2;
 422   } sfmt_bcc_w;
 423   struct { /*  */
 424     IADDR i_o_pcrel;
 425     UINT f_operand2;
 426   } sfmt_bcc_b;
 427   struct { /*  */
 428     unsigned char in_h_sr_SI_13;
 429     unsigned char out_h_sr_SI_13;
 430   } sfmt_rfe;
 431   struct { /*  */
 432     INT f_s8;
 433     UINT f_operand2;
 434     unsigned char in_Rd;
 435   } sfmt_addoq;
 436   struct { /*  */
 437     ADDR i_const32_pcrel;
 438     UINT f_operand2;
 439     unsigned char out_Pd;
 440   } sfmt_bas_c;
 441   struct { /*  */
 442     ADDR i_qo;
 443     UINT f_operand2;
 444     unsigned char out_Rd;
 445   } sfmt_lapcq;
 446   struct { /*  */
 447     ADDR i_const32_pcrel;
 448     UINT f_operand2;
 449     unsigned char out_Rd;
 450   } sfmt_lapc_d;
 451   struct { /*  */
 452     INT f_indir_pc__dword;
 453     UINT f_operand2;
 454     unsigned char out_Pd;
 455   } sfmt_move_c_sprv32_p2;
 456   struct { /*  */
 457     INT f_s6;
 458     UINT f_operand2;
 459     unsigned char out_Rd;
 460   } sfmt_moveq;
 461   struct { /*  */
 462     INT f_indir_pc__dword;
 463     UINT f_operand2;
 464     unsigned char in_Rd;
 465     unsigned char out_Rd;
 466   } sfmt_bound_cd;
 467   struct { /*  */
 468     INT f_indir_pc__word;
 469     UINT f_operand2;
 470     unsigned char in_Rd;
 471     unsigned char out_Rd;
 472   } sfmt_bound_cw;
 473   struct { /*  */
 474     INT f_indir_pc__byte;
 475     UINT f_operand2;
 476     unsigned char in_Rd;
 477     unsigned char out_Rd;
 478   } sfmt_bound_cb;
 479   struct { /*  */
 480     UINT f_operand2;
 481     UINT f_u5;
 482     unsigned char in_Rd;
 483     unsigned char out_Rd;
 484   } sfmt_asrq;
 485   struct { /*  */
 486     INT f_s6;
 487     UINT f_operand2;
 488     unsigned char in_Rd;
 489     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 490   } sfmt_andq;
 491   struct { /*  */
 492     INT f_indir_pc__dword;
 493     UINT f_operand2;
 494     unsigned char in_Rd;
 495     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 496   } sfmt_addcdr;
 497   struct { /*  */
 498     INT f_indir_pc__word;
 499     UINT f_operand2;
 500     unsigned char in_Rd;
 501     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 502   } sfmt_addcwr;
 503   struct { /*  */
 504     INT f_indir_pc__byte;
 505     UINT f_operand2;
 506     unsigned char in_Rd;
 507     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 508   } sfmt_addcbr;
 509   struct { /*  */
 510     UINT f_operand2;
 511     UINT f_u6;
 512     unsigned char in_Rd;
 513     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 514   } sfmt_addq;
 515   struct { /*  */
 516     UINT f_operand1;
 517     UINT f_operand2;
 518     unsigned char in_Ps;
 519     unsigned char in_Rs;
 520     unsigned char out_h_gr_SI_index_of__DFLT_Rs;
 521   } sfmt_mcp;
 522   struct { /*  */
 523     UINT f_operand1;
 524     UINT f_operand2;
 525     unsigned char in_Rd;
 526     unsigned char in_Rs;
 527     unsigned char out_Rd;
 528     unsigned char out_h_sr_SI_7;
 529   } sfmt_muls_b;
 530   struct { /*  */
 531     UINT f_memmode;
 532     UINT f_operand1;
 533     UINT f_operand2;
 534     unsigned char in_Ps;
 535     unsigned char in_Rs;
 536     unsigned char out_Rs;
 537   } sfmt_move_spr_mv32;
 538   struct { /*  */
 539     UINT f_memmode;
 540     UINT f_operand1;
 541     UINT f_operand2;
 542     unsigned char in_Rs;
 543     unsigned char out_Pd;
 544     unsigned char out_Rs;
 545   } sfmt_move_m_sprv32;
 546   struct { /*  */
 547     UINT f_memmode;
 548     UINT f_operand1;
 549     UINT f_operand2;
 550     unsigned char in_Rs;
 551     unsigned char out_Rd;
 552     unsigned char out_Rs;
 553   } sfmt_movs_m_b_m;
 554   struct { /*  */
 555     UINT f_memmode;
 556     UINT f_operand1;
 557     UINT f_operand2;
 558     unsigned char in_Rd;
 559     unsigned char in_Rs;
 560     unsigned char out_Rs;
 561     unsigned char out_h_gr_SI_index_of__DFLT_Rd;
 562   } sfmt_addc_m;
 563   struct { /*  */
 564     UINT f_memmode;
 565     UINT f_operand1;
 566     UINT f_operand2;
 567     unsigned char in_Rd;
 568     unsigned char in_Rs;
 569     unsigned char out_Rs;
 570     unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
 571   } sfmt_add_m_b_m;
 572   struct { /*  */
 573     UINT f_memmode;
 574     UINT f_operand1;
 575     UINT f_operand2;
 576     unsigned char in_Rd;
 577     unsigned char in_Rs;
 578     unsigned char out_Rs;
 579     unsigned char out_h_gr_SI_0;
 580     unsigned char out_h_gr_SI_1;
 581     unsigned char out_h_gr_SI_10;
 582     unsigned char out_h_gr_SI_11;
 583     unsigned char out_h_gr_SI_12;
 584     unsigned char out_h_gr_SI_13;
 585     unsigned char out_h_gr_SI_14;
 586     unsigned char out_h_gr_SI_15;
 587     unsigned char out_h_gr_SI_2;
 588     unsigned char out_h_gr_SI_3;
 589     unsigned char out_h_gr_SI_4;
 590     unsigned char out_h_gr_SI_5;
 591     unsigned char out_h_gr_SI_6;
 592     unsigned char out_h_gr_SI_7;
 593     unsigned char out_h_gr_SI_8;
 594     unsigned char out_h_gr_SI_9;
 595   } sfmt_movem_m_r_v32;
 596   struct { /*  */
 597     UINT f_memmode;
 598     UINT f_operand1;
 599     UINT f_operand2;
 600     unsigned char in_Rd;
 601     unsigned char in_Rs;
 602     unsigned char in_h_gr_SI_0;
 603     unsigned char in_h_gr_SI_1;
 604     unsigned char in_h_gr_SI_10;
 605     unsigned char in_h_gr_SI_11;
 606     unsigned char in_h_gr_SI_12;
 607     unsigned char in_h_gr_SI_13;
 608     unsigned char in_h_gr_SI_14;
 609     unsigned char in_h_gr_SI_15;
 610     unsigned char in_h_gr_SI_2;
 611     unsigned char in_h_gr_SI_3;
 612     unsigned char in_h_gr_SI_4;
 613     unsigned char in_h_gr_SI_5;
 614     unsigned char in_h_gr_SI_6;
 615     unsigned char in_h_gr_SI_7;
 616     unsigned char in_h_gr_SI_8;
 617     unsigned char in_h_gr_SI_9;
 618     unsigned char out_Rs;
 619   } sfmt_movem_r_m_v32;
 620 #if WITH_SCACHE_PBB
 621   /* Writeback handler.  */
 622   struct {
 623     /* Pointer to argbuf entry for insn whose results need writing back.  */
 624     const struct argbuf *abuf;
 625   } write;
 626   /* x-before handler */
 627   struct {
 628     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 629     int first_p;
 630   } before;
 631   /* x-after handler */
 632   struct {
 633     int empty;
 634   } after;
 635   /* This entry is used to terminate each pbb.  */
 636   struct {
 637     /* Number of insns in pbb.  */
 638     int insn_count;
 639     /* Next pbb to execute.  */
 640     SCACHE *next;
 641     SCACHE *branch_target;
 642   } chain;
 643 #endif
 644 };
 645
 646 /* The ARGBUF struct.  */
 647 struct argbuf {
 648   /* These are the baseclass definitions.  */
 649   IADDR addr;
 650   const IDESC *idesc;
 651   char trace_p;
 652   char profile_p;
 653   /* ??? Temporary hack for skip insns.  */
 654   char skip_count;
 655   char unused;
 656   /* cpu specific data follows */
 657   union sem semantic;
 658   int written;
 659   union sem_fields fields;
 660 };
 661
 662 /* A cached insn.
 663
 664    ??? SCACHE used to contain more than just argbuf.  We could delete the
 665    type entirely and always just use ARGBUF, but for future concerns and as
 666    a level of abstraction it is left in.  */
 667
 668 struct scache {
 669   struct argbuf argbuf;
 670 };
 671
 672 /* Macros to simplify extraction, reading and semantic code.
 673    These define and assign the local vars that contain the insn's fields.  */
 674
 675 #define EXTRACT_IFMT_EMPTY_VARS \
 676   unsigned int length;
 677 #define EXTRACT_IFMT_EMPTY_CODE \
 678   length = 0; \
 679
 680 #define EXTRACT_IFMT_MOVE_B_R_VARS \
 681   UINT f_operand2; \
 682   UINT f_mode; \
 683   UINT f_opcode; \
 684   UINT f_size; \
 685   UINT f_operand1; \
 686   unsigned int length;
 687 #define EXTRACT_IFMT_MOVE_B_R_CODE \
 688   length = 2; \
 689   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 690   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 691   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 692   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 693   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 694
 695 #define EXTRACT_IFMT_MOVEQ_VARS \
 696   UINT f_operand2; \
 697   UINT f_mode; \
 698   UINT f_opcode; \
 699   INT f_s6; \
 700   unsigned int length;
 701 #define EXTRACT_IFMT_MOVEQ_CODE \
 702   length = 2; \
 703   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 704   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 705   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 706   f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
 707
 708 #define EXTRACT_IFMT_MOVECBR_VARS \
 709   UINT f_operand2; \
 710   INT f_indir_pc__byte; \
 711   UINT f_mode; \
 712   UINT f_opcode; \
 713   UINT f_size; \
 714   UINT f_operand1; \
 715   /* Contents of trailing part of insn.  */ \
 716   UINT word_1; \
 717   unsigned int length;
 718 #define EXTRACT_IFMT_MOVECBR_CODE \
 719   length = 4; \
 720   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 721   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 722   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 723   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 724   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 725   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 726   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 727
 728 #define EXTRACT_IFMT_MOVECWR_VARS \
 729   UINT f_operand2; \
 730   INT f_indir_pc__word; \
 731   UINT f_mode; \
 732   UINT f_opcode; \
 733   UINT f_size; \
 734   UINT f_operand1; \
 735   /* Contents of trailing part of insn.  */ \
 736   UINT word_1; \
 737   unsigned int length;
 738 #define EXTRACT_IFMT_MOVECWR_CODE \
 739   length = 4; \
 740   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 741   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 742   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 743   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 744   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 745   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 746   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 747
 748 #define EXTRACT_IFMT_MOVECDR_VARS \
 749   INT f_indir_pc__dword; \
 750   UINT f_operand2; \
 751   UINT f_mode; \
 752   UINT f_opcode; \
 753   UINT f_size; \
 754   UINT f_operand1; \
 755   /* Contents of trailing part of insn.  */ \
 756   UINT word_1; \
 757   unsigned int length;
 758 #define EXTRACT_IFMT_MOVECDR_CODE \
 759   length = 6; \
 760   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 761   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 762   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 763   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 764   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 765   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 766   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 767
 768 #define EXTRACT_IFMT_MOVUCBR_VARS \
 769   UINT f_operand2; \
 770   INT f_indir_pc__byte; \
 771   UINT f_mode; \
 772   UINT f_opcode; \
 773   UINT f_size; \
 774   UINT f_operand1; \
 775   /* Contents of trailing part of insn.  */ \
 776   UINT word_1; \
 777   unsigned int length;
 778 #define EXTRACT_IFMT_MOVUCBR_CODE \
 779   length = 4; \
 780   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 781   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 782   f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 783   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 784   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 785   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 786   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 787
 788 #define EXTRACT_IFMT_MOVUCWR_VARS \
 789   UINT f_operand2; \
 790   INT f_indir_pc__word; \
 791   UINT f_mode; \
 792   UINT f_opcode; \
 793   UINT f_size; \
 794   UINT f_operand1; \
 795   /* Contents of trailing part of insn.  */ \
 796   UINT word_1; \
 797   unsigned int length;
 798 #define EXTRACT_IFMT_MOVUCWR_CODE \
 799   length = 4; \
 800   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 801   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 802   f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \
 803   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 804   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 805   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 806   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 807
 808 #define EXTRACT_IFMT_ADDQ_VARS \
 809   UINT f_operand2; \
 810   UINT f_mode; \
 811   UINT f_opcode; \
 812   UINT f_u6; \
 813   unsigned int length;
 814 #define EXTRACT_IFMT_ADDQ_CODE \
 815   length = 2; \
 816   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 817   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 818   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 819   f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
 820
 821 #define EXTRACT_IFMT_CMP_M_B_M_VARS \
 822   UINT f_operand2; \
 823   UINT f_membit; \
 824   UINT f_memmode; \
 825   UINT f_opcode; \
 826   UINT f_size; \
 827   UINT f_operand1; \
 828   unsigned int length;
 829 #define EXTRACT_IFMT_CMP_M_B_M_CODE \
 830   length = 2; \
 831   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 832   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 833   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 834   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 835   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 836   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 837
 838 #define EXTRACT_IFMT_MOVE_R_SPRV32_VARS \
 839   UINT f_operand2; \
 840   UINT f_mode; \
 841   UINT f_opcode; \
 842   UINT f_size; \
 843   UINT f_operand1; \
 844   unsigned int length;
 845 #define EXTRACT_IFMT_MOVE_R_SPRV32_CODE \
 846   length = 2; \
 847   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 848   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 849   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 850   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 851   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 852
 853 #define EXTRACT_IFMT_MOVE_SPR_RV32_VARS \
 854   UINT f_operand2; \
 855   UINT f_mode; \
 856   UINT f_opcode; \
 857   UINT f_size; \
 858   UINT f_operand1; \
 859   unsigned int length;
 860 #define EXTRACT_IFMT_MOVE_SPR_RV32_CODE \
 861   length = 2; \
 862   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 863   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 864   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 865   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 866   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 867
 868 #define EXTRACT_IFMT_MOVE_M_SPRV32_VARS \
 869   UINT f_operand2; \
 870   UINT f_membit; \
 871   UINT f_memmode; \
 872   UINT f_opcode; \
 873   UINT f_size; \
 874   UINT f_operand1; \
 875   unsigned int length;
 876 #define EXTRACT_IFMT_MOVE_M_SPRV32_CODE \
 877   length = 2; \
 878   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 879   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 880   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 881   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 882   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 883   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 884
 885 #define EXTRACT_IFMT_MOVE_C_SPRV32_P2_VARS \
 886   INT f_indir_pc__dword; \
 887   UINT f_operand2; \
 888   UINT f_mode; \
 889   UINT f_opcode; \
 890   UINT f_size; \
 891   UINT f_operand1; \
 892   /* Contents of trailing part of insn.  */ \
 893   UINT word_1; \
 894   unsigned int length;
 895 #define EXTRACT_IFMT_MOVE_C_SPRV32_P2_CODE \
 896   length = 6; \
 897   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 898   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
 899   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 900   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 901   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 902   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 903   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 904
 905 #define EXTRACT_IFMT_MOVE_SPR_MV32_VARS \
 906   UINT f_operand2; \
 907   UINT f_membit; \
 908   UINT f_memmode; \
 909   UINT f_opcode; \
 910   UINT f_size; \
 911   UINT f_operand1; \
 912   unsigned int length;
 913 #define EXTRACT_IFMT_MOVE_SPR_MV32_CODE \
 914   length = 2; \
 915   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 916   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 917   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
 918   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 919   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 920   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 921
 922 #define EXTRACT_IFMT_MOVE_SS_R_VARS \
 923   UINT f_operand2; \
 924   UINT f_mode; \
 925   UINT f_opcode; \
 926   UINT f_size; \
 927   UINT f_operand1; \
 928   unsigned int length;
 929 #define EXTRACT_IFMT_MOVE_SS_R_CODE \
 930   length = 2; \
 931   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 932   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 933   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 934   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 935   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 936
 937 #define EXTRACT_IFMT_MOVE_R_SS_VARS \
 938   UINT f_operand2; \
 939   UINT f_mode; \
 940   UINT f_opcode; \
 941   UINT f_size; \
 942   UINT f_operand1; \
 943   unsigned int length;
 944 #define EXTRACT_IFMT_MOVE_R_SS_CODE \
 945   length = 2; \
 946   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 947   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 948   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 949   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 950   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 951
 952 #define EXTRACT_IFMT_LAPC_D_VARS \
 953   SI f_indir_pc__dword_pcrel; \
 954   UINT f_operand2; \
 955   UINT f_mode; \
 956   UINT f_opcode; \
 957   UINT f_size; \
 958   UINT f_operand1; \
 959   /* Contents of trailing part of insn.  */ \
 960   UINT word_1; \
 961   unsigned int length;
 962 #define EXTRACT_IFMT_LAPC_D_CODE \
 963   length = 6; \
 964   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
 965   f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \
 966   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 967   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 968   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 969   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 970   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 971
 972 #define EXTRACT_IFMT_LAPCQ_VARS \
 973   UINT f_operand2; \
 974   UINT f_mode; \
 975   UINT f_opcode; \
 976   UINT f_size; \
 977   SI f_qo; \
 978   unsigned int length;
 979 #define EXTRACT_IFMT_LAPCQ_CODE \
 980   length = 2; \
 981   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 982   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
 983   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
 984   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
 985   f_qo = ((pc) + (((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)))); \
 986
 987 #define EXTRACT_IFMT_TEST_M_B_M_VARS \
 988   UINT f_operand2; \
 989   UINT f_membit; \
 990   UINT f_memmode; \
 991   UINT f_opcode; \
 992   UINT f_size; \
 993   UINT f_operand1; \
 994   unsigned int length;
 995 #define EXTRACT_IFMT_TEST_M_B_M_CODE \
 996   length = 2; \
 997   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
 998   f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
 999   f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
1000   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1001   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1002   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1003
1004 #define EXTRACT_IFMT_SWAP_VARS \
1005   UINT f_operand2; \
1006   UINT f_mode; \
1007   UINT f_opcode; \
1008   UINT f_size; \
1009   UINT f_operand1; \
1010   unsigned int length;
1011 #define EXTRACT_IFMT_SWAP_CODE \
1012   length = 2; \
1013   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1014   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1015   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1016   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1017   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1018
1019 #define EXTRACT_IFMT_ASRQ_VARS \
1020   UINT f_operand2; \
1021   UINT f_mode; \
1022   UINT f_opcode; \
1023   UINT f_b5; \
1024   UINT f_u5; \
1025   unsigned int length;
1026 #define EXTRACT_IFMT_ASRQ_CODE \
1027   length = 2; \
1028   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1029   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1030   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1031   f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
1032   f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
1033
1034 #define EXTRACT_IFMT_SETF_VARS \
1035   UINT f_mode; \
1036   UINT f_opcode; \
1037   UINT f_size; \
1038   UINT f_operand2; \
1039   UINT f_operand1; \
1040   UINT f_dstsrc; \
1041   unsigned int length;
1042 #define EXTRACT_IFMT_SETF_CODE \
1043   length = 2; \
1044   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1045   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1046   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1047   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1048   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1049   f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
1050
1051 #define EXTRACT_IFMT_RFE_VARS \
1052   UINT f_operand2; \
1053   UINT f_mode; \
1054   UINT f_opcode; \
1055   UINT f_size; \
1056   UINT f_operand1; \
1057   unsigned int length;
1058 #define EXTRACT_IFMT_RFE_CODE \
1059   length = 2; \
1060   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1061   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1062   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1063   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1064   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1065
1066 #define EXTRACT_IFMT_BCC_B_VARS \
1067   UINT f_operand2; \
1068   UINT f_mode; \
1069   UINT f_opcode_hi; \
1070   INT f_disp9_hi; \
1071   UINT f_disp9_lo; \
1072   INT f_disp9; \
1073   unsigned int length;
1074 #define EXTRACT_IFMT_BCC_B_CODE \
1075   length = 2; \
1076   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1077   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1078   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1079   f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
1080   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
1081 {\
1082   SI tmp_abslo;\
1083   SI tmp_absval;\
1084   tmp_abslo = ((f_disp9_lo) << (1));\
1085   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
1086   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\
1087 }\
1088
1089 #define EXTRACT_IFMT_BA_B_VARS \
1090   UINT f_operand2; \
1091   UINT f_mode; \
1092   UINT f_opcode_hi; \
1093   INT f_disp9_hi; \
1094   UINT f_disp9_lo; \
1095   INT f_disp9; \
1096   unsigned int length;
1097 #define EXTRACT_IFMT_BA_B_CODE \
1098   length = 2; \
1099   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1100   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1101   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1102   f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
1103   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
1104 {\
1105   SI tmp_abslo;\
1106   SI tmp_absval;\
1107   tmp_abslo = ((f_disp9_lo) << (1));\
1108   tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
1109   f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\
1110 }\
1111
1112 #define EXTRACT_IFMT_BCC_W_VARS \
1113   UINT f_operand2; \
1114   SI f_indir_pc__word_pcrel; \
1115   UINT f_mode; \
1116   UINT f_opcode; \
1117   UINT f_size; \
1118   UINT f_operand1; \
1119   /* Contents of trailing part of insn.  */ \
1120   UINT word_1; \
1121   unsigned int length;
1122 #define EXTRACT_IFMT_BCC_W_CODE \
1123   length = 4; \
1124   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1125   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1126   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
1127   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1128   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1129   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1130   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1131
1132 #define EXTRACT_IFMT_BA_W_VARS \
1133   UINT f_operand2; \
1134   SI f_indir_pc__word_pcrel; \
1135   UINT f_mode; \
1136   UINT f_opcode; \
1137   UINT f_size; \
1138   UINT f_operand1; \
1139   /* Contents of trailing part of insn.  */ \
1140   UINT word_1; \
1141   unsigned int length;
1142 #define EXTRACT_IFMT_BA_W_CODE \
1143   length = 4; \
1144   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1145   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1146   f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
1147   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1148   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1149   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1150   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1151
1152 #define EXTRACT_IFMT_JAS_C_VARS \
1153   INT f_indir_pc__dword; \
1154   UINT f_operand2; \
1155   UINT f_mode; \
1156   UINT f_opcode; \
1157   UINT f_size; \
1158   UINT f_operand1; \
1159   /* Contents of trailing part of insn.  */ \
1160   UINT word_1; \
1161   unsigned int length;
1162 #define EXTRACT_IFMT_JAS_C_CODE \
1163   length = 6; \
1164   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1165   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
1166   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1167   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1168   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1169   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1170   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1171
1172 #define EXTRACT_IFMT_JUMP_P_VARS \
1173   UINT f_operand2; \
1174   UINT f_mode; \
1175   UINT f_opcode; \
1176   UINT f_size; \
1177   UINT f_operand1; \
1178   unsigned int length;
1179 #define EXTRACT_IFMT_JUMP_P_CODE \
1180   length = 2; \
1181   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1182   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1183   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1184   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1185   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1186
1187 #define EXTRACT_IFMT_BAS_C_VARS \
1188   SI f_indir_pc__dword_pcrel; \
1189   UINT f_operand2; \
1190   UINT f_mode; \
1191   UINT f_opcode; \
1192   UINT f_size; \
1193   UINT f_operand1; \
1194   /* Contents of trailing part of insn.  */ \
1195   UINT word_1; \
1196   unsigned int length;
1197 #define EXTRACT_IFMT_BAS_C_CODE \
1198   length = 6; \
1199   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
1200   f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \
1201   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1202   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1203   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1204   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1205   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1206
1207 #define EXTRACT_IFMT_BREAK_VARS \
1208   UINT f_operand2; \
1209   UINT f_mode; \
1210   UINT f_opcode; \
1211   UINT f_size; \
1212   UINT f_u4; \
1213   unsigned int length;
1214 #define EXTRACT_IFMT_BREAK_CODE \
1215   length = 2; \
1216   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1217   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1218   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1219   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1220   f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1221
1222 #define EXTRACT_IFMT_SCC_VARS \
1223   UINT f_operand2; \
1224   UINT f_mode; \
1225   UINT f_opcode; \
1226   UINT f_size; \
1227   UINT f_operand1; \
1228   unsigned int length;
1229 #define EXTRACT_IFMT_SCC_CODE \
1230   length = 2; \
1231   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1232   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1233   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1234   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1235   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1236
1237 #define EXTRACT_IFMT_ADDOQ_VARS \
1238   UINT f_operand2; \
1239   UINT f_mode; \
1240   UINT f_opcode_hi; \
1241   INT f_s8; \
1242   unsigned int length;
1243 #define EXTRACT_IFMT_ADDOQ_CODE \
1244   length = 2; \
1245   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1246   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1247   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
1248   f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
1249
1250 #define EXTRACT_IFMT_FIDXI_VARS \
1251   UINT f_operand2; \
1252   UINT f_mode; \
1253   UINT f_opcode; \
1254   UINT f_size; \
1255   UINT f_operand1; \
1256   unsigned int length;
1257 #define EXTRACT_IFMT_FIDXI_CODE \
1258   length = 2; \
1259   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
1260   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
1261   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
1262   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
1263   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
1264
1265 /* Collection of various things for the trace handler to use.  */
1266
1267 typedef struct trace_record {
1268   IADDR pc;
1269   /* FIXME:wip */
1270 } TRACE_RECORD;
1271
1272 #endif /* CPU_CRISV32F_H */