gnu/dist/gdb6/sim/iq2000/cpu.h

   1 /* CPU family header for iq2000bf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_IQ2000BF_H
  26 #define CPU_IQ2000BF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 1
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() get_h_pc (current_cpu)
  42 #define SET_H_PC(x) \
  43 do { \
  44 set_h_pc (current_cpu, (x));\
  45 ;} while (0)
  46   /* General purpose registers */
  47   SI h_gr[32];
  48 #define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index]))
  49 #define SET_H_GR(index, x) \
  50 do { \
  51 if ((((index)) == (0))) {\
  52 ((void) 0); /*nop*/\
  53 }\
  54  else {\
  55 CPU (h_gr[(index)]) = (x);\
  56 }\
  57 ;} while (0)
  58   } hardware;
  59 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  60 } IQ2000BF_CPU_DATA;
  61
  62 /* Cover fns for register access.  */
  63 USI iq2000bf_h_pc_get (SIM_CPU *);
  64 void iq2000bf_h_pc_set (SIM_CPU *, USI);
  65 SI iq2000bf_h_gr_get (SIM_CPU *, UINT);
  66 void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI);
  67
  68 /* These must be hand-written.  */
  69 extern CPUREG_FETCH_FN iq2000bf_fetch_register;
  70 extern CPUREG_STORE_FN iq2000bf_store_register;
  71
  72 typedef struct {
  73   int empty;
  74 } MODEL_IQ2000_DATA;
  75
  76 /* Instruction argument buffer.  */
  77
  78 union sem_fields {
  79   struct { /* no operands */
  80     int empty;
  81   } fmt_empty;
  82   struct { /*  */
  83     IADDR i_jmptarg;
  84   } sfmt_j;
  85   struct { /*  */
  86     IADDR i_offset;
  87     UINT f_rs;
  88     UINT f_rt;
  89   } sfmt_bbi;
  90   struct { /*  */
  91     UINT f_imm;
  92     UINT f_rs;
  93     UINT f_rt;
  94   } sfmt_addi;
  95   struct { /*  */
  96     UINT f_mask;
  97     UINT f_rd;
  98     UINT f_rs;
  99     UINT f_rt;
 100   } sfmt_mrgb;
 101   struct { /*  */
 102     UINT f_maskl;
 103     UINT f_rd;
 104     UINT f_rs;
 105     UINT f_rt;
 106     UINT f_shamt;
 107   } sfmt_ram;
 108 #if WITH_SCACHE_PBB
 109   /* Writeback handler.  */
 110   struct {
 111     /* Pointer to argbuf entry for insn whose results need writing back.  */
 112     const struct argbuf *abuf;
 113   } write;
 114   /* x-before handler */
 115   struct {
 116     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 117     int first_p;
 118   } before;
 119   /* x-after handler */
 120   struct {
 121     int empty;
 122   } after;
 123   /* This entry is used to terminate each pbb.  */
 124   struct {
 125     /* Number of insns in pbb.  */
 126     int insn_count;
 127     /* Next pbb to execute.  */
 128     SCACHE *next;
 129     SCACHE *branch_target;
 130   } chain;
 131 #endif
 132 };
 133
 134 /* The ARGBUF struct.  */
 135 struct argbuf {
 136   /* These are the baseclass definitions.  */
 137   IADDR addr;
 138   const IDESC *idesc;
 139   char trace_p;
 140   char profile_p;
 141   /* ??? Temporary hack for skip insns.  */
 142   char skip_count;
 143   char unused;
 144   /* cpu specific data follows */
 145   union sem semantic;
 146   int written;
 147   union sem_fields fields;
 148 };
 149
 150 /* A cached insn.
 151
 152    ??? SCACHE used to contain more than just argbuf.  We could delete the
 153    type entirely and always just use ARGBUF, but for future concerns and as
 154    a level of abstraction it is left in.  */
 155
 156 struct scache {
 157   struct argbuf argbuf;
 158 };
 159
 160 /* Macros to simplify extraction, reading and semantic code.
 161    These define and assign the local vars that contain the insn's fields.  */
 162
 163 #define EXTRACT_IFMT_EMPTY_VARS \
 164   unsigned int length;
 165 #define EXTRACT_IFMT_EMPTY_CODE \
 166   length = 0; \
 167
 168 #define EXTRACT_IFMT_ADD_VARS \
 169   UINT f_opcode; \
 170   UINT f_rs; \
 171   UINT f_rt; \
 172   UINT f_rd; \
 173   UINT f_shamt; \
 174   UINT f_func; \
 175   unsigned int length;
 176 #define EXTRACT_IFMT_ADD_CODE \
 177   length = 4; \
 178   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 179   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 180   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 181   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 182   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 183   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 184
 185 #define EXTRACT_IFMT_ADDI_VARS \
 186   UINT f_opcode; \
 187   UINT f_rs; \
 188   UINT f_rt; \
 189   UINT f_imm; \
 190   unsigned int length;
 191 #define EXTRACT_IFMT_ADDI_CODE \
 192   length = 4; \
 193   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 194   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 195   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 196   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 197
 198 #define EXTRACT_IFMT_RAM_VARS \
 199   UINT f_opcode; \
 200   UINT f_rs; \
 201   UINT f_rt; \
 202   UINT f_rd; \
 203   UINT f_shamt; \
 204   UINT f_5; \
 205   UINT f_maskl; \
 206   unsigned int length;
 207 #define EXTRACT_IFMT_RAM_CODE \
 208   length = 4; \
 209   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 210   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 211   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 212   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 213   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 214   f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
 215   f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \
 216
 217 #define EXTRACT_IFMT_SLL_VARS \
 218   UINT f_opcode; \
 219   UINT f_rs; \
 220   UINT f_rt; \
 221   UINT f_rd; \
 222   UINT f_shamt; \
 223   UINT f_func; \
 224   unsigned int length;
 225 #define EXTRACT_IFMT_SLL_CODE \
 226   length = 4; \
 227   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 228   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 229   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 230   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 231   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 232   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 233
 234 #define EXTRACT_IFMT_SLMV_VARS \
 235   UINT f_opcode; \
 236   UINT f_rs; \
 237   UINT f_rt; \
 238   UINT f_rd; \
 239   UINT f_shamt; \
 240   UINT f_func; \
 241   unsigned int length;
 242 #define EXTRACT_IFMT_SLMV_CODE \
 243   length = 4; \
 244   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 245   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 246   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 247   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 248   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 249   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 250
 251 #define EXTRACT_IFMT_SLTI_VARS \
 252   UINT f_opcode; \
 253   UINT f_rs; \
 254   UINT f_rt; \
 255   UINT f_imm; \
 256   unsigned int length;
 257 #define EXTRACT_IFMT_SLTI_CODE \
 258   length = 4; \
 259   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 260   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 261   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 262   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 263
 264 #define EXTRACT_IFMT_BBI_VARS \
 265   UINT f_opcode; \
 266   UINT f_rs; \
 267   UINT f_rt; \
 268   SI f_offset; \
 269   unsigned int length;
 270 #define EXTRACT_IFMT_BBI_CODE \
 271   length = 4; \
 272   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 273   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 274   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 275   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 276
 277 #define EXTRACT_IFMT_BBV_VARS \
 278   UINT f_opcode; \
 279   UINT f_rs; \
 280   UINT f_rt; \
 281   SI f_offset; \
 282   unsigned int length;
 283 #define EXTRACT_IFMT_BBV_CODE \
 284   length = 4; \
 285   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 286   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 287   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 288   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 289
 290 #define EXTRACT_IFMT_BGEZ_VARS \
 291   UINT f_opcode; \
 292   UINT f_rs; \
 293   UINT f_rt; \
 294   SI f_offset; \
 295   unsigned int length;
 296 #define EXTRACT_IFMT_BGEZ_CODE \
 297   length = 4; \
 298   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 299   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 300   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 301   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 302
 303 #define EXTRACT_IFMT_JALR_VARS \
 304   UINT f_opcode; \
 305   UINT f_rs; \
 306   UINT f_rt; \
 307   UINT f_rd; \
 308   UINT f_shamt; \
 309   UINT f_func; \
 310   unsigned int length;
 311 #define EXTRACT_IFMT_JALR_CODE \
 312   length = 4; \
 313   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 314   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 315   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 316   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 317   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 318   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 319
 320 #define EXTRACT_IFMT_JR_VARS \
 321   UINT f_opcode; \
 322   UINT f_rs; \
 323   UINT f_rt; \
 324   UINT f_rd; \
 325   UINT f_shamt; \
 326   UINT f_func; \
 327   unsigned int length;
 328 #define EXTRACT_IFMT_JR_CODE \
 329   length = 4; \
 330   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 331   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 332   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 333   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 334   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 335   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 336
 337 #define EXTRACT_IFMT_LB_VARS \
 338   UINT f_opcode; \
 339   UINT f_rs; \
 340   UINT f_rt; \
 341   UINT f_imm; \
 342   unsigned int length;
 343 #define EXTRACT_IFMT_LB_CODE \
 344   length = 4; \
 345   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 346   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 347   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 348   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 349
 350 #define EXTRACT_IFMT_LUI_VARS \
 351   UINT f_opcode; \
 352   UINT f_rs; \
 353   UINT f_rt; \
 354   UINT f_imm; \
 355   unsigned int length;
 356 #define EXTRACT_IFMT_LUI_CODE \
 357   length = 4; \
 358   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 359   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 360   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 361   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 362
 363 #define EXTRACT_IFMT_BREAK_VARS \
 364   UINT f_opcode; \
 365   UINT f_rs; \
 366   UINT f_rt; \
 367   UINT f_rd; \
 368   UINT f_shamt; \
 369   UINT f_func; \
 370   unsigned int length;
 371 #define EXTRACT_IFMT_BREAK_CODE \
 372   length = 4; \
 373   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 374   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 375   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 376   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 377   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 378   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 379
 380 #define EXTRACT_IFMT_SYSCALL_VARS \
 381   UINT f_opcode; \
 382   UINT f_excode; \
 383   UINT f_func; \
 384   unsigned int length;
 385 #define EXTRACT_IFMT_SYSCALL_CODE \
 386   length = 4; \
 387   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 388   f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \
 389   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 390
 391 #define EXTRACT_IFMT_ANDOUI_VARS \
 392   UINT f_opcode; \
 393   UINT f_rs; \
 394   UINT f_rt; \
 395   UINT f_imm; \
 396   unsigned int length;
 397 #define EXTRACT_IFMT_ANDOUI_CODE \
 398   length = 4; \
 399   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 400   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 401   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 402   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 403
 404 #define EXTRACT_IFMT_MRGB_VARS \
 405   UINT f_opcode; \
 406   UINT f_rs; \
 407   UINT f_rt; \
 408   UINT f_rd; \
 409   UINT f_10; \
 410   UINT f_mask; \
 411   UINT f_func; \
 412   unsigned int length;
 413 #define EXTRACT_IFMT_MRGB_CODE \
 414   length = 4; \
 415   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 416   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 417   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 418   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 419   f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
 420   f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
 421   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 422
 423 #define EXTRACT_IFMT_BC0F_VARS \
 424   UINT f_opcode; \
 425   UINT f_rs; \
 426   UINT f_rt; \
 427   SI f_offset; \
 428   unsigned int length;
 429 #define EXTRACT_IFMT_BC0F_CODE \
 430   length = 4; \
 431   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 432   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 433   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 434   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 435
 436 #define EXTRACT_IFMT_CFC0_VARS \
 437   UINT f_opcode; \
 438   UINT f_rs; \
 439   UINT f_rt; \
 440   UINT f_rd; \
 441   UINT f_10_11; \
 442   unsigned int length;
 443 #define EXTRACT_IFMT_CFC0_CODE \
 444   length = 4; \
 445   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 446   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 447   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 448   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 449   f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 450
 451 #define EXTRACT_IFMT_CHKHDR_VARS \
 452   UINT f_opcode; \
 453   UINT f_rs; \
 454   UINT f_rt; \
 455   UINT f_rd; \
 456   UINT f_shamt; \
 457   UINT f_func; \
 458   unsigned int length;
 459 #define EXTRACT_IFMT_CHKHDR_CODE \
 460   length = 4; \
 461   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 462   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 463   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 464   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 465   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 466   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 467
 468 #define EXTRACT_IFMT_LULCK_VARS \
 469   UINT f_opcode; \
 470   UINT f_rs; \
 471   UINT f_rt; \
 472   UINT f_rd; \
 473   UINT f_shamt; \
 474   UINT f_func; \
 475   unsigned int length;
 476 #define EXTRACT_IFMT_LULCK_CODE \
 477   length = 4; \
 478   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 479   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 480   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 481   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 482   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 483   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 484
 485 #define EXTRACT_IFMT_PKRLR1_VARS \
 486   UINT f_opcode; \
 487   UINT f_rs; \
 488   UINT f_rt; \
 489   UINT f_count; \
 490   UINT f_index; \
 491   unsigned int length;
 492 #define EXTRACT_IFMT_PKRLR1_CODE \
 493   length = 4; \
 494   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 495   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 496   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 497   f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \
 498   f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \
 499
 500 #define EXTRACT_IFMT_RFE_VARS \
 501   UINT f_opcode; \
 502   UINT f_25; \
 503   UINT f_24_19; \
 504   UINT f_func; \
 505   unsigned int length;
 506 #define EXTRACT_IFMT_RFE_CODE \
 507   length = 4; \
 508   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 509   f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
 510   f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \
 511   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 512
 513 #define EXTRACT_IFMT_J_VARS \
 514   UINT f_opcode; \
 515   UINT f_rsrvd; \
 516   USI f_jtarg; \
 517   unsigned int length;
 518 #define EXTRACT_IFMT_J_CODE \
 519   length = 4; \
 520   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 521   f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \
 522   f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \
 523
 524 /* Collection of various things for the trace handler to use.  */
 525
 526 typedef struct trace_record {
 527   IADDR pc;
 528   /* FIXME:wip */
 529 } TRACE_RECORD;
 530
 531 #endif /* CPU_IQ2000BF_H */