gnu/dist/gdb6/sim/ppc/registers.h

   1 /*  This file is part of the program psim.
   2
   3     Copyright 1994, 1997, 2003 Andrew Cagney
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18
  19     */
  20
  21
  22 #ifndef _REGISTERS_H_
  23 #define _REGISTERS_H_
  24
  25
  26 /*
  27  * The PowerPC registers
  28  *
  29  */
  30
  31 /* FIXME:
  32
  33    For the moment use macro's to determine if the E500 or Altivec
  34    registers should be included.  IGEN should instead of a :register:
  35    field to facilitate the specification and generation of per ISA
  36    registers.  */
  37
  38 #ifdef WITH_E500
  39 #include "e500_registers.h"
  40 #endif
  41 #if WITH_ALTIVEC
  42 #include "altivec_registers.h"
  43 #endif
  44
  45 /**
  46  ** General Purpose Registers
  47  **/
  48
  49 typedef signed_word gpreg;
  50
  51
  52
  53 /**
  54  ** Floating Point Registers
  55  **/
  56
  57 typedef unsigned64 fpreg;
  58
  59
  60
  61 /**
  62  ** The condition register
  63  **
  64  **/
  65
  66 typedef unsigned32 creg;
  67
  68 /* The following sub bits are defined for the condition register */
  69 enum {
  70   cr_i_negative = BIT4(0),
  71   cr_i_positive = BIT4(1),
  72   cr_i_zero = BIT4(2),
  73   cr_i_summary_overflow = BIT4(3),
  74 #if 0
  75   /* cr0 - integer status */
  76   cr0_i_summary_overflow_bit = 3,
  77   cr0_i_negative = BIT32(0),
  78   cr0_i_positive = BIT32(1),
  79   cr0_i_zero = BIT32(2),
  80   cr0_i_summary_overflow = BIT32(3),
  81   cr0_i_mask = MASK32(0,3),
  82 #endif
  83   /* cr1 - floating-point status */
  84   cr1_i_floating_point_exception_summary_bit = 4,
  85   cr1_i_floating_point_enabled_exception_summary_bit = 5,
  86   cr1_i_floating_point_invalid_operation_exception_summary_bit = 6,
  87   cr1_i_floating_point_overflow_exception_bit = 7,
  88   cr1_i_floating_point_exception_summary = BIT32(4),
  89   cr1_i_floating_point_enabled_exception_summary = BIT32(5),
  90   cr1_i_floating_point_invalid_operation_exception_summary = BIT32(6),
  91   cr1_i_floating_point_overflow_exception = BIT32(7),
  92   cr1_i_mask = MASK32(4,7),
  93 };
  94
  95
  96 /* Condition register 1 contains the result of floating point arithmetic */
  97 enum {
  98   cr_fp_exception = BIT4(0),
  99   cr_fp_enabled_exception = BIT4(1),
 100   cr_fp_invalid_exception = BIT4(2),
 101   cr_fp_overflow_exception = BIT4(3),
 102 };
 103
 104
 105
 106 /**
 107  ** Floating-Point Status and Control Register
 108  **/
 109
 110 typedef unsigned32 fpscreg;
 111 enum {
 112   fpscr_fx_bit = 0,
 113   fpscr_fx = BIT32(0),
 114   fpscr_fex_bit = 1,
 115   fpscr_fex = BIT32(1),
 116   fpscr_vx_bit = 2,
 117   fpscr_vx = BIT32(2),
 118   fpscr_ox_bit = 3,
 119   fpscr_ox = BIT32(3),
 120   fpscr_ux = BIT32(4),
 121   fpscr_zx = BIT32(5),
 122   fpscr_xx = BIT32(6),
 123   fpscr_vxsnan = BIT32(7), /* SNAN */
 124   fpscr_vxisi = BIT32(8), /* INF - INF */
 125   fpscr_vxidi = BIT32(9), /* INF / INF */
 126   fpscr_vxzdz = BIT32(10), /* 0 / 0 */
 127   fpscr_vximz = BIT32(11), /* INF * 0 */
 128   fpscr_vxvc = BIT32(12),
 129   fpscr_fr = BIT32(13),
 130   fpscr_fi = BIT32(14),
 131   fpscr_fprf = MASK32(15, 19),
 132   fpscr_c = BIT32(15),
 133   fpscr_fpcc_bit = 16, /* well sort of */
 134   fpscr_fpcc = MASK32(16, 19),
 135   fpscr_fl = BIT32(16),
 136   fpscr_fg = BIT32(17),
 137   fpscr_fe = BIT32(18),
 138   fpscr_fu = BIT32(19),
 139   fpscr_rf_quiet_nan = fpscr_c | fpscr_fu,
 140   fpscr_rf_neg_infinity = fpscr_fl | fpscr_fu,
 141   fpscr_rf_neg_normal_number = fpscr_fl,
 142   fpscr_rf_neg_denormalized_number = fpscr_c | fpscr_fl,
 143   fpscr_rf_neg_zero = fpscr_c | fpscr_fe,
 144   fpscr_rf_pos_zero = fpscr_fe,
 145   fpscr_rf_pos_denormalized_number = fpscr_c | fpscr_fg,
 146   fpscr_rf_pos_normal_number = fpscr_fg,
 147   fpscr_rf_pos_infinity = fpscr_fg | fpscr_fu,
 148   fpscr_reserved_20 = BIT32(20),
 149   fpscr_vxsoft = BIT32(21),
 150   fpscr_vxsqrt = BIT32(22),
 151   fpscr_vxcvi = BIT32(23),
 152   fpscr_ve = BIT32(24),
 153   fpscr_oe = BIT32(25),
 154   fpscr_ue = BIT32(26),
 155   fpscr_ze = BIT32(27),
 156   fpscr_xe = BIT32(28),
 157   fpscr_ni = BIT32(29),
 158   fpscr_rn = MASK32(30, 31),
 159   fpscr_rn_round_to_nearest = 0,
 160   fpscr_rn_round_towards_zero = MASK32(31,31),
 161   fpscr_rn_round_towards_pos_infinity = MASK32(30,30),
 162   fpscr_rn_round_towards_neg_infinity = MASK32(30,31),
 163   fpscr_vx_bits = (fpscr_vxsnan | fpscr_vxisi | fpscr_vxidi
 164                    | fpscr_vxzdz | fpscr_vximz | fpscr_vxvc
 165                    | fpscr_vxsoft | fpscr_vxsqrt | fpscr_vxcvi),
 166 };
 167
 168
 169
 170 /**
 171  ** XER Register
 172  **/
 173
 174 typedef unsigned32 xereg;
 175
 176 enum {
 177   xer_summary_overflow = BIT32(0), xer_summary_overflow_bit = 0,
 178   xer_carry = BIT32(2), xer_carry_bit = 2,
 179   xer_overflow = BIT32(1),
 180   xer_reserved_3_24 = MASK32(3,24),
 181   xer_byte_count_mask = MASK32(25,31)
 182 };
 183
 184
 185 /**
 186  ** SPR's
 187  **/
 188
 189 #include "spreg.h"
 190
 191
 192 /**
 193  ** Segment Registers
 194  **/
 195
 196 typedef unsigned32 sreg;
 197 enum {
 198   nr_of_srs = 16
 199 };
 200
 201
 202 /**
 203  ** Machine state register
 204  **/
 205 typedef unsigned_word msreg; /* 32 or 64 bits */
 206
 207 enum {
 208 #if (WITH_TARGET_WORD_BITSIZE == 64)
 209   msr_64bit_mode = BIT(0),
 210 #endif
 211 #if (WITH_TARGET_WORD_BITSIZE == 32)
 212   msr_64bit_mode = 0,
 213 #endif
 214   msr_power_management_enable = BIT(45),
 215   msr_tempoary_gpr_remapping = BIT(46), /* 603 specific */
 216   msr_interrupt_little_endian_mode = BIT(47),
 217   msr_external_interrupt_enable = BIT(48),
 218   msr_problem_state = BIT(49),
 219   msr_floating_point_available = BIT(50),
 220   msr_machine_check_enable = BIT(51),
 221   msr_floating_point_exception_mode_0 = BIT(52),
 222   msr_single_step_trace_enable = BIT(53),
 223   msr_branch_trace_enable = BIT(54),
 224   msr_floating_point_exception_mode_1 = BIT(55),
 225   msr_interrupt_prefix = BIT(57),
 226   msr_instruction_relocate = BIT(58),
 227   msr_data_relocate = BIT(59),
 228   msr_recoverable_interrupt = BIT(62),
 229   msr_little_endian_mode = BIT(63)
 230 };
 231
 232 enum {
 233   srr1_hash_table_or_ibat_miss = BIT(33),
 234   srr1_direct_store_error_exception = BIT(35),
 235   srr1_protection_violation = BIT(36),
 236   srr1_segment_table_miss = BIT(42),
 237   srr1_floating_point_enabled = BIT(43),
 238   srr1_illegal_instruction = BIT(44),
 239   srr1_priviliged_instruction = BIT(45),
 240   srr1_trap = BIT(46),
 241   srr1_subsequent_instruction = BIT(47)
 242 };
 243
 244 /**
 245  ** storage interrupt registers
 246  **/
 247
 248 typedef enum {
 249   dsisr_direct_store_error_exception = BIT32(0),
 250   dsisr_hash_table_or_dbat_miss = BIT32(1),
 251   dsisr_protection_violation = BIT32(4),
 252   dsisr_earwax_violation = BIT32(5),
 253   dsisr_store_operation = BIT32(6),
 254   dsisr_segment_table_miss = BIT32(10),
 255   dsisr_earwax_disabled = BIT32(11)
 256 } dsisr_status;
 257
 258
 259
 260 /**
 261  ** And the registers proper
 262  **/
 263 typedef struct _registers {
 264
 265   gpreg gpr[32];
 266   fpreg fpr[32];
 267   creg cr;
 268   fpscreg fpscr;
 269
 270   /* Machine state register */
 271   msreg msr;
 272
 273   /* Spr's */
 274   spreg spr[nr_of_sprs];
 275
 276   /* Segment Registers */
 277   sreg sr[nr_of_srs];
 278
 279 #if WITH_ALTIVEC
 280   struct altivec_regs altivec;
 281 #endif
 282 #if WITH_E500
 283   struct e500_regs e500;
 284 #endif
 285
 286 } registers;
 287
 288 /* dump out all the registers */
 289
 290 INLINE_REGISTERS\
 291 (void) registers_dump
 292 (registers *regs);
 293
 294
 295 /* return information on a register based on name */
 296
 297 typedef enum {
 298   reg_invalid,
 299   reg_gpr, reg_fpr, reg_spr, reg_msr,
 300   reg_cr, reg_fpscr, reg_pc, reg_sr,
 301   reg_insns, reg_stalls, reg_cycles,
 302 #ifdef WITH_ALTIVEC
 303   reg_vr, reg_vscr,
 304 #endif
 305 #ifdef WITH_E500
 306   reg_acc, reg_gprh, reg_evr,
 307 #endif
 308   nr_register_types
 309 } register_types;
 310
 311 typedef struct {
 312   register_types type;
 313   int index;
 314   int size;
 315 } register_descriptions;
 316
 317 INLINE_REGISTERS\
 318 (register_descriptions) register_description
 319 (const char reg[]);
 320
 321
 322 /* Special purpose registers by their more common names */
 323
 324 #define SPREG(N)        cpu_registers(processor)->spr[N]
 325 #define XER             SPREG(spr_xer)
 326 #define LR              SPREG(spr_lr)
 327 #define CTR             SPREG(spr_ctr)
 328 #define SRR0            SPREG(spr_srr0)
 329 #define SRR1            SPREG(spr_srr1)
 330 #define DAR             SPREG(spr_dar)
 331 #define DSISR           SPREG(spr_dsisr)
 332
 333 /* general purpose registers - indexed access */
 334 #define GPR(N)          cpu_registers(processor)->gpr[N]
 335
 336 /* segment registers */
 337 #define SEGREG(N)       cpu_registers(processor)->sr[N]
 338
 339 /* condition register */
 340 #define CR              cpu_registers(processor)->cr
 341
 342 /* machine status register */
 343 #define MSR             cpu_registers(processor)->msr
 344
 345 /* floating-point status condition register */
 346 #define FPSCR           cpu_registers(processor)->fpscr
 347
 348 #endif /* _REGISTERS_H_ */