gnu/dist/gdb6/sim/sh/interp.c

   1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
   2
   3    Written by Steve Chamberlain of Cygnus Support.
   4    sac@cygnus.com
   5
   6    This file is part of SH sim
   7
   8
   9                 THIS SOFTWARE IS NOT COPYRIGHTED
  10
  11    Cygnus offers the following for use in the public domain.  Cygnus
  12    makes no warranty with regard to the software or it's performance
  13    and the user accepts the software "AS IS" with all faults.
  14
  15    CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
  16    THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  18
  19 */
  20
  21 #include "config.h"
  22
  23 #include <signal.h>
  24 #ifdef HAVE_UNISTD_H
  25 #include <unistd.h>
  26 #endif
  27 #ifdef HAVE_MMAP
  28 #include <sys/mman.h>
  29 # ifndef MAP_FAILED
  30 #  define MAP_FAILED -1
  31 # endif
  32 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON)
  33 #  define MAP_ANONYMOUS MAP_ANON
  34 # endif
  35 #endif
  36
  37 #include "sysdep.h"
  38 #include "bfd.h"
  39 #include "gdb/callback.h"
  40 #include "gdb/remote-sim.h"
  41 #include "gdb/sim-sh.h"
  42
  43 /* This file is local - if newlib changes, then so should this.  */
  44 #include "syscall.h"
  45
  46 #include <math.h>
  47
  48 #ifdef _WIN32
  49 #include <float.h>              /* Needed for _isnan() */
  50 #define isnan _isnan
  51 #endif
  52
  53 #ifndef SIGBUS
  54 #define SIGBUS SIGSEGV
  55 #endif
  56
  57 #ifndef SIGQUIT
  58 #define SIGQUIT SIGTERM
  59 #endif
  60
  61 #ifndef SIGTRAP
  62 #define SIGTRAP 5
  63 #endif
  64
  65 extern unsigned short sh_jump_table[], sh_dsp_table[0x1000], ppi_table[];
  66
  67 int sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size);
  68
  69 #define O_RECOMPILE 85
  70 #define DEFINE_TABLE
  71 #define DISASSEMBLER_TABLE
  72
  73 /* Define the rate at which the simulator should poll the host
  74    for a quit. */
  75 #define POLL_QUIT_INTERVAL 0x60000
  76
  77 typedef struct
  78 {
  79   int regs[20];
  80 } regstacktype;
  81
  82 typedef union
  83 {
  84
  85   struct
  86   {
  87     int regs[16];
  88     int pc;
  89
  90     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
  91        which are located in fregs, i.e. strictly speaking, these are
  92        out-of-bounds accesses of sregs.i .  This wart of the code could be
  93        fixed by making fregs part of sregs, and including pc too - to avoid
  94        alignment repercussions - but this would cause very onerous union /
  95        structure nesting, which would only be managable with anonymous
  96        unions and structs.  */
  97     union
  98       {
  99         struct
 100           {
 101             int mach;
 102             int macl;
 103             int pr;
 104             int dummy3, dummy4;
 105             int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
 106             int fpscr; /* dsr for sh-dsp */
 107           } named;
 108         int i[7];
 109       } sregs;
 110
 111     /* sh3e / sh-dsp */
 112     union fregs_u
 113       {
 114         float f[16];
 115         double d[8];
 116         int i[16];
 117       }
 118     fregs[2];
 119
 120     /* Control registers; on the SH4, ldc / stc is privileged, except when
 121        accessing gbr.  */
 122     union
 123       {
 124         struct
 125           {
 126             int sr;
 127             int gbr;
 128             int vbr;
 129             int ssr;
 130             int spc;
 131             int mod;
 132             /* sh-dsp */
 133             int rs;
 134             int re;
 135             /* sh3 */
 136             int bank[8];
 137             int dbr;            /* debug base register */
 138             int sgr;            /* saved gr15 */
 139             int ldst;           /* load/store flag (boolean) */
 140             int tbr;
 141             int ibcr;           /* sh2a bank control register */
 142             int ibnr;           /* sh2a bank number register */
 143           } named;
 144         int i[16];
 145       } cregs;
 146
 147     unsigned char *insn_end;
 148
 149     int ticks;
 150     int stalls;
 151     int memstalls;
 152     int cycles;
 153     int insts;
 154
 155     int prevlock;
 156     int thislock;
 157     int exception;
 158
 159     int end_of_registers;
 160
 161     int msize;
 162 #define PROFILE_FREQ 1
 163 #define PROFILE_SHIFT 2
 164     int profile;
 165     unsigned short *profile_hist;
 166     unsigned char *memory;
 167     int xyram_select, xram_start, yram_start;
 168     unsigned char *xmem;
 169     unsigned char *ymem;
 170     unsigned char *xmem_offset;
 171     unsigned char *ymem_offset;
 172     unsigned long bfd_mach;
 173     regstacktype *regstack;
 174   }
 175   asregs;
 176   int asints[40];
 177 } saved_state_type;
 178
 179 saved_state_type saved_state;
 180
 181 struct loop_bounds { unsigned char *start, *end; };
 182
 183 /* These variables are at file scope so that functions other than
 184    sim_resume can use the fetch/store macros */
 185
 186 static int target_little_endian;
 187 static int global_endianw, endianb;
 188 static int target_dsp;
 189 static int host_little_endian;
 190 static char **prog_argv;
 191
 192 static int maskw = 0;
 193 static int maskl = 0;
 194
 195 static SIM_OPEN_KIND sim_kind;
 196 static char *myname;
 197 static int   tracing = 0;
 198
 199
 200 /* Short hand definitions of the registers */
 201
 202 #define SBIT(x) ((x)&sbit)
 203 #define R0      saved_state.asregs.regs[0]
 204 #define Rn      saved_state.asregs.regs[n]
 205 #define Rm      saved_state.asregs.regs[m]
 206 #define UR0     (unsigned int) (saved_state.asregs.regs[0])
 207 #define UR      (unsigned int) R
 208 #define UR      (unsigned int) R
 209 #define SR0     saved_state.asregs.regs[0]
 210 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
 211 #define GBR     saved_state.asregs.cregs.named.gbr
 212 #define VBR     saved_state.asregs.cregs.named.vbr
 213 #define DBR     saved_state.asregs.cregs.named.dbr
 214 #define TBR     saved_state.asregs.cregs.named.tbr
 215 #define IBCR    saved_state.asregs.cregs.named.ibcr
 216 #define IBNR    saved_state.asregs.cregs.named.ibnr
 217 #define BANKN   (saved_state.asregs.cregs.named.ibnr & 0x1ff)
 218 #define ME      ((saved_state.asregs.cregs.named.ibnr >> 14) & 0x3)
 219 #define SSR     saved_state.asregs.cregs.named.ssr
 220 #define SPC     saved_state.asregs.cregs.named.spc
 221 #define SGR     saved_state.asregs.cregs.named.sgr
 222 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
 223 #define MACH    saved_state.asregs.sregs.named.mach
 224 #define MACL    saved_state.asregs.sregs.named.macl
 225 #define PR      saved_state.asregs.sregs.named.pr
 226 #define FPUL    saved_state.asregs.sregs.named.fpul
 227
 228 #define PC insn_ptr
 229
 230
 231
 232 /* Alternate bank of registers r0-r7 */
 233
 234 /* Note: code controling SR handles flips between BANK0 and BANK1 */
 235 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
 236 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
 237
 238
 239 /* Manipulate SR */
 240
 241 #define SR_MASK_BO  (1 << 14)
 242 #define SR_MASK_CS  (1 << 13)
 243 #define SR_MASK_DMY (1 << 11)
 244 #define SR_MASK_DMX (1 << 10)
 245 #define SR_MASK_M (1 << 9)
 246 #define SR_MASK_Q (1 << 8)
 247 #define SR_MASK_I (0xf << 4)
 248 #define SR_MASK_S (1 << 1)
 249 #define SR_MASK_T (1 << 0)
 250
 251 #define SR_MASK_BL (1 << 28)
 252 #define SR_MASK_RB (1 << 29)
 253 #define SR_MASK_MD (1 << 30)
 254 #define SR_MASK_RC 0x0fff0000
 255 #define SR_RC_INCREMENT -0x00010000
 256
 257 #define BO      ((saved_state.asregs.cregs.named.sr & SR_MASK_BO) != 0)
 258 #define CS      ((saved_state.asregs.cregs.named.sr & SR_MASK_CS) != 0)
 259 #define M       ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
 260 #define Q       ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
 261 #define S       ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
 262 #define T       ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
 263 #define LDST    ((saved_state.asregs.cregs.named.ldst) != 0)
 264
 265 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
 266 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
 267 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
 268 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
 269 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
 270 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
 271
 272 /* Note: don't use this for privileged bits */
 273 #define SET_SR_BIT(EXP, BIT) \
 274 do { \
 275   if ((EXP) & 1) \
 276     saved_state.asregs.cregs.named.sr |= (BIT); \
 277   else \
 278     saved_state.asregs.cregs.named.sr &= ~(BIT); \
 279 } while (0)
 280
 281 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO)
 282 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS)
 283 #define SET_BANKN(EXP) \
 284 do { \
 285   IBNR = (IBNR & 0xfe00) | (EXP & 0x1f); \
 286 } while (0)
 287 #define SET_ME(EXP) \
 288 do { \
 289   IBNR = (IBNR & 0x3fff) | ((EXP & 0x3) << 14); \
 290 } while (0)
 291 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
 292 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
 293 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
 294 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
 295 #define SET_LDST(EXP) (saved_state.asregs.cregs.named.ldst = ((EXP) != 0))
 296
 297 /* stc currently relies on being able to read SR without modifications.  */
 298 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
 299
 300 #define SET_SR(x) set_sr (x)
 301
 302 #define SET_RC(x) \
 303   (saved_state.asregs.cregs.named.sr \
 304    = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
 305
 306 /* Manipulate FPSCR */
 307
 308 #define FPSCR_MASK_FR (1 << 21)
 309 #define FPSCR_MASK_SZ (1 << 20)
 310 #define FPSCR_MASK_PR (1 << 19)
 311
 312 #define FPSCR_FR  ((GET_FPSCR () & FPSCR_MASK_FR) != 0)
 313 #define FPSCR_SZ  ((GET_FPSCR () & FPSCR_MASK_SZ) != 0)
 314 #define FPSCR_PR  ((GET_FPSCR () & FPSCR_MASK_PR) != 0)
 315
 316 /* Count the number of arguments in an argv.  */
 317 static int
 318 count_argc (char **argv)
 319 {
 320   int i;
 321
 322   if (! argv)
 323     return -1;
 324
 325   for (i = 0; argv[i] != NULL; ++i)
 326     continue;
 327   return i;
 328 }
 329
 330 static void
 331 set_fpscr1 (x)
 332         int x;
 333 {
 334   int old = saved_state.asregs.sregs.named.fpscr;
 335   saved_state.asregs.sregs.named.fpscr = (x);
 336   /* swap the floating point register banks */
 337   if ((saved_state.asregs.sregs.named.fpscr ^ old) & FPSCR_MASK_FR
 338       /* Ignore bit change if simulating sh-dsp.  */
 339       && ! target_dsp)
 340     {
 341       union fregs_u tmpf = saved_state.asregs.fregs[0];
 342       saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1];
 343       saved_state.asregs.fregs[1] = tmpf;
 344     }
 345 }
 346
 347 /* sts relies on being able to read fpscr directly.  */
 348 #define GET_FPSCR()  (saved_state.asregs.sregs.named.fpscr)
 349 #define SET_FPSCR(x) \
 350 do { \
 351   set_fpscr1 (x); \
 352 } while (0)
 353
 354 #define DSR  (saved_state.asregs.sregs.named.fpscr)
 355
 356 int
 357 fail ()
 358 {
 359   abort ();
 360 }
 361
 362 #define RAISE_EXCEPTION(x) \
 363   (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
 364
 365 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \
 366   if (in_delay_slot) RAISE_EXCEPTION (SIGILL)
 367
 368 /* This function exists mainly for the purpose of setting a breakpoint to
 369    catch simulated bus errors when running the simulator under GDB.  */
 370
 371 void
 372 raise_exception (x)
 373      int x;
 374 {
 375   RAISE_EXCEPTION (x);
 376 }
 377
 378 void
 379 raise_buserror ()
 380 {
 381   raise_exception (SIGBUS);
 382 }
 383
 384 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
 385                                 forbidden_addr_bits, data, retval) \
 386 do { \
 387   if (addr & forbidden_addr_bits) \
 388     { \
 389       raise_buserror (); \
 390       return retval; \
 391     } \
 392   else if ((addr & saved_state.asregs.xyram_select) \
 393            == saved_state.asregs.xram_start) \
 394     ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
 395   else if ((addr & saved_state.asregs.xyram_select) \
 396            == saved_state.asregs.yram_start) \
 397     ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
 398   else if ((unsigned) addr >> 24 == 0xf0 \
 399            && bits_written == 32 && (data & 1) == 0) \
 400     /* This invalidates (if not associative) or might invalidate \
 401        (if associative) an instruction cache line.  This is used for \
 402        trampolines.  Since we don't simulate the cache, this is a no-op \
 403        as far as the simulator is concerned.  */ \
 404     return retval; \
 405   else \
 406     { \
 407       if (bits_written == 8 && addr > 0x5000000) \
 408         IOMEM (addr, 1, data); \
 409       /* We can't do anything useful with the other stuff, so fail.  */ \
 410       raise_buserror (); \
 411       return retval; \
 412     } \
 413 } while (0)
 414
 415 /* FIXME: sim_resume should be renamed to sim_engine_run.  sim_resume
 416    being implemented by ../common/sim_resume.c and the below should
 417    make a call to sim_engine_halt */
 418
 419 #define BUSERROR(addr, mask) ((addr) & (mask))
 420
 421 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
 422   do \
 423     { \
 424       if (addr & mask) \
 425         { \
 426           addr_func (addr, data); \
 427           return; \
 428         } \
 429     } \
 430   while (0)
 431
 432 #define READ_BUSERROR(addr, mask, addr_func) \
 433   do \
 434     { \
 435       if (addr & mask) \
 436         return addr_func (addr); \
 437     } \
 438   while (0)
 439
 440 /* Define this to enable register lifetime checking.
 441    The compiler generates "add #0,rn" insns to mark registers as invalid,
 442    the simulator uses this info to call fail if it finds a ref to an invalid
 443    register before a def
 444
 445    #define PARANOID
 446 */
 447
 448 #ifdef PARANOID
 449 int valid[16];
 450 #define CREF(x)  if (!valid[x]) fail ();
 451 #define CDEF(x)  valid[x] = 1;
 452 #define UNDEF(x) valid[x] = 0;
 453 #else
 454 #define CREF(x)
 455 #define CDEF(x)
 456 #define UNDEF(x)
 457 #endif
 458
 459 static void parse_and_set_memory_size PARAMS ((char *str));
 460 static int IOMEM PARAMS ((int addr, int write, int value));
 461 static struct loop_bounds get_loop_bounds PARAMS ((int, int, unsigned char *,
 462                                                    unsigned char *, int, int));
 463 static void process_wlat_addr PARAMS ((int, int));
 464 static void process_wwat_addr PARAMS ((int, int));
 465 static void process_wbat_addr PARAMS ((int, int));
 466 static int process_rlat_addr PARAMS ((int));
 467 static int process_rwat_addr PARAMS ((int));
 468 static int process_rbat_addr PARAMS ((int));
 469 static void INLINE wlat_fast PARAMS ((unsigned char *, int, int, int));
 470 static void INLINE wwat_fast PARAMS ((unsigned char *, int, int, int, int));
 471 static void INLINE wbat_fast PARAMS ((unsigned char *, int, int, int));
 472 static int INLINE rlat_fast PARAMS ((unsigned char *, int, int));
 473 static int INLINE rwat_fast PARAMS ((unsigned char *, int, int, int));
 474 static int INLINE rbat_fast PARAMS ((unsigned char *, int, int));
 475
 476 static host_callback *callback;
 477
 478
 479
 480 /* Floating point registers */
 481
 482 #define DR(n) (get_dr (n))
 483 static double
 484 get_dr (n)
 485      int n;
 486 {
 487   n = (n & ~1);
 488   if (host_little_endian)
 489     {
 490       union
 491       {
 492         int i[2];
 493         double d;
 494       } dr;
 495       dr.i[1] = saved_state.asregs.fregs[0].i[n + 0];
 496       dr.i[0] = saved_state.asregs.fregs[0].i[n + 1];
 497       return dr.d;
 498     }
 499   else
 500     return (saved_state.asregs.fregs[0].d[n >> 1]);
 501 }
 502
 503 #define SET_DR(n, EXP) set_dr ((n), (EXP))
 504 static void
 505 set_dr (n, exp)
 506      int n;
 507      double exp;
 508 {
 509   n = (n & ~1);
 510   if (host_little_endian)
 511     {
 512       union
 513       {
 514         int i[2];
 515         double d;
 516       } dr;
 517       dr.d = exp;
 518       saved_state.asregs.fregs[0].i[n + 0] = dr.i[1];
 519       saved_state.asregs.fregs[0].i[n + 1] = dr.i[0];
 520     }
 521   else
 522     saved_state.asregs.fregs[0].d[n >> 1] = exp;
 523 }
 524
 525 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
 526 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
 527
 528 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
 529 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
 530
 531 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
 532 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
 533 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
 534
 535 #define RS saved_state.asregs.cregs.named.rs
 536 #define RE saved_state.asregs.cregs.named.re
 537 #define MOD (saved_state.asregs.cregs.named.mod)
 538 #define SET_MOD(i) \
 539 (MOD = (i), \
 540  MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
 541  MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
 542
 543 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
 544 #define DSP_GRD(n) DSP_R ((n) + 8)
 545 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
 546 #define A1 DSP_R (5)
 547 #define A0 DSP_R (7)
 548 #define X0 DSP_R (8)
 549 #define X1 DSP_R (9)
 550 #define Y0 DSP_R (10)
 551 #define Y1 DSP_R (11)
 552 #define M0 DSP_R (12)
 553 #define A1G DSP_R (13)
 554 #define M1 DSP_R (14)
 555 #define A0G DSP_R (15)
 556 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp.  */
 557 #define MOD_ME DSP_GRD (17)
 558 #define MOD_DELTA DSP_GRD (18)
 559
 560 #define FP_OP(n, OP, m) \
 561 { \
 562   if (FPSCR_PR) \
 563     { \
 564       if (((n) & 1) || ((m) & 1)) \
 565         RAISE_EXCEPTION (SIGILL); \
 566       else \
 567         SET_DR (n, (DR (n) OP DR (m))); \
 568     } \
 569   else \
 570     SET_FR (n, (FR (n) OP FR (m))); \
 571 } while (0)
 572
 573 #define FP_UNARY(n, OP) \
 574 { \
 575   if (FPSCR_PR) \
 576     { \
 577       if ((n) & 1) \
 578         RAISE_EXCEPTION (SIGILL); \
 579       else \
 580         SET_DR (n, (OP (DR (n)))); \
 581     } \
 582   else \
 583     SET_FR (n, (OP (FR (n)))); \
 584 } while (0)
 585
 586 #define FP_CMP(n, OP, m) \
 587 { \
 588   if (FPSCR_PR) \
 589     { \
 590       if (((n) & 1) || ((m) & 1)) \
 591         RAISE_EXCEPTION (SIGILL); \
 592       else \
 593         SET_SR_T (DR (n) OP DR (m)); \
 594     } \
 595   else \
 596     SET_SR_T (FR (n) OP FR (m)); \
 597 } while (0)
 598
 599 static void
 600 set_sr (new_sr)
 601      int new_sr;
 602 {
 603   /* do we need to swap banks */
 604   int old_gpr = SR_MD && SR_RB;
 605   int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB);
 606   if (old_gpr != new_gpr)
 607     {
 608       int i, tmp;
 609       for (i = 0; i < 8; i++)
 610         {
 611           tmp = saved_state.asregs.cregs.named.bank[i];
 612           saved_state.asregs.cregs.named.bank[i] = saved_state.asregs.regs[i];
 613           saved_state.asregs.regs[i] = tmp;
 614         }
 615     }
 616   saved_state.asregs.cregs.named.sr = new_sr;
 617   SET_MOD (MOD);
 618 }
 619
 620 static void INLINE
 621 wlat_fast (memory, x, value, maskl)
 622      unsigned char *memory;
 623 {
 624   int v = value;
 625   unsigned int *p = (unsigned int *) (memory + x);
 626   WRITE_BUSERROR (x, maskl, v, process_wlat_addr);
 627   *p = v;
 628 }
 629
 630 static void INLINE
 631 wwat_fast (memory, x, value, maskw, endianw)
 632      unsigned char *memory;
 633 {
 634   int v = value;
 635   unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
 636   WRITE_BUSERROR (x, maskw, v, process_wwat_addr);
 637   *p = v;
 638 }
 639
 640 static void INLINE
 641 wbat_fast (memory, x, value, maskb)
 642      unsigned char *memory;
 643 {
 644   unsigned char *p = memory + (x ^ endianb);
 645   WRITE_BUSERROR (x, maskb, value, process_wbat_addr);
 646
 647   p[0] = value;
 648 }
 649
 650 /* Read functions */
 651
 652 static int INLINE
 653 rlat_fast (memory, x, maskl)
 654      unsigned char *memory;
 655 {
 656   unsigned int *p = (unsigned int *) (memory + x);
 657   READ_BUSERROR (x, maskl, process_rlat_addr);
 658
 659   return *p;
 660 }
 661
 662 static int INLINE
 663 rwat_fast (memory, x, maskw, endianw)
 664      unsigned char *memory;
 665      int x, maskw, endianw;
 666 {
 667   unsigned short *p = (unsigned short *) (memory + (x ^ endianw));
 668   READ_BUSERROR (x, maskw, process_rwat_addr);
 669
 670   return *p;
 671 }
 672
 673 static int INLINE
 674 riat_fast (insn_ptr, endianw)
 675      unsigned char *insn_ptr;
 676 {
 677   unsigned short *p = (unsigned short *) ((size_t) insn_ptr ^ endianw);
 678
 679   return *p;
 680 }
 681
 682 static int INLINE
 683 rbat_fast (memory, x, maskb)
 684      unsigned char *memory;
 685 {
 686   unsigned char *p = memory + (x ^ endianb);
 687   READ_BUSERROR (x, maskb, process_rbat_addr);
 688
 689   return *p;
 690 }
 691
 692 #define RWAT(x)         (rwat_fast (memory, x, maskw, endianw))
 693 #define RLAT(x)         (rlat_fast (memory, x, maskl))
 694 #define RBAT(x)         (rbat_fast (memory, x, maskb))
 695 #define RIAT(p)         (riat_fast ((p), endianw))
 696 #define WWAT(x,v)       (wwat_fast (memory, x, v, maskw, endianw))
 697 #define WLAT(x,v)       (wlat_fast (memory, x, v, maskl))
 698 #define WBAT(x,v)       (wbat_fast (memory, x, v, maskb))
 699
 700 #define RUWAT(x)  (RWAT (x) & 0xffff)
 701 #define RSWAT(x)  ((short) (RWAT (x)))
 702 #define RSLAT(x)  ((long) (RLAT (x)))
 703 #define RSBAT(x)  (SEXT (RBAT (x)))
 704
 705 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
 706 static int
 707 do_rdat (memory, x, n, maskl)
 708      char *memory;
 709      int x;
 710      int n;
 711      int maskl;
 712 {
 713   int f0;
 714   int f1;
 715   int i = (n & 1);
 716   int j = (n & ~1);
 717   f0 = rlat_fast (memory, x + 0, maskl);
 718   f1 = rlat_fast (memory, x + 4, maskl);
 719   saved_state.asregs.fregs[i].i[(j + 0)] = f0;
 720   saved_state.asregs.fregs[i].i[(j + 1)] = f1;
 721   return 0;
 722 }
 723
 724 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
 725 static int
 726 do_wdat (memory, x, n, maskl)
 727      char *memory;
 728      int x;
 729      int n;
 730      int maskl;
 731 {
 732   int f0;
 733   int f1;
 734   int i = (n & 1);
 735   int j = (n & ~1);
 736   f0 = saved_state.asregs.fregs[i].i[(j + 0)];
 737   f1 = saved_state.asregs.fregs[i].i[(j + 1)];
 738   wlat_fast (memory, (x + 0), f0, maskl);
 739   wlat_fast (memory, (x + 4), f1, maskl);
 740   return 0;
 741 }
 742
 743 static void
 744 process_wlat_addr (addr, value)
 745      int addr;
 746      int value;
 747 {
 748   unsigned int *ptr;
 749
 750   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, );
 751   *ptr = value;
 752 }
 753
 754 static void
 755 process_wwat_addr (addr, value)
 756      int addr;
 757      int value;
 758 {
 759   unsigned short *ptr;
 760
 761   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, );
 762   *ptr = value;
 763 }
 764
 765 static void
 766 process_wbat_addr (addr, value)
 767      int addr;
 768      int value;
 769 {
 770   unsigned char *ptr;
 771
 772   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, );
 773   *ptr = value;
 774 }
 775
 776 static int
 777 process_rlat_addr (addr)
 778      int addr;
 779 {
 780   unsigned char *ptr;
 781
 782   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0);
 783   return *ptr;
 784 }
 785
 786 static int
 787 process_rwat_addr (addr)
 788      int addr;
 789 {
 790   unsigned char *ptr;
 791
 792   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0);
 793   return *ptr;
 794 }
 795
 796 static int
 797 process_rbat_addr (addr)
 798      int addr;
 799 {
 800   unsigned char *ptr;
 801
 802   PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0);
 803   return *ptr;
 804 }
 805
 806 #define SEXT(x)         (((x &  0xff) ^ (~0x7f))+0x80)
 807 #define SEXT12(x)       (((x & 0xfff) ^ 0x800) - 0x800)
 808 #define SEXTW(y)        ((int) ((short) y))
 809 #if 0
 810 #define SEXT32(x)       ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
 811 #else
 812 #define SEXT32(x)       ((int) (x))
 813 #endif
 814 #define SIGN32(x)       (SEXT32 (x) >> 31)
 815
 816 /* convert pointer from target to host value.  */
 817 #define PT2H(x) ((x) + memory)
 818 /* convert pointer from host to target value.  */
 819 #define PH2T(x) ((x) - memory)
 820
 821 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
 822
 823 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
 824
 825 static int in_delay_slot = 0;
 826 #define Delay_Slot(TEMPPC)      iword = RIAT (TEMPPC); in_delay_slot = 1; goto top;
 827
 828 #define CHECK_INSN_PTR(p) \
 829 do { \
 830   if (saved_state.asregs.exception || PH2T (p) & maskw) \
 831     saved_state.asregs.insn_end = 0; \
 832   else if (p < loop.end) \
 833     saved_state.asregs.insn_end = loop.end; \
 834   else \
 835     saved_state.asregs.insn_end = mem_end; \
 836 } while (0)
 837
 838 #ifdef ACE_FAST
 839
 840 #define MA(n)
 841 #define L(x)
 842 #define TL(x)
 843 #define TB(x)
 844
 845 #else
 846
 847 #define MA(n) \
 848   do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
 849
 850 #define L(x)   thislock = x;
 851 #define TL(x)  if ((x) == prevlock) stalls++;
 852 #define TB(x,y)  if ((x) == prevlock || (y) == prevlock) stalls++;
 853
 854 #endif
 855
 856 #if defined(__GO32__)
 857 int sim_memory_size = 19;
 858 #else
 859 int sim_memory_size = 24;
 860 #endif
 861
 862 static int sim_profile_size = 17;
 863 static int nsamples;
 864
 865 #undef TB
 866 #define TB(x,y)
 867
 868 #define SMR1 (0x05FFFEC8)       /* Channel 1  serial mode register */
 869 #define BRR1 (0x05FFFEC9)       /* Channel 1  bit rate register */
 870 #define SCR1 (0x05FFFECA)       /* Channel 1  serial control register */
 871 #define TDR1 (0x05FFFECB)       /* Channel 1  transmit data register */
 872 #define SSR1 (0x05FFFECC)       /* Channel 1  serial status register */
 873 #define RDR1 (0x05FFFECD)       /* Channel 1  receive data register */
 874
 875 #define SCI_RDRF         0x40   /* Recieve data register full */
 876 #define SCI_TDRE        0x80    /* Transmit data register empty */
 877
 878 static int
 879 IOMEM (addr, write, value)
 880      int addr;
 881      int write;
 882      int value;
 883 {
 884   if (write)
 885     {
 886       switch (addr)
 887         {
 888         case TDR1:
 889           if (value != '\r')
 890             {
 891               putchar (value);
 892               fflush (stdout);
 893             }
 894           break;
 895         }
 896     }
 897   else
 898     {
 899       switch (addr)
 900         {
 901         case RDR1:
 902           return getchar ();
 903         }
 904     }
 905   return 0;
 906 }
 907
 908 static int
 909 get_now ()
 910 {
 911   return time ((long *) 0);
 912 }
 913
 914 static int
 915 now_persec ()
 916 {
 917   return 1;
 918 }
 919
 920 static FILE *profile_file;
 921
 922 static unsigned INLINE
 923 swap (n)
 924      unsigned n;
 925 {
 926   if (endianb)
 927     n = (n << 24 | (n & 0xff00) << 8
 928          | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24);
 929   return n;
 930 }
 931
 932 static unsigned short INLINE
 933 swap16 (n)
 934      unsigned short n;
 935 {
 936   if (endianb)
 937     n = n << 8 | (n & 0xff00) >> 8;
 938   return n;
 939 }
 940
 941 static void
 942 swapout (n)
 943      int n;
 944 {
 945   if (profile_file)
 946     {
 947       union { char b[4]; int n; } u;
 948       u.n = swap (n);
 949       fwrite (u.b, 4, 1, profile_file);
 950     }
 951 }
 952
 953 static void
 954 swapout16 (n)
 955      int n;
 956 {
 957   union { char b[4]; int n; } u;
 958   u.n = swap16 (n);
 959   fwrite (u.b, 2, 1, profile_file);
 960 }
 961
 962 /* Turn a pointer in a register into a pointer into real memory. */
 963
 964 static char *
 965 ptr (x)
 966      int x;
 967 {
 968   return (char *) (x + saved_state.asregs.memory);
 969 }
 970
 971 /* STR points to a zero-terminated string in target byte order.  Return
 972    the number of bytes that need to be converted to host byte order in order
 973    to use this string as a zero-terminated string on the host.
 974    (Not counting the rounding up needed to operate on entire words.)  */
 975 static int
 976 strswaplen (str)
 977      int str;
 978 {
 979   unsigned char *memory = saved_state.asregs.memory;
 980   int start, end;
 981   int endian = endianb;
 982
 983   if (! endian)
 984     return 0;
 985   end = str;
 986   for (end = str; memory[end ^ endian]; end++) ;
 987   return end - str + 1;
 988 }
 989
 990 static void
 991 strnswap (str, len)
 992      int str;
 993      int len;
 994 {
 995   int *start, *end;
 996
 997   if (! endianb || ! len)
 998     return;
 999   start = (int *) ptr (str & ~3);
1000   end = (int *) ptr (str + len);
1001   do
1002     {
1003       int old = *start;
1004       *start = (old << 24 | (old & 0xff00) << 8
1005                 | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24);
1006       start++;
1007     }
1008   while (start < end);
1009 }
1010
1011 /* Simulate a monitor trap, put the result into r0 and errno into r1
1012    return offset by which to adjust pc.  */
1013
1014 static int
1015 trap (i, regs, insn_ptr, memory, maskl, maskw, endianw)
1016      int i;
1017      int *regs;
1018      unsigned char *insn_ptr;
1019      unsigned char *memory;
1020 {
1021   switch (i)
1022     {
1023     case 1:
1024       printf ("%c", regs[0]);
1025       break;
1026     case 2:
1027       raise_exception (SIGQUIT);
1028       break;
1029     case 3:                     /* FIXME: for backwards compat, should be removed */
1030     case 33:
1031       {
1032         unsigned int countp = * (unsigned int *) (insn_ptr + 4);
1033
1034         WLAT (countp, RLAT (countp) + 1);
1035         return 6;
1036       }
1037     case 34:
1038       {
1039         extern int errno;
1040         int perrno = errno;
1041         errno = 0;
1042
1043         switch (regs[4])
1044           {
1045
1046 #if !defined(__GO32__) && !defined(_WIN32)
1047           case SYS_fork:
1048             regs[0] = fork ();
1049             break;
1050 /* This would work only if endianness matched between host and target.
1051    Besides, it's quite dangerous.  */
1052 #if 0
1053           case SYS_execve:
1054             regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]),
1055                               (char **) ptr (regs[7]));
1056             break;
1057           case SYS_execv:
1058             regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0);
1059             break;
1060 #endif
1061           case SYS_pipe:
1062             {
1063               regs[0] = (BUSERROR (regs[5], maskl)
1064                          ? -EINVAL
1065                          : pipe ((int *) ptr (regs[5])));
1066             }
1067             break;
1068
1069           case SYS_wait:
1070             regs[0] = wait (ptr (regs[5]));
1071             break;
1072 #endif /* !defined(__GO32__) && !defined(_WIN32) */
1073
1074           case SYS_read:
1075             strnswap (regs[6], regs[7]);
1076             regs[0]
1077               = callback->read (callback, regs[5], ptr (regs[6]), regs[7]);
1078             strnswap (regs[6], regs[7]);
1079             break;
1080           case SYS_write:
1081             strnswap (regs[6], regs[7]);
1082             if (regs[5] == 1)
1083               regs[0] = (int) callback->write_stdout (callback,
1084                                                       ptr (regs[6]), regs[7]);
1085             else
1086               regs[0] = (int) callback->write (callback, regs[5],
1087                                                ptr (regs[6]), regs[7]);
1088             strnswap (regs[6], regs[7]);
1089             break;
1090           case SYS_lseek:
1091             regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]);
1092             break;
1093           case SYS_close:
1094             regs[0] = callback->close (callback,regs[5]);
1095             break;
1096           case SYS_open:
1097             {
1098               int len = strswaplen (regs[5]);
1099               strnswap (regs[5], len);
1100               regs[0] = callback->open (callback, ptr (regs[5]), regs[6]);
1101               strnswap (regs[5], len);
1102               break;
1103             }
1104           case SYS_exit:
1105             /* EXIT - caller can look in r5 to work out the reason */
1106             raise_exception (SIGQUIT);
1107             regs[0] = regs[5];
1108             break;
1109
1110           case SYS_stat:        /* added at hmsi */
1111             /* stat system call */
1112             {
1113               struct stat host_stat;
1114               int buf;
1115               int len = strswaplen (regs[5]);
1116
1117               strnswap (regs[5], len);
1118               regs[0] = stat (ptr (regs[5]), &host_stat);
1119               strnswap (regs[5], len);
1120
1121               buf = regs[6];
1122
1123               WWAT (buf, host_stat.st_dev);
1124               buf += 2;
1125               WWAT (buf, host_stat.st_ino);
1126               buf += 2;
1127               WLAT (buf, host_stat.st_mode);
1128               buf += 4;
1129               WWAT (buf, host_stat.st_nlink);
1130               buf += 2;
1131               WWAT (buf, host_stat.st_uid);
1132               buf += 2;
1133               WWAT (buf, host_stat.st_gid);
1134               buf += 2;
1135               WWAT (buf, host_stat.st_rdev);
1136               buf += 2;
1137               WLAT (buf, host_stat.st_size);
1138               buf += 4;
1139               WLAT (buf, host_stat.st_atime);
1140               buf += 4;
1141               WLAT (buf, 0);
1142               buf += 4;
1143               WLAT (buf, host_stat.st_mtime);
1144               buf += 4;
1145               WLAT (buf, 0);
1146               buf += 4;
1147               WLAT (buf, host_stat.st_ctime);
1148               buf += 4;
1149               WLAT (buf, 0);
1150               buf += 4;
1151               WLAT (buf, 0);
1152               buf += 4;
1153               WLAT (buf, 0);
1154               buf += 4;
1155             }
1156             break;
1157
1158 #ifndef _WIN32
1159           case SYS_chown:
1160             {
1161               int len = strswaplen (regs[5]);
1162
1163               strnswap (regs[5], len);
1164               regs[0] = chown (ptr (regs[5]), regs[6], regs[7]);
1165               strnswap (regs[5], len);
1166               break;
1167             }
1168 #endif /* _WIN32 */
1169           case SYS_chmod:
1170             {
1171               int len = strswaplen (regs[5]);
1172
1173               strnswap (regs[5], len);
1174               regs[0] = chmod (ptr (regs[5]), regs[6]);
1175               strnswap (regs[5], len);
1176               break;
1177             }
1178           case SYS_utime:
1179             {
1180               /* Cast the second argument to void *, to avoid type mismatch
1181                  if a prototype is present.  */
1182               int len = strswaplen (regs[5]);
1183
1184               strnswap (regs[5], len);
1185               regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6]));
1186               strnswap (regs[5], len);
1187               break;
1188             }
1189           case SYS_argc:
1190             regs[0] = count_argc (prog_argv);
1191             break;
1192           case SYS_argnlen:
1193             if (regs[5] < count_argc (prog_argv))
1194               regs[0] = strlen (prog_argv[regs[5]]);
1195             else
1196               regs[0] = -1;
1197             break;
1198           case SYS_argn:
1199             if (regs[5] < count_argc (prog_argv))
1200               {
1201                 /* Include the termination byte.  */
1202                 int i = strlen (prog_argv[regs[5]]) + 1;
1203                 regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], i);
1204               }
1205             else
1206               regs[0] = -1;
1207             break;
1208           case SYS_time:
1209             regs[0] = get_now ();
1210             break;
1211           case SYS_ftruncate:
1212             regs[0] = callback->ftruncate (callback, regs[5], regs[6]);
1213             break;
1214           case SYS_truncate:
1215             {
1216               int len = strswaplen (regs[5]);
1217               strnswap (regs[5], len);
1218               regs[0] = callback->truncate (callback, ptr (regs[5]), regs[6]);
1219               strnswap (regs[5], len);
1220               break;
1221             }
1222           default:
1223             regs[0] = -1;
1224             break;
1225           }
1226         regs[1] = callback->get_errno (callback);
1227         errno = perrno;
1228       }
1229       break;
1230
1231     case 13:    /* Set IBNR */
1232       IBNR = regs[0] & 0xffff;
1233       break;
1234     case 14:    /* Set IBCR */
1235       IBCR = regs[0] & 0xffff;
1236       break;
1237     case 0xc3:
1238     case 255:
1239       raise_exception (SIGTRAP);
1240       if (i == 0xc3)
1241         return -2;
1242       break;
1243     }
1244   return 0;
1245 }
1246
1247 void
1248 control_c (sig, code, scp, addr)
1249      int sig;
1250      int code;
1251      char *scp;
1252      char *addr;
1253 {
1254   raise_exception (SIGINT);
1255 }
1256
1257 static int
1258 div1 (R, iRn2, iRn1/*, T*/)
1259      int *R;
1260      int iRn1;
1261      int iRn2;
1262      /* int T;*/
1263 {
1264   unsigned long tmp0;
1265   unsigned char old_q, tmp1;
1266
1267   old_q = Q;
1268   SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0));
1269   R[iRn1] <<= 1;
1270   R[iRn1] |= (unsigned long) T;
1271
1272   switch (old_q)
1273     {
1274     case 0:
1275       switch (M)
1276         {
1277         case 0:
1278           tmp0 = R[iRn1];
1279           R[iRn1] -= R[iRn2];
1280           tmp1 = (R[iRn1] > tmp0);
1281           switch (Q)
1282             {
1283             case 0:
1284               SET_SR_Q (tmp1);
1285               break;
1286             case 1:
1287               SET_SR_Q ((unsigned char) (tmp1 == 0));
1288               break;
1289             }
1290           break;
1291         case 1:
1292           tmp0 = R[iRn1];
1293           R[iRn1] += R[iRn2];
1294           tmp1 = (R[iRn1] < tmp0);
1295           switch (Q)
1296             {
1297             case 0:
1298               SET_SR_Q ((unsigned char) (tmp1 == 0));
1299               break;
1300             case 1:
1301               SET_SR_Q (tmp1);
1302               break;
1303             }
1304           break;
1305         }
1306       break;
1307     case 1:
1308       switch (M)
1309         {
1310         case 0:
1311           tmp0 = R[iRn1];
1312           R[iRn1] += R[iRn2];
1313           tmp1 = (R[iRn1] < tmp0);
1314           switch (Q)
1315             {
1316             case 0:
1317               SET_SR_Q (tmp1);
1318               break;
1319             case 1:
1320               SET_SR_Q ((unsigned char) (tmp1 == 0));
1321               break;
1322             }
1323           break;
1324         case 1:
1325           tmp0 = R[iRn1];
1326           R[iRn1] -= R[iRn2];
1327           tmp1 = (R[iRn1] > tmp0);
1328           switch (Q)
1329             {
1330             case 0:
1331               SET_SR_Q ((unsigned char) (tmp1 == 0));
1332               break;
1333             case 1:
1334               SET_SR_Q (tmp1);
1335               break;
1336             }
1337           break;
1338         }
1339       break;
1340     }
1341   /*T = (Q == M);*/
1342   SET_SR_T (Q == M);
1343   /*return T;*/
1344 }
1345
1346 static void
1347 dmul (sign, rm, rn)
1348      int sign;
1349      unsigned int rm;
1350      unsigned int rn;
1351 {
1352   unsigned long RnL, RnH;
1353   unsigned long RmL, RmH;
1354   unsigned long temp0, temp1, temp2, temp3;
1355   unsigned long Res2, Res1, Res0;
1356
1357   RnL = rn & 0xffff;
1358   RnH = (rn >> 16) & 0xffff;
1359   RmL = rm & 0xffff;
1360   RmH = (rm >> 16) & 0xffff;
1361   temp0 = RmL * RnL;
1362   temp1 = RmH * RnL;
1363   temp2 = RmL * RnH;
1364   temp3 = RmH * RnH;
1365   Res2 = 0;
1366   Res1 = temp1 + temp2;
1367   if (Res1 < temp1)
1368     Res2 += 0x00010000;
1369   temp1 = (Res1 << 16) & 0xffff0000;
1370   Res0 = temp0 + temp1;
1371   if (Res0 < temp0)
1372     Res2 += 1;
1373   Res2 += ((Res1 >> 16) & 0xffff) + temp3;
1374
1375   if (sign)
1376     {
1377       if (rn & 0x80000000)
1378         Res2 -= rm;
1379       if (rm & 0x80000000)
1380         Res2 -= rn;
1381     }
1382
1383   MACH = Res2;
1384   MACL = Res0;
1385 }
1386
1387 static void
1388 macw (regs, memory, n, m, endianw)
1389      int *regs;
1390      unsigned char *memory;
1391      int m, n;
1392      int endianw;
1393 {
1394   long tempm, tempn;
1395   long prod, macl, sum;
1396
1397   tempm=RSWAT (regs[m]); regs[m]+=2;
1398   tempn=RSWAT (regs[n]); regs[n]+=2;
1399
1400   macl = MACL;
1401   prod = (long) (short) tempm * (long) (short) tempn;
1402   sum = prod + macl;
1403   if (S)
1404     {
1405       if ((~(prod ^ macl) & (sum ^ prod)) < 0)
1406         {
1407           /* MACH's lsb is a sticky overflow bit.  */
1408           MACH |= 1;
1409           /* Store the smallest negative number in MACL if prod is
1410              negative, and the largest positive number otherwise.  */
1411           sum = 0x7fffffff + (prod < 0);
1412         }
1413     }
1414   else
1415     {
1416       long mach;
1417       /* Add to MACH the sign extended product, and carry from low sum.  */
1418       mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod);
1419       /* Sign extend at 10:th bit in MACH.  */
1420       MACH = (mach & 0x1ff) | -(mach & 0x200);
1421     }
1422   MACL = sum;
1423 }
1424
1425 static void
1426 macl (regs, memory, n, m)
1427      int *regs;
1428      unsigned char *memory;
1429      int m, n;
1430 {
1431   long tempm, tempn;
1432   long prod, macl, mach, sum;
1433   long long ans,ansl,ansh,t;
1434   unsigned long long high,low,combine;
1435   union mac64
1436   {
1437     long m[2]; /* mach and macl*/
1438     long long m64; /* 64 bit MAC */
1439   }mac64;
1440
1441   tempm = RSLAT (regs[m]);
1442   regs[m] += 4;
1443
1444   tempn = RSLAT (regs[n]);
1445   regs[n] += 4;
1446
1447   mach = MACH;
1448   macl = MACL;
1449
1450   mac64.m[0] = macl;
1451   mac64.m[1] = mach;
1452
1453   ans = (long long) tempm * (long long) tempn; /* Multiply 32bit * 32bit */
1454
1455   mac64.m64 += ans; /* Accumulate   64bit + 64 bit */
1456
1457   macl = mac64.m[0];
1458   mach = mac64.m[1];
1459
1460   if (S)  /* Store only 48 bits of the result */
1461     {
1462       if (mach < 0) /* Result is negative */
1463         {
1464           mach = mach & 0x0000ffff; /* Mask higher 16 bits */
1465           mach |= 0xffff8000; /* Sign extend higher 16 bits */
1466         }
1467       else
1468         mach = mach & 0x00007fff; /* Postive Result */
1469     }
1470
1471   MACL = macl;
1472   MACH = mach;
1473 }
1474
1475 enum {
1476   B_BCLR = 0,
1477   B_BSET = 1,
1478   B_BST  = 2,
1479   B_BLD  = 3,
1480   B_BAND = 4,
1481   B_BOR  = 5,
1482   B_BXOR = 6,
1483   B_BLDNOT = 11,
1484   B_BANDNOT = 12,
1485   B_BORNOT = 13,
1486
1487   MOVB_RM = 0x0000,
1488   MOVW_RM = 0x1000,
1489   MOVL_RM = 0x2000,
1490   FMOV_RM = 0x3000,
1491   MOVB_MR = 0x4000,
1492   MOVW_MR = 0x5000,
1493   MOVL_MR = 0x6000,
1494   FMOV_MR = 0x7000,
1495   MOVU_BMR = 0x8000,
1496   MOVU_WMR = 0x9000,
1497 };
1498
1499 /* Do extended displacement move instructions.  */
1500 void
1501 do_long_move_insn (int op, int disp12, int m, int n, int *thatlock)
1502 {
1503   int memstalls = 0;
1504   int thislock = *thatlock;
1505   int endianw = global_endianw;
1506   int *R = &(saved_state.asregs.regs[0]);
1507   unsigned char *memory = saved_state.asregs.memory;
1508   int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1509   unsigned char *insn_ptr = PT2H (saved_state.asregs.pc);
1510
1511   switch (op) {
1512   case MOVB_RM:         /* signed */
1513     WBAT (disp12 * 1 + R[n], R[m]);
1514     break;
1515   case MOVW_RM:
1516     WWAT (disp12 * 2 + R[n], R[m]);
1517     break;
1518   case MOVL_RM:
1519     WLAT (disp12 * 4 + R[n], R[m]);
1520     break;
1521   case FMOV_RM:         /* floating point */
1522     if (FPSCR_SZ)
1523       {
1524         MA (1);
1525         WDAT (R[n] + 8 * disp12, m);
1526       }
1527     else
1528       WLAT (R[n] + 4 * disp12, FI (m));
1529     break;
1530   case MOVB_MR:
1531     R[n] = RSBAT (disp12 * 1 + R[m]);
1532     L (n);
1533     break;
1534   case MOVW_MR:
1535     R[n] = RSWAT (disp12 * 2 + R[m]);
1536     L (n);
1537     break;
1538   case MOVL_MR:
1539     R[n] = RLAT (disp12 * 4 + R[m]);
1540     L (n);
1541     break;
1542   case FMOV_MR:
1543     if (FPSCR_SZ) {
1544       MA (1);
1545       RDAT (R[m] + 8 * disp12, n);
1546     }
1547     else
1548       SET_FI (n, RLAT (R[m] + 4 * disp12));
1549     break;
1550   case MOVU_BMR:        /* unsigned */
1551     R[n] = RBAT (disp12 * 1 + R[m]);
1552     L (n);
1553     break;
1554   case MOVU_WMR:
1555     R[n] = RWAT (disp12 * 2 + R[m]);
1556     L (n);
1557     break;
1558   default:
1559     RAISE_EXCEPTION (SIGINT);
1560     exit (1);
1561   }
1562   saved_state.asregs.memstalls += memstalls;
1563   *thatlock = thislock;
1564 }
1565
1566 /* Do binary logical bit-manipulation insns.  */
1567 void
1568 do_blog_insn (int imm, int addr, int binop,
1569               unsigned char *memory, int maskb)
1570 {
1571   int oldval = RBAT (addr);
1572
1573   switch (binop) {
1574   case B_BCLR:  /* bclr.b */
1575     WBAT (addr, oldval & ~imm);
1576     break;
1577   case B_BSET:  /* bset.b */
1578     WBAT (addr, oldval | imm);
1579     break;
1580   case B_BST:   /* bst.b */
1581     if (T)
1582       WBAT (addr, oldval | imm);
1583     else
1584       WBAT (addr, oldval & ~imm);
1585     break;
1586   case B_BLD:   /* bld.b */
1587     SET_SR_T ((oldval & imm) != 0);
1588     break;
1589   case B_BAND:  /* band.b */
1590     SET_SR_T (T && ((oldval & imm) != 0));
1591     break;
1592   case B_BOR:   /* bor.b */
1593     SET_SR_T (T || ((oldval & imm) != 0));
1594     break;
1595   case B_BXOR:  /* bxor.b */
1596     SET_SR_T (T ^ ((oldval & imm) != 0));
1597     break;
1598   case B_BLDNOT:        /* bldnot.b */
1599     SET_SR_T ((oldval & imm) == 0);
1600     break;
1601   case B_BANDNOT:       /* bandnot.b */
1602     SET_SR_T (T && ((oldval & imm) == 0));
1603     break;
1604   case B_BORNOT:        /* bornot.b */
1605     SET_SR_T (T || ((oldval & imm) == 0));
1606     break;
1607   }
1608 }
1609 float
1610 fsca_s (int in, double (*f) (double))
1611 {
1612   double rad = ldexp ((in & 0xffff), -15) * 3.141592653589793238462643383;
1613   double result = (*f) (rad);
1614   double error, upper, lower, frac;
1615   int exp;
1616
1617   /* Search the value with the maximum error that is still within the
1618      architectural spec.  */
1619   error = ldexp (1., -21);
1620   /* compensate for calculation inaccuracy by reducing error.  */
1621   error = error - ldexp (1., -50);
1622   upper = result + error;
1623   frac = frexp (upper, &exp);
1624   upper = ldexp (floor (ldexp (frac, 24)), exp - 24);
1625   lower = result - error;
1626   frac = frexp (lower, &exp);
1627   lower = ldexp (ceil (ldexp (frac, 24)), exp - 24);
1628   return abs (upper - result) >= abs (lower - result) ? upper : lower;
1629 }
1630
1631 float
1632 fsrra_s (float in)
1633 {
1634   double result = 1. / sqrt (in);
1635   int exp;
1636   double frac, upper, lower, error, eps;
1637
1638   /* refine result */
1639   result = result - (result * result * in - 1) * 0.5 * result;
1640   /* Search the value with the maximum error that is still within the
1641      architectural spec.  */
1642   frac = frexp (result, &exp);
1643   frac = ldexp (frac, 24);
1644   error = 4.0; /* 1 << 24-1-21 */
1645   /* use eps to compensate for possible 1 ulp error in our 'exact' result.  */
1646   eps = ldexp (1., -29);
1647   upper = floor (frac + error - eps);
1648   if (upper > 16777216.)
1649     upper = floor ((frac + error - eps) * 0.5) * 2.;
1650   lower = ceil ((frac - error + eps) * 2) * .5;
1651   if (lower > 8388608.)
1652     lower = ceil (frac - error + eps);
1653   upper = ldexp (upper, exp - 24);
1654   lower = ldexp (lower, exp - 24);
1655   return upper - result >= result - lower ? upper : lower;
1656 }
1657
1658
1659 /* GET_LOOP_BOUNDS {EXTENDED}
1660    These two functions compute the actual starting and ending point
1661    of the repeat loop, based on the RS and RE registers (repeat start,
1662    repeat stop).  The extended version is called for LDRC, and the
1663    regular version is called for SETRC.  The difference is that for
1664    LDRC, the loop start and end instructions are literally the ones
1665    pointed to by RS and RE -- for SETRC, they're not (see docs).  */
1666
1667 static struct loop_bounds
1668 get_loop_bounds_ext (rs, re, memory, mem_end, maskw, endianw)
1669      int rs, re;
1670      unsigned char *memory, *mem_end;
1671      int maskw, endianw;
1672 {
1673   struct loop_bounds loop;
1674
1675   /* FIXME: should I verify RS < RE?  */
1676   loop.start = PT2H (RS);       /* FIXME not using the params?  */
1677   loop.end   = PT2H (RE & ~1);  /* Ignore bit 0 of RE.  */
1678   SKIP_INSN (loop.end);
1679   if (loop.end >= mem_end)
1680     loop.end = PT2H (0);
1681   return loop;
1682 }
1683
1684 static struct loop_bounds
1685 get_loop_bounds (rs, re, memory, mem_end, maskw, endianw)
1686      int rs, re;
1687      unsigned char *memory, *mem_end;
1688      int maskw, endianw;
1689 {
1690   struct loop_bounds loop;
1691
1692   if (SR_RC)
1693     {
1694       if (RS >= RE)
1695         {
1696           loop.start = PT2H (RE - 4);
1697           SKIP_INSN (loop.start);
1698           loop.end = loop.start;
1699           if (RS - RE == 0)
1700             SKIP_INSN (loop.end);
1701           if (RS - RE <= 2)
1702             SKIP_INSN (loop.end);
1703           SKIP_INSN (loop.end);
1704         }
1705       else
1706         {
1707           loop.start = PT2H (RS);
1708           loop.end = PT2H (RE - 4);
1709           SKIP_INSN (loop.end);
1710           SKIP_INSN (loop.end);
1711           SKIP_INSN (loop.end);
1712           SKIP_INSN (loop.end);
1713         }
1714       if (loop.end >= mem_end)
1715         loop.end = PT2H (0);
1716     }
1717   else
1718     loop.end = PT2H (0);
1719
1720   return loop;
1721 }
1722
1723 static void ppi_insn ();
1724
1725 #include "ppi.c"
1726
1727 /* Provide calloc / free versions that use an anonymous mmap.  This can
1728    significantly cut the start-up time when a large simulator memory is
1729    required, because pages are only zeroed on demand.  */
1730 #ifdef MAP_ANONYMOUS
1731 void *
1732 mcalloc (size_t nmemb, size_t size)
1733 {
1734   void *page;
1735
1736   if (nmemb != 1)
1737     size *= nmemb;
1738   return mmap (0, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS,
1739                -1, 0);
1740 }
1741
1742 #define mfree(start,length) munmap ((start), (length))
1743 #else
1744 #define mcalloc calloc
1745 #define mfree(start,length) free(start)
1746 #endif
1747
1748 /* Set the memory size to the power of two provided. */
1749
1750 void
1751 sim_size (power)
1752      int power;
1753
1754 {
1755   sim_memory_size = power;
1756
1757   if (saved_state.asregs.memory)
1758     {
1759       mfree (saved_state.asregs.memory, saved_state.asregs.msize);
1760     }
1761
1762   saved_state.asregs.msize = 1 << power;
1763
1764   saved_state.asregs.memory =
1765     (unsigned char *) mcalloc (1, saved_state.asregs.msize);
1766
1767   if (!saved_state.asregs.memory)
1768     {
1769       fprintf (stderr,
1770                "Not enough VM for simulation of %d bytes of RAM\n",
1771                saved_state.asregs.msize);
1772
1773       saved_state.asregs.msize = 1;
1774       saved_state.asregs.memory = (unsigned char *) mcalloc (1, 1);
1775     }
1776 }
1777
1778 static void
1779 init_dsp (abfd)
1780      struct bfd *abfd;
1781 {
1782   int was_dsp = target_dsp;
1783   unsigned long mach = bfd_get_mach (abfd);
1784
1785   if (mach == bfd_mach_sh_dsp  ||
1786       mach == bfd_mach_sh4al_dsp ||
1787       mach == bfd_mach_sh3_dsp)
1788     {
1789       int ram_area_size, xram_start, yram_start;
1790       int new_select;
1791
1792       target_dsp = 1;
1793       if (mach == bfd_mach_sh_dsp)
1794         {
1795           /* SH7410 (orig. sh-sdp):
1796              4KB each for X & Y memory;
1797              On-chip X RAM 0x0800f000-0x0800ffff
1798              On-chip Y RAM 0x0801f000-0x0801ffff  */
1799           xram_start = 0x0800f000;
1800           ram_area_size = 0x1000;
1801         }
1802       if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp)
1803         {
1804           /* SH7612:
1805              8KB each for X & Y memory;
1806              On-chip X RAM 0x1000e000-0x1000ffff
1807              On-chip Y RAM 0x1001e000-0x1001ffff  */
1808           xram_start = 0x1000e000;
1809           ram_area_size = 0x2000;
1810         }
1811       yram_start = xram_start + 0x10000;
1812       new_select = ~(ram_area_size - 1);
1813       if (saved_state.asregs.xyram_select != new_select)
1814         {
1815           saved_state.asregs.xyram_select = new_select;
1816           free (saved_state.asregs.xmem);
1817           free (saved_state.asregs.ymem);
1818           saved_state.asregs.xmem =
1819             (unsigned char *) calloc (1, ram_area_size);
1820           saved_state.asregs.ymem =
1821             (unsigned char *) calloc (1, ram_area_size);
1822
1823           /* Disable use of X / Y mmeory if not allocated.  */
1824           if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem)
1825             {
1826               saved_state.asregs.xyram_select = 0;
1827               if (saved_state.asregs.xmem)
1828                 free (saved_state.asregs.xmem);
1829               if (saved_state.asregs.ymem)
1830                 free (saved_state.asregs.ymem);
1831             }
1832         }
1833       saved_state.asregs.xram_start = xram_start;
1834       saved_state.asregs.yram_start = yram_start;
1835       saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start;
1836       saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start;
1837     }
1838   else
1839     {
1840       target_dsp = 0;
1841       if (saved_state.asregs.xyram_select)
1842         {
1843           saved_state.asregs.xyram_select = 0;
1844           free (saved_state.asregs.xmem);
1845           free (saved_state.asregs.ymem);
1846         }
1847     }
1848
1849   if (! saved_state.asregs.xyram_select)
1850     {
1851       saved_state.asregs.xram_start = 1;
1852       saved_state.asregs.yram_start = 1;
1853     }
1854
1855   if (saved_state.asregs.regstack == NULL)
1856     saved_state.asregs.regstack =
1857       calloc (512, sizeof *saved_state.asregs.regstack);
1858
1859   if (target_dsp != was_dsp)
1860     {
1861       int i, tmp;
1862
1863       for (i = (sizeof sh_dsp_table / sizeof sh_dsp_table[0]) - 1; i >= 0; i--)
1864         {
1865           tmp = sh_jump_table[0xf000 + i];
1866           sh_jump_table[0xf000 + i] = sh_dsp_table[i];
1867           sh_dsp_table[i] = tmp;
1868         }
1869     }
1870 }
1871
1872 static void
1873 init_pointers ()
1874 {
1875   host_little_endian = 0;
1876   * (char*) &host_little_endian = 1;
1877   host_little_endian &= 1;
1878
1879   if (saved_state.asregs.msize != 1 << sim_memory_size)
1880     {
1881       sim_size (sim_memory_size);
1882     }
1883
1884   if (saved_state.asregs.profile && !profile_file)
1885     {
1886       profile_file = fopen ("gmon.out", "wb");
1887       /* Seek to where to put the call arc data */
1888       nsamples = (1 << sim_profile_size);
1889
1890       fseek (profile_file, nsamples * 2 + 12, 0);
1891
1892       if (!profile_file)
1893         {
1894           fprintf (stderr, "Can't open gmon.out\n");
1895         }
1896       else
1897         {
1898           saved_state.asregs.profile_hist =
1899             (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
1900         }
1901     }
1902 }
1903
1904 static void
1905 dump_profile ()
1906 {
1907   unsigned int minpc;
1908   unsigned int maxpc;
1909   unsigned short *p;
1910   int i;
1911
1912   p = saved_state.asregs.profile_hist;
1913   minpc = 0;
1914   maxpc = (1 << sim_profile_size);
1915
1916   fseek (profile_file, 0L, 0);
1917   swapout (minpc << PROFILE_SHIFT);
1918   swapout (maxpc << PROFILE_SHIFT);
1919   swapout (nsamples * 2 + 12);
1920   for (i = 0; i < nsamples; i++)
1921     swapout16 (saved_state.asregs.profile_hist[i]);
1922
1923 }
1924
1925 static void
1926 gotcall (from, to)
1927      int from;
1928      int to;
1929 {
1930   swapout (from);
1931   swapout (to);
1932   swapout (1);
1933 }
1934
1935 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1936
1937 int
1938 sim_stop (sd)
1939      SIM_DESC sd;
1940 {
1941   raise_exception (SIGINT);
1942   return 1;
1943 }
1944
1945 void
1946 sim_resume (sd, step, siggnal)
1947      SIM_DESC sd;
1948      int step, siggnal;
1949 {
1950   register unsigned char *insn_ptr;
1951   unsigned char *mem_end;
1952   struct loop_bounds loop;
1953   register int cycles = 0;
1954   register int stalls = 0;
1955   register int memstalls = 0;
1956   register int insts = 0;
1957   register int prevlock;
1958 #if 1
1959   int thislock;
1960 #else
1961   register int thislock;
1962 #endif
1963   register unsigned int doprofile;
1964   register int pollcount = 0;
1965   /* endianw is used for every insn fetch, hence it makes sense to cache it.
1966      endianb is used less often.  */
1967   register int endianw = global_endianw;
1968
1969   int tick_start = get_now ();
1970   void (*prev) ();
1971   void (*prev_fpe) ();
1972
1973   register unsigned short *jump_table = sh_jump_table;
1974
1975   register int *R = &(saved_state.asregs.regs[0]);
1976   /*register int T;*/
1977 #ifndef PR
1978   register int PR;
1979 #endif
1980
1981   register int maskb = ~((saved_state.asregs.msize - 1) & ~0);
1982   register int maskw = ~((saved_state.asregs.msize - 1) & ~1);
1983   register int maskl = ~((saved_state.asregs.msize - 1) & ~3);
1984   register unsigned char *memory;
1985   register unsigned int sbit = ((unsigned int) 1 << 31);
1986
1987   prev = signal (SIGINT, control_c);
1988   prev_fpe = signal (SIGFPE, SIG_IGN);
1989
1990   init_pointers ();
1991   saved_state.asregs.exception = 0;
1992
1993   memory = saved_state.asregs.memory;
1994   mem_end = memory + saved_state.asregs.msize;
1995
1996   if (RE & 1)
1997     loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw);
1998   else
1999     loop = get_loop_bounds     (RS, RE, memory, mem_end, maskw, endianw);
2000
2001   insn_ptr = PT2H (saved_state.asregs.pc);
2002   CHECK_INSN_PTR (insn_ptr);
2003
2004 #ifndef PR
2005   PR = saved_state.asregs.sregs.named.pr;
2006 #endif
2007   /*T = GET_SR () & SR_MASK_T;*/
2008   prevlock = saved_state.asregs.prevlock;
2009   thislock = saved_state.asregs.thislock;
2010   doprofile = saved_state.asregs.profile;
2011
2012   /* If profiling not enabled, disable it by asking for
2013      profiles infrequently. */
2014   if (doprofile == 0)
2015     doprofile = ~0;
2016
2017  loop:
2018   if (step && insn_ptr < saved_state.asregs.insn_end)
2019     {
2020       if (saved_state.asregs.exception)
2021         /* This can happen if we've already been single-stepping and
2022            encountered a loop end.  */
2023         saved_state.asregs.insn_end = insn_ptr;
2024       else
2025         {
2026           saved_state.asregs.exception = SIGTRAP;
2027           saved_state.asregs.insn_end = insn_ptr + 2;
2028         }
2029     }
2030
2031   while (insn_ptr < saved_state.asregs.insn_end)
2032     {
2033       register unsigned int iword = RIAT (insn_ptr);
2034       register unsigned int ult;
2035       register unsigned char *nip = insn_ptr + 2;
2036
2037 #ifndef ACE_FAST
2038       insts++;
2039 #endif
2040     top:
2041       if (tracing)
2042         fprintf (stderr, "PC: %08x, insn: %04x\n", PH2T (insn_ptr), iword);
2043
2044 #include "code.c"
2045
2046
2047       in_delay_slot = 0;
2048       insn_ptr = nip;
2049
2050       if (--pollcount < 0)
2051         {
2052           pollcount = POLL_QUIT_INTERVAL;
2053           if ((*callback->poll_quit) != NULL
2054               && (*callback->poll_quit) (callback))
2055             {
2056               sim_stop (sd);
2057             }
2058         }
2059
2060 #ifndef ACE_FAST
2061       prevlock = thislock;
2062       thislock = 30;
2063       cycles++;
2064
2065       if (cycles >= doprofile)
2066         {
2067
2068           saved_state.asregs.cycles += doprofile;
2069           cycles -= doprofile;
2070           if (saved_state.asregs.profile_hist)
2071             {
2072               int n = PH2T (insn_ptr) >> PROFILE_SHIFT;
2073               if (n < nsamples)
2074                 {
2075                   int i = saved_state.asregs.profile_hist[n];
2076                   if (i < 65000)
2077                     saved_state.asregs.profile_hist[n] = i + 1;
2078                 }
2079
2080             }
2081         }
2082 #endif
2083     }
2084   if (saved_state.asregs.insn_end == loop.end)
2085     {
2086       saved_state.asregs.cregs.named.sr += SR_RC_INCREMENT;
2087       if (SR_RC)
2088         insn_ptr = loop.start;
2089       else
2090         {
2091           saved_state.asregs.insn_end = mem_end;
2092           loop.end = PT2H (0);
2093         }
2094       goto loop;
2095     }
2096
2097   if (saved_state.asregs.exception == SIGILL
2098       || saved_state.asregs.exception == SIGBUS)
2099     {
2100       insn_ptr -= 2;
2101     }
2102   /* Check for SIGBUS due to insn fetch.  */
2103   else if (! saved_state.asregs.exception)
2104     saved_state.asregs.exception = SIGBUS;
2105
2106   saved_state.asregs.ticks += get_now () - tick_start;
2107   saved_state.asregs.cycles += cycles;
2108   saved_state.asregs.stalls += stalls;
2109   saved_state.asregs.memstalls += memstalls;
2110   saved_state.asregs.insts += insts;
2111   saved_state.asregs.pc = PH2T (insn_ptr);
2112 #ifndef PR
2113   saved_state.asregs.sregs.named.pr = PR;
2114 #endif
2115
2116   saved_state.asregs.prevlock = prevlock;
2117   saved_state.asregs.thislock = thislock;
2118
2119   if (profile_file)
2120     {
2121       dump_profile ();
2122     }
2123
2124   signal (SIGFPE, prev_fpe);
2125   signal (SIGINT, prev);
2126 }
2127
2128 int
2129 sim_write (sd, addr, buffer, size)
2130      SIM_DESC sd;
2131      SIM_ADDR addr;
2132      unsigned char *buffer;
2133      int size;
2134 {
2135   int i;
2136
2137   init_pointers ();
2138
2139   for (i = 0; i < size; i++)
2140     {
2141       saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = buffer[i];
2142     }
2143   return size;
2144 }
2145
2146 int
2147 sim_read (sd, addr, buffer, size)
2148      SIM_DESC sd;
2149      SIM_ADDR addr;
2150      unsigned char *buffer;
2151      int size;
2152 {
2153   int i;
2154
2155   init_pointers ();
2156
2157   for (i = 0; i < size; i++)
2158     {
2159       buffer[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb];
2160     }
2161   return size;
2162 }
2163
2164 static int gdb_bank_number;
2165 enum {
2166   REGBANK_MACH = 15,
2167   REGBANK_IVN  = 16,
2168   REGBANK_PR   = 17,
2169   REGBANK_GBR  = 18,
2170   REGBANK_MACL = 19
2171 };
2172
2173 int
2174 sim_store_register (sd, rn, memory, length)
2175      SIM_DESC sd;
2176      int rn;
2177      unsigned char *memory;
2178      int length;
2179 {
2180   unsigned val;
2181
2182   init_pointers ();
2183   val = swap (* (int *) memory);
2184   switch (rn)
2185     {
2186     case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
2187     case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
2188     case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
2189     case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
2190     case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
2191     case SIM_SH_R15_REGNUM:
2192       saved_state.asregs.regs[rn] = val;
2193       break;
2194     case SIM_SH_PC_REGNUM:
2195       saved_state.asregs.pc = val;
2196       break;
2197     case SIM_SH_PR_REGNUM:
2198       PR = val;
2199       break;
2200     case SIM_SH_GBR_REGNUM:
2201       GBR = val;
2202       break;
2203     case SIM_SH_VBR_REGNUM:
2204       VBR = val;
2205       break;
2206     case SIM_SH_MACH_REGNUM:
2207       MACH = val;
2208       break;
2209     case SIM_SH_MACL_REGNUM:
2210       MACL = val;
2211       break;
2212     case SIM_SH_SR_REGNUM:
2213       SET_SR (val);
2214       break;
2215     case SIM_SH_FPUL_REGNUM:
2216       FPUL = val;
2217       break;
2218     case SIM_SH_FPSCR_REGNUM:
2219       SET_FPSCR (val);
2220       break;
2221     case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
2222     case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
2223     case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
2224     case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
2225     case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
2226     case SIM_SH_FR15_REGNUM:
2227       SET_FI (rn - SIM_SH_FR0_REGNUM, val);
2228       break;
2229     case SIM_SH_DSR_REGNUM:
2230       DSR = val;
2231       break;
2232     case SIM_SH_A0G_REGNUM:
2233       A0G = val;
2234       break;
2235     case SIM_SH_A0_REGNUM:
2236       A0 = val;
2237       break;
2238     case SIM_SH_A1G_REGNUM:
2239       A1G = val;
2240       break;
2241     case SIM_SH_A1_REGNUM:
2242       A1 = val;
2243       break;
2244     case SIM_SH_M0_REGNUM:
2245       M0 = val;
2246       break;
2247     case SIM_SH_M1_REGNUM:
2248       M1 = val;
2249       break;
2250     case SIM_SH_X0_REGNUM:
2251       X0 = val;
2252       break;
2253     case SIM_SH_X1_REGNUM:
2254       X1 = val;
2255       break;
2256     case SIM_SH_Y0_REGNUM:
2257       Y0 = val;
2258       break;
2259     case SIM_SH_Y1_REGNUM:
2260       Y1 = val;
2261       break;
2262     case SIM_SH_MOD_REGNUM:
2263       SET_MOD (val);
2264       break;
2265     case SIM_SH_RS_REGNUM:
2266       RS = val;
2267       break;
2268     case SIM_SH_RE_REGNUM:
2269       RE = val;
2270       break;
2271     case SIM_SH_SSR_REGNUM:
2272       SSR = val;
2273       break;
2274     case SIM_SH_SPC_REGNUM:
2275       SPC = val;
2276       break;
2277     /* The rn_bank idiosyncracies are not due to hardware differences, but to
2278        a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
2279     case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2280     case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2281     case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2282     case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2283       if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2284         {
2285           rn -= SIM_SH_R0_BANK0_REGNUM;
2286           saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val;
2287         }
2288       else
2289       if (SR_MD && SR_RB)
2290         Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val;
2291       else
2292         saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val;
2293       break;
2294     case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2295     case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2296     case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2297     case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2298       if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2299         {
2300           rn -= SIM_SH_R0_BANK1_REGNUM;
2301           saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val;
2302         }
2303       else
2304       if (SR_MD && SR_RB)
2305         saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val;
2306       else
2307         Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val;
2308       break;
2309     case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2310     case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2311     case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2312     case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2313       SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val);
2314       break;
2315     case SIM_SH_TBR_REGNUM:
2316       TBR = val;
2317       break;
2318     case SIM_SH_IBNR_REGNUM:
2319       IBNR = val;
2320       break;
2321     case SIM_SH_IBCR_REGNUM:
2322       IBCR = val;
2323       break;
2324     case SIM_SH_BANK_REGNUM:
2325       /* This is a pseudo-register maintained just for gdb.
2326          It tells us what register bank gdb would like to read/write.  */
2327       gdb_bank_number = val;
2328       break;
2329     case SIM_SH_BANK_MACL_REGNUM:
2330       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val;
2331       break;
2332     case SIM_SH_BANK_GBR_REGNUM:
2333       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val;
2334       break;
2335     case SIM_SH_BANK_PR_REGNUM:
2336       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val;
2337       break;
2338     case SIM_SH_BANK_IVN_REGNUM:
2339       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
2340       break;
2341     case SIM_SH_BANK_MACH_REGNUM:
2342       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
2343       break;
2344     default:
2345       return 0;
2346     }
2347   return -1;
2348 }
2349
2350 int
2351 sim_fetch_register (sd, rn, memory, length)
2352      SIM_DESC sd;
2353      int rn;
2354      unsigned char *memory;
2355      int length;
2356 {
2357   int val;
2358
2359   init_pointers ();
2360   switch (rn)
2361     {
2362     case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM:
2363     case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM:
2364     case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM:
2365     case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM:
2366     case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM:
2367     case SIM_SH_R15_REGNUM:
2368       val = saved_state.asregs.regs[rn];
2369       break;
2370     case SIM_SH_PC_REGNUM:
2371       val = saved_state.asregs.pc;
2372       break;
2373     case SIM_SH_PR_REGNUM:
2374       val = PR;
2375       break;
2376     case SIM_SH_GBR_REGNUM:
2377       val = GBR;
2378       break;
2379     case SIM_SH_VBR_REGNUM:
2380       val = VBR;
2381       break;
2382     case SIM_SH_MACH_REGNUM:
2383       val = MACH;
2384       break;
2385     case SIM_SH_MACL_REGNUM:
2386       val = MACL;
2387       break;
2388     case SIM_SH_SR_REGNUM:
2389       val = GET_SR ();
2390       break;
2391     case SIM_SH_FPUL_REGNUM:
2392       val = FPUL;
2393       break;
2394     case SIM_SH_FPSCR_REGNUM:
2395       val = GET_FPSCR ();
2396       break;
2397     case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM:
2398     case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM:
2399     case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM:
2400     case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM:
2401     case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM:
2402     case SIM_SH_FR15_REGNUM:
2403       val = FI (rn - SIM_SH_FR0_REGNUM);
2404       break;
2405     case SIM_SH_DSR_REGNUM:
2406       val = DSR;
2407       break;
2408     case SIM_SH_A0G_REGNUM:
2409       val = SEXT (A0G);
2410       break;
2411     case SIM_SH_A0_REGNUM:
2412       val = A0;
2413       break;
2414     case SIM_SH_A1G_REGNUM:
2415       val = SEXT (A1G);
2416       break;
2417     case SIM_SH_A1_REGNUM:
2418       val = A1;
2419       break;
2420     case SIM_SH_M0_REGNUM:
2421       val = M0;
2422       break;
2423     case SIM_SH_M1_REGNUM:
2424       val = M1;
2425       break;
2426     case SIM_SH_X0_REGNUM:
2427       val = X0;
2428       break;
2429     case SIM_SH_X1_REGNUM:
2430       val = X1;
2431       break;
2432     case SIM_SH_Y0_REGNUM:
2433       val = Y0;
2434       break;
2435     case SIM_SH_Y1_REGNUM:
2436       val = Y1;
2437       break;
2438     case SIM_SH_MOD_REGNUM:
2439       val = MOD;
2440       break;
2441     case SIM_SH_RS_REGNUM:
2442       val = RS;
2443       break;
2444     case SIM_SH_RE_REGNUM:
2445       val = RE;
2446       break;
2447     case SIM_SH_SSR_REGNUM:
2448       val = SSR;
2449       break;
2450     case SIM_SH_SPC_REGNUM:
2451       val = SPC;
2452       break;
2453     /* The rn_bank idiosyncracies are not due to hardware differences, but to
2454        a weird aliasing naming scheme for sh3 / sh3e / sh4.  */
2455     case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM:
2456     case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM:
2457     case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM:
2458     case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM:
2459       if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2460         {
2461           rn -= SIM_SH_R0_BANK0_REGNUM;
2462           val = saved_state.asregs.regstack[gdb_bank_number].regs[rn];
2463         }
2464       else
2465       val = (SR_MD && SR_RB
2466              ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM)
2467              : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]);
2468       break;
2469     case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM:
2470     case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM:
2471     case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM:
2472     case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM:
2473       if (saved_state.asregs.bfd_mach == bfd_mach_sh2a)
2474         {
2475           rn -= SIM_SH_R0_BANK1_REGNUM;
2476           val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8];
2477         }
2478       else
2479       val = (! SR_MD || ! SR_RB
2480              ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM)
2481              : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]);
2482       break;
2483     case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM:
2484     case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM:
2485     case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM:
2486     case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM:
2487       val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM);
2488       break;
2489     case SIM_SH_TBR_REGNUM:
2490       val = TBR;
2491       break;
2492     case SIM_SH_IBNR_REGNUM:
2493       val = IBNR;
2494       break;
2495     case SIM_SH_IBCR_REGNUM:
2496       val = IBCR;
2497       break;
2498     case SIM_SH_BANK_REGNUM:
2499       /* This is a pseudo-register maintained just for gdb.
2500          It tells us what register bank gdb would like to read/write.  */
2501       val = gdb_bank_number;
2502       break;
2503     case SIM_SH_BANK_MACL_REGNUM:
2504       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL];
2505       break;
2506     case SIM_SH_BANK_GBR_REGNUM:
2507       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR];
2508       break;
2509     case SIM_SH_BANK_PR_REGNUM:
2510       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR];
2511       break;
2512     case SIM_SH_BANK_IVN_REGNUM:
2513       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
2514       break;
2515     case SIM_SH_BANK_MACH_REGNUM:
2516       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
2517       break;
2518     default:
2519       return 0;
2520     }
2521   * (int *) memory = swap (val);
2522   return -1;
2523 }
2524
2525 int
2526 sim_trace (sd)
2527      SIM_DESC sd;
2528 {
2529   tracing = 1;
2530   sim_resume (sd, 0, 0);
2531   tracing = 0;
2532   return 1;
2533 }
2534
2535 void
2536 sim_stop_reason (sd, reason, sigrc)
2537      SIM_DESC sd;
2538      enum sim_stop *reason;
2539      int *sigrc;
2540 {
2541   /* The SH simulator uses SIGQUIT to indicate that the program has
2542      exited, so we must check for it here and translate it to exit.  */
2543   if (saved_state.asregs.exception == SIGQUIT)
2544     {
2545       *reason = sim_exited;
2546       *sigrc = saved_state.asregs.regs[5];
2547     }
2548   else
2549     {
2550       *reason = sim_stopped;
2551       *sigrc = saved_state.asregs.exception;
2552     }
2553 }
2554
2555 void
2556 sim_info (sd, verbose)
2557      SIM_DESC sd;
2558      int verbose;
2559 {
2560   double timetaken =
2561     (double) saved_state.asregs.ticks / (double) now_persec ();
2562   double virttime = saved_state.asregs.cycles / 36.0e6;
2563
2564   callback->printf_filtered (callback, "\n\n# instructions executed  %10d\n",
2565                              saved_state.asregs.insts);
2566   callback->printf_filtered (callback, "# cycles                 %10d\n",
2567                              saved_state.asregs.cycles);
2568   callback->printf_filtered (callback, "# pipeline stalls        %10d\n",
2569                              saved_state.asregs.stalls);
2570   callback->printf_filtered (callback, "# misaligned load/store  %10d\n",
2571                              saved_state.asregs.memstalls);
2572   callback->printf_filtered (callback, "# real time taken        %10.4f\n",
2573                              timetaken);
2574   callback->printf_filtered (callback, "# virtual time taken     %10.4f\n",
2575                              virttime);
2576   callback->printf_filtered (callback, "# profiling size         %10d\n",
2577                              sim_profile_size);
2578   callback->printf_filtered (callback, "# profiling frequency    %10d\n",
2579                              saved_state.asregs.profile);
2580   callback->printf_filtered (callback, "# profile maxpc          %10x\n",
2581                              (1 << sim_profile_size) << PROFILE_SHIFT);
2582
2583   if (timetaken != 0)
2584     {
2585       callback->printf_filtered (callback, "# cycles/second          %10d\n",
2586                                  (int) (saved_state.asregs.cycles / timetaken));
2587       callback->printf_filtered (callback, "# simulation ratio       %10.4f\n",
2588                                  virttime / timetaken);
2589     }
2590 }
2591
2592 void
2593 sim_set_profile (n)
2594      int n;
2595 {
2596   saved_state.asregs.profile = n;
2597 }
2598
2599 void
2600 sim_set_profile_size (n)
2601      int n;
2602 {
2603   sim_profile_size = n;
2604 }
2605
2606 SIM_DESC
2607 sim_open (kind, cb, abfd, argv)
2608      SIM_OPEN_KIND kind;
2609      host_callback *cb;
2610      struct bfd *abfd;
2611      char **argv;
2612 {
2613   char **p;
2614   int endian_set = 0;
2615   int i;
2616   union
2617     {
2618       int i;
2619       short s[2];
2620       char c[4];
2621     }
2622   mem_word;
2623
2624   sim_kind = kind;
2625   myname = argv[0];
2626   callback = cb;
2627
2628   for (p = argv + 1; *p != NULL; ++p)
2629     {
2630       if (strcmp (*p, "-E") == 0)
2631         {
2632           ++p;
2633           if (*p == NULL)
2634             {
2635               /* FIXME: This doesn't use stderr, but then the rest of the
2636                  file doesn't either.  */
2637               callback->printf_filtered (callback, "Missing argument to `-E'.\n");
2638               return 0;
2639             }
2640           target_little_endian = strcmp (*p, "big") != 0;
2641           endian_set = 1;
2642         }
2643       else if (isdigit (**p))
2644         parse_and_set_memory_size (*p);
2645     }
2646
2647   if (abfd != NULL && ! endian_set)
2648       target_little_endian = ! bfd_big_endian (abfd);
2649
2650   if (abfd)
2651     init_dsp (abfd);
2652
2653   for (i = 4; (i -= 2) >= 0; )
2654     mem_word.s[i >> 1] = i;
2655   global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff;
2656
2657   for (i = 4; --i >= 0; )
2658     mem_word.c[i] = i;
2659   endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff;
2660
2661   /* fudge our descriptor for now */
2662   return (SIM_DESC) 1;
2663 }
2664
2665 static void
2666 parse_and_set_memory_size (str)
2667      char *str;
2668 {
2669   int n;
2670
2671   n = strtol (str, NULL, 10);
2672   if (n > 0 && n <= 24)
2673     sim_memory_size = n;
2674   else
2675     callback->printf_filtered (callback, "Bad memory size %d; must be 1 to 24, inclusive\n", n);
2676 }
2677
2678 void
2679 sim_close (sd, quitting)
2680      SIM_DESC sd;
2681      int quitting;
2682 {
2683   /* nothing to do */
2684 }
2685
2686 SIM_RC
2687 sim_load (sd, prog, abfd, from_tty)
2688      SIM_DESC sd;
2689      char *prog;
2690      bfd *abfd;
2691      int from_tty;
2692 {
2693   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
2694   bfd *prog_bfd;
2695
2696   prog_bfd = sim_load_file (sd, myname, callback, prog, abfd,
2697                             sim_kind == SIM_OPEN_DEBUG,
2698                             0, sim_write);
2699
2700   /* Set the bfd machine type.  */
2701   if (prog_bfd)
2702     saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
2703   else if (abfd)
2704     saved_state.asregs.bfd_mach = bfd_get_mach (abfd);
2705   else
2706     saved_state.asregs.bfd_mach = 0;
2707
2708   if (prog_bfd == NULL)
2709     return SIM_RC_FAIL;
2710   if (abfd == NULL)
2711     bfd_close (prog_bfd);
2712   return SIM_RC_OK;
2713 }
2714
2715 SIM_RC
2716 sim_create_inferior (sd, prog_bfd, argv, env)
2717      SIM_DESC sd;
2718      struct bfd *prog_bfd;
2719      char **argv;
2720      char **env;
2721 {
2722   /* Clear the registers. */
2723   memset (&saved_state, 0,
2724           (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state);
2725
2726   /* Set the PC.  */
2727   if (prog_bfd != NULL)
2728     saved_state.asregs.pc = bfd_get_start_address (prog_bfd);
2729
2730   /* Set the bfd machine type.  */
2731   if (prog_bfd != NULL)
2732     saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd);
2733
2734   /* Record the program's arguments. */
2735   prog_argv = argv;
2736
2737   return SIM_RC_OK;
2738 }
2739
2740 void
2741 sim_do_command (sd, cmd)
2742      SIM_DESC sd;
2743      char *cmd;
2744 {
2745   char *sms_cmd = "set-memory-size";
2746   int cmdsize;
2747
2748   if (cmd == NULL || *cmd == '\0')
2749     {
2750       cmd = "help";
2751     }
2752
2753   cmdsize = strlen (sms_cmd);
2754   if (strncmp (cmd, sms_cmd, cmdsize) == 0
2755       && strchr (" \t", cmd[cmdsize]) != NULL)
2756     {
2757       parse_and_set_memory_size (cmd + cmdsize + 1);
2758     }
2759   else if (strcmp (cmd, "help") == 0)
2760     {
2761       (callback->printf_filtered) (callback,
2762                                    "List of SH simulator commands:\n\n");
2763       (callback->printf_filtered) (callback, "set-memory-size <n> -- Set the number of address bits to use\n");
2764       (callback->printf_filtered) (callback, "\n");
2765     }
2766   else
2767     {
2768       (callback->printf_filtered) (callback, "Error: \"%s\" is not a valid SH simulator command.\n", cmd);
2769     }
2770 }
2771
2772 void
2773 sim_set_callbacks (p)
2774      host_callback *p;
2775 {
2776   callback = p;
2777 }