1 .\" $NetBSD: ioasic.9,v 1.9 2005/12/26 19:48:12 perry Exp $
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35 .Nm ioasic_intr_establish ,
36 .Nm ioasic_intr_disestablish ,
37 .Nm ioasic_intr_evcnt ,
38 .Nm ioasic_attach_devs ,
40 .Nd baseboard I/O control ASIC for DEC TURBOchannel systems
44 .In dev/tc/ioasicreg.h
45 .In dev/tc/ioasicvar.h
47 .Fn ioasic_intr_establish "struct device *dev" "void *cookie" "int level" \
48 "int (*handler)(void *)" "void *arg"
50 .Fn ioasic_intr_disestablish "struct device *dev" "void *cookie"
51 .Ft const struct evcnt *
52 .Fn ioasic_intr_evcnt "struct device *dev" "void *cookie"
54 .Fn ioasic_attach_devs "struct ioasic_softc *sc" \
55 "struct ioasic_dev *ioasic_devs" "int ioasic_ndevs"
57 .Fn ioasic_submatch "struct cfdata *match" "struct ioasicdev_attach_args *ia"
61 device provides support for the DEC proprietary IOCTL ASIC found on
62 all DEC TURBOchannel machines with MIPS (DECstation 5000 series,
63 excluding the 5000/200) and Alpha (3000-series) systems.
66 is memory-mapped into the TURBOchannel system slot to interface up to
68 It connects the TURBOchannel to a 16-bit wide I/O bus and supplies
69 various control signals to the devices that share this bus.
73 provides hardware DMA channels and interrupt support.
74 DMA transfers are between one and four 32-bit words (16 bytes) in
75 length, depending on the device.
78 stores the data in internal data registers.
79 The data is transferred to and from the registers in 16-bit words
81 Various interrupts are signalled on DMA pointer-related conditions.
83 Drivers for devices attached to the
85 will make use of the following data types:
86 .Bl -tag -width compact
87 .It Fa struct ioasicdev_attach_args
88 A structure used to inform the driver of the
91 It contains the following members:
94 tc_offset_t iada_offset
98 .It Fa struct ioasic_softc
99 The parent structure which contains at the following members which are
102 bus_space_tag_t sc_bst;
103 bus_space_handle_t sc_bsh;
104 bus_dma_tag_t sc_dmat;
106 .It Fa struct ioasic_dev
107 A structure describing the machine-dependent devices attached to the
109 containing the following members:
112 tc_offset_t iad_offset;
114 uint32_t iad_intrbits;
118 .Bl -tag -width compact
119 .It Fn ioasic_intr_establish "dev" "cookie" "level" "handler" "arg"
120 Establish an interrupt handler with device
122 for the interrupt described completely by
124 The priority of the interrupt is specified by
126 When the interrupt occurs the function
128 is called with argument
130 .It Fn ioasic_intr_disestablish "dev" "cookie"
131 Dis-establish the interrupt handler with device
133 for the interrupt described complete ly
135 .It Fn ioasic_intr_evcnt "dev" "cookie"
136 Do interrupt event counting with device
138 for the event described completely by
140 .It Fn ioasic_attach_devs "sc" "ioasic_devs" "ioasic_ndevs"
141 Configure each of the
145 .It Fn ioasic_submatch "match" "ia"
146 Check that the device offset is not OASIC_OFFSET_UNKNOWN.
150 .Fn ioasic_intr_establish ,
151 .Fn ioasic_intr_disestablish ,
153 .Fn ioasic_intr_evcnt
154 functions are likely to used by all
158 .Fn ioasic_attach_devs
159 function is used by ioasic driver internally and is of interest to
160 driver writers because it must be aware of your device for it to be
161 found during autoconfiguration.
162 .Sh AUTOCONFIGURATION
163 The IOASIC is a direct-connection bus.
164 During autoconfiguration, machine-dependent code will provide an array of
165 .Fa struct ioasic_devs
166 describing devices attached to the
168 to be used by the ioasic driver.
169 The ioasic driver will pass this array to
170 .Fn ioasic_attach_devs
171 to attach the drivers with the devices.
173 Drivers match the device using
176 During attach, all drivers should use the parent's bus_space and
177 bus_dma resources, and map the appropriate bus_space region using
178 .Fn bus_space_subregion
182 No additional support is provided for
184 DMA beyond the facilities provided by the
190 provides two pairs of DMA address pointers (transmitting and
191 receiving) for each DMA-capable device.
192 The pair of address pointers point to consecutive (but not necessarily
193 contiguous) DMA blocks of size IOASIC_DMA_BLOCKSIZE.
194 Upon successful transfer of the first block, DMA continues to the next
195 block and an interrupt is posted to signal an address pointer update.
196 DMA transfers are enabled and disabled by bits inside the
198 status (CSR) register.
200 The interrupt handler must update the address pointers to point to the
201 next block in the DMA transfer.
202 The address pointer update must be completed before the completion of
203 the second DMA block, otherwise a DMA overrun error condition will occur.
205 This section describes places within the
207 source tree where actual code implementing or using the
208 machine-independent IOASIC subsystem can be found.
209 All pathnames are relative to
212 The IOASIC subsystem itself is implemented within the file
213 .Pa sys/dev/tc/ioasic_subr.c .
214 Machine-dependent portions can be found in
215 .Pa sys/arch/\*[Lt]arch\*[Gt]/tc/ioasic.c .