sys/arch/acorn26/include/fpureg.h

   1 /*      $NetBSD: fpureg.h,v 1.1 2000/12/23 13:37:03 bjh21 Exp $ */
   2
   3 /*
   4  * ARM FPU definitions
   5  */
   6
   7 /* System ID byte */
   8 #define FPSR_SYSID_MASK         0xff000000
   9 #define FPSR_SYSID_FPPC         0x80000000
  10 #define FPSR_SYSID_FPA          0x81000000
  11
  12 /* Trap enable bits */
  13 #define FPSR_TE_IVO             0x00010000 /* InValid Operation */
  14 #define FPSR_TE_DVZ             0x00020000 /* DiVision by Zero */
  15 #define FPSR_TE_OFL             0x00040000 /* OverFLow */
  16 #define FPSR_TE_UFL             0x00080000 /* UnderFLow */
  17 #define FPSR_TE_INX             0x00100000 /* INeXact */
  18
  19 /* System control byte (FPA only) */
  20 #define FPSR_CTL_ND             0x00000100 /* No Denormalised numbers */
  21 #define FPSR_CTL_NE             0x00000200 /* NaN Exception */
  22 #define FPSR_CTL_SO             0x00000400 /* Synchronous Operation */
  23 #define FPSR_CTL_EP             0x00000800 /* Expanded Packed decimal */
  24 #define FPSR_CTL_AC             0x00001000 /* Alternative C flag */
  25
  26 /* Cumulative exception bits */
  27 #define FPSR_EX_IVO             0x00000001 /* InValid Operation */
  28 #define FPSR_EX_DVZ             0x00000002 /* DiVision by Zero */
  29 #define FPSR_EX_OFL             0x00000004 /* OverFLow */
  30 #define FPSR_EX_UFL             0x00000008 /* UnderFLow */
  31 #define FPSR_EX_INX             0x00000010 /* INeXact */
  32
  33 /*
  34  * FPPC FPCR
  35  */
  36 #define FPPC_FPCR_DA    0x00000001 /* Disable */
  37 #define FPPC_FPCR_EX    0x00000002 /* FP exception occurred */
  38 #define FPPC_FPCR_AS    0x00000004 /* Last exception was async */
  39 #define FPPC_FPCR_SBM   0x00000010 /* Use supervisor bank 'm' */
  40 #define FPPC_FPCR_SBN   0x00000020 /* Use supervisor bank 'n' */
  41 #define FPPC_FPCR_SBD   0x00000040 /* Use supervisor bank 'd' */
  42 #define FPPC_FPCR_PR    0x00000080 /* Last RMF gave partial remainder */
  43
  44 /*
  45  * FPA FPCR
  46  * This is provisional, from the RISC OS 3 PRM
  47  */
  48 #define FPA_FPCR_S2     0x0000000f /* AU source register 2 */
  49 #define FPA_FPCR_OP     0x00f08010 /* AU operation code */
  50 #define FPA_FPCR_RM     0x00000060 /* AU rounding mode */
  51 #define FPA_FPCR_PR     0x00080080 /* AU precision */
  52 #define FPA_FPCR_EN     0x00000100 /* Enable FPA */
  53 #define FPA_FPCR_RE     0x00000200 /* Rounding exception */
  54 #define FPA_FPCR_AB     0x00000400 /* Asynchronous bounce */
  55 #define FPA_FPCR_SB     0x00000800 /* Synchronous bounce */
  56 #define FPA_FPCR_DS     0x00007000 /* AU destination register */
  57 #define FPA_FPCR_S1     0x00070000 /* AU source register 1 */
  58 #define FPA_FPCR_EO     0x04000000 /* Exponent overflow */
  59 #define FPA_FPCR_MO     0x08000000 /* Mantissa overflow */
  60 #define FPA_FPCR_IE     0x10000000 /* Inexact bit */
  61 #define FPA_FPCR_RU     0x80000000 /* Rounded up bit */