sys/arch/acorn26/vidc/vidcreg.h

   1 /* $NetBSD: vidcreg.h,v 1.1 2002/03/24 15:47:30 bjh21 Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1998, 2001 Ben Harris
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the author may not be used to endorse or promote products
  16  *    derived from this software without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  */
  29 /*
  30  * vidcreg.h - Acorn/ARM VIDC (Arabella) registers
  31  */
  32
  33 #ifndef _ARM26_VIDCREG_H
  34 #define _ARM26_VIDCREG_H
  35
  36 /*
  37  * The VIDC is accessed by writing words to addresses starting at
  38  * MEMC_VIDC_BASE definied in memcreg.h.
  39  *
  40  * As with the MEMC, the value is the logical OR of the register
  41  * specifier and the new value.
  42  */
  43
  44 /* Palette entries */
  45
  46 #define VIDC_PALETTE            0x00000000
  47 #define VIDC_PALETTE_LCOL(n)    (n << 26)
  48 #define VIDC_PALETTE_BCOL       0x40000000
  49 #define VIDC_PALETTE_CCOL(n)    (0x40000000 + (n << 26))
  50
  51 #define VIDC_PALETTE_ENTRY(r, g, b, s)  ((s != 0) << 12 | b << 8 | g << 4 | r)
  52
  53 /* Stereo image registers */
  54 /* They're in the order 70123456 */
  55 #define VIDC_SIR(n)             (0x60000000 + ((n + 1) % 8 << 26))
  56 #define VIDC_STEREO_L100        1
  57 #define VIDC_STEREO_L83         2
  58 #define VIDC_STEREO_L67         3
  59 #define VIDC_STEREO_C           4
  60 #define VIDC_STEREO_R67         5
  61 #define VIDC_STEREO_R83         6
  62 #define VIDC_STEREO_R100        7
  63
  64 /* Video timing register */
  65 #define VIDC_HCR                0x80000000
  66 #define VIDC_HSWR               0x84000000
  67 #define VIDC_HBSR               0x88000000
  68 #define VIDC_HDSR               0x8c000000
  69 #define VIDC_HDER               0x90000000
  70 #define VIDC_HBER               0x94000000
  71 #define VIDC_HCSR               0x98000000
  72 #define VIDC_HIR                0x9c000000
  73
  74 #define VIDC_VCR                0xa0000000
  75 #define VIDC_VSWR               0xa4000000
  76 #define VIDC_VBSR               0xa8000000
  77 #define VIDC_VDSR               0xac000000
  78 #define VIDC_VDER               0xb0000000
  79 #define VIDC_VBER               0xb4000000
  80 #define VIDC_VCSR               0xb8000000
  81 #define VIDC_VCER               0xbc000000
  82
  83 /*
  84  * Horizontal timings have units of two pixels (except HCSR).
  85  * Vertical timings have units of a raster.  Most have to have one or
  86  * two subtracted from them.
  87  */
  88 #define VIDC_VIDTIMING(x)       (x << 14)
  89 #define VIDC_HCS(x)             (x << 13)
  90 #define VIDC_HCS_HIRES(x)       (x << 11)
  91
  92 /* Sound frequency register */
  93 #define VIDC_SFR                0xc0000000
  94 /* Units are us */
  95 #define VIDC_SF(x)              (x & 0x100)
  96
  97 /* Control register */
  98 #define VIDC_CONTROL            0xe0000000
  99
 100 #define VIDC_CTL_DOTCLOCK_MASK  0x00000003
 101 #define VIDC_CTL_DOTCLOCK_8MHZ  0x00000000
 102 #define VIDC_CTL_DOTCLOCK_12MHZ 0x00000001
 103 #define VIDC_CTL_DOTCLOCK_16MHZ 0x00000002
 104 #define VIDC_CTL_DOTCLOCK_24MHZ 0x00000003
 105
 106 #define VIDC_CTL_BPP_MASK       0x0000000c
 107 #define VIDC_CTL_BPP_ONE        0x00000000
 108 #define VIDC_CTL_BPP_TWO        0x00000004
 109 #define VIDC_CTL_BPP_FOUR       0x00000008
 110 #define VIDC_CTL_BPP_EIGHT      0x0000000c
 111
 112 #define VIDC_CTL_DMARQ_MASK     0x00000030
 113 #define VIDC_CTL_DMARQ_04       0x00000000
 114 #define VIDC_CTL_DMARQ_15       0x00000010
 115 #define VIDC_CTL_DMARQ_26       0x00000020
 116 #define VIDC_CTL_DMARQ_37       0x00000030
 117
 118 #define VIDC_CTL_INTERLACE      0x00000040
 119
 120 #define VIDC_CTL_CSYNC          0x00000080
 121
 122 #define VIDC_CTL_TEST_MASK      0x0000c100
 123 #define VIDC_CTL_TEST_OFF       0x00000000
 124 #define VIDC_CTL_TEST_MODE0     0x00004000
 125 #define VIDC_CTL_TEST_MODE1     0x00008000
 126 #define VIDC_CTL_TEST_MODE2     0x0000c000
 127 #define VIDC_CTL_TEST_MODE3     0x00000100
 128
 129 #define VIDC_WRITE(value)       *(volatile u_int32_t *)MEMC_VIDC_BASE = value
 130
 131 /*
 132  * VIDC audio format is mu-law, but with the bits in a strange order.
 133  *
 134  * VIDC1 has:
 135  * D[7]   sign
 136  * D[6:4] chord select
 137  * D[3:0] point on chord
 138  * so 0x00 -> +0, 0x7f -> +inf, 0x80 -> -0, 0xff -> -inf
 139  *
 140  * VIDC2 has:
 141  * D[7:5] chord select
 142  * D[4:1] point on chord
 143  * D[0]   sign
 144  * so 0x00 -> +0, 0xfe -> +inf, 0x01 -> -0, 0xff -> -inf
 145  *
 146  * Normal mu-law appears to have:
 147  * 0x00 -> -inf, 0x7f -> -0, 0x80 -> +inf, 0xff -> +0
 148  * Thus VIDC1 is NOT(mu-law), while VIDC2 is NOT(mu-law)<<1 | NOT(mu-law)>>7.
 149  *
 150  * I think the A500 uses VIDC1 and the Archimedes uses VIDC2.
 151  */
 152
 153 #endif