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[netbsd-mini2440.git] / sys / arch / algor / pci / pci_alignstride_bus_io_chipdep.c
blobd5a4fb46227bb41cb14c5e0c8b309e99cfe304c2
1 /* $NetBSD: pci_alignstride_bus_io_chipdep.c,v 1.8 2008/04/28 20:23:10 martin Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
35 * All rights reserved.
36 *
37 * Author: Chris G. Demetriou
38 *
39 * Permission to use, copy, modify and distribute this software and
40 * its documentation is hereby granted, provided that both the copyright
41 * notice and this permission notice appear in all copies of the
42 * software, derivative works or modified versions, and any portions
43 * thereof, and that both notices appear in supporting documentation.
44 *
45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
48 *
49 * Carnegie Mellon requests users of this software to return to
50 *
51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
52 * School of Computer Science
53 * Carnegie Mellon University
54 * Pittsburgh PA 15213-3890
55 *
56 * any improvements or extensions that they make and grant Carnegie the
57 * rights to redistribute these changes.
58 */
59
60 /*
61 * Common PCI Chipset "bus I/O" functions, for chipsets which have to
62 * deal with only a single PCI interface chip in a machine.
63 *
64 * uses:
65 * CHIP name of the 'chip' it's being compiled for.
66 * CHIP_IO_BASE Sparse I/O space base to use.
67 * CHIP_IO_EX_STORE
68 * If defined, device-provided static storage area
69 * for the I/O space extent. If this is defined,
70 * CHIP_IO_EX_STORE_SIZE must also be defined. If
71 * this is not defined, a static area will be
72 * declared.
73 * CHIP_IO_EX_STORE_SIZE
74 * Size of the device-provided static storage area
75 * for the I/O memory space extent.
76 */
77
78 #include <sys/cdefs.h>
79 __KERNEL_RCSID(1, "$NetBSD: pci_alignstride_bus_io_chipdep.c,v 1.8 2008/04/28 20:23:10 martin Exp $");
80
81 #include <sys/extent.h>
82
83 #define __C(A,B) __CONCAT(A,B)
84 #define __S(S) __STRING(S)
85
86 /* mapping/unmapping */
87 int __C(CHIP,_io_map)(void *, bus_addr_t, bus_size_t, int,
88 bus_space_handle_t *, int);
89 void __C(CHIP,_io_unmap)(void *, bus_space_handle_t,
90 bus_size_t, int);
91 int __C(CHIP,_io_subregion)(void *, bus_space_handle_t,
92 bus_size_t, bus_size_t, bus_space_handle_t *);
93
94 int __C(CHIP,_io_translate)(void *, bus_addr_t, bus_size_t,
95 int, struct mips_bus_space_translation *);
96 int __C(CHIP,_io_get_window)(void *, int,
97 struct mips_bus_space_translation *);
98
99 /* allocation/deallocation */
100 int __C(CHIP,_io_alloc)(void *, bus_addr_t, bus_addr_t,
101 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
102 bus_space_handle_t *);
103 void __C(CHIP,_io_free)(void *, bus_space_handle_t,
104 bus_size_t);
105
106 /* get kernel virtual address */
107 void * __C(CHIP,_io_vaddr)(void *, bus_space_handle_t);
108
109 /* mmap for user */
110 paddr_t __C(CHIP,_io_mmap)(void *, bus_addr_t, off_t, int, int);
111
112 /* barrier */
113 inline void __C(CHIP,_io_barrier)(void *, bus_space_handle_t,
114 bus_size_t, bus_size_t, int);
115
116 /* read (single) */
117 inline u_int8_t __C(CHIP,_io_read_1)(void *, bus_space_handle_t,
118 bus_size_t);
119 inline u_int16_t __C(CHIP,_io_read_2)(void *, bus_space_handle_t,
120 bus_size_t);
121 inline u_int32_t __C(CHIP,_io_read_4)(void *, bus_space_handle_t,
122 bus_size_t);
123 inline u_int64_t __C(CHIP,_io_read_8)(void *, bus_space_handle_t,
124 bus_size_t);
125
126 /* read multiple */
127 void __C(CHIP,_io_read_multi_1)(void *, bus_space_handle_t,
128 bus_size_t, u_int8_t *, bus_size_t);
129 void __C(CHIP,_io_read_multi_2)(void *, bus_space_handle_t,
130 bus_size_t, u_int16_t *, bus_size_t);
131 void __C(CHIP,_io_read_multi_4)(void *, bus_space_handle_t,
132 bus_size_t, u_int32_t *, bus_size_t);
133 void __C(CHIP,_io_read_multi_8)(void *, bus_space_handle_t,
134 bus_size_t, u_int64_t *, bus_size_t);
135
136 /* read region */
137 void __C(CHIP,_io_read_region_1)(void *, bus_space_handle_t,
138 bus_size_t, u_int8_t *, bus_size_t);
139 void __C(CHIP,_io_read_region_2)(void *, bus_space_handle_t,
140 bus_size_t, u_int16_t *, bus_size_t);
141 void __C(CHIP,_io_read_region_4)(void *, bus_space_handle_t,
142 bus_size_t, u_int32_t *, bus_size_t);
143 void __C(CHIP,_io_read_region_8)(void *, bus_space_handle_t,
144 bus_size_t, u_int64_t *, bus_size_t);
145
146 /* write (single) */
147 inline void __C(CHIP,_io_write_1)(void *, bus_space_handle_t,
148 bus_size_t, u_int8_t);
149 inline void __C(CHIP,_io_write_2)(void *, bus_space_handle_t,
150 bus_size_t, u_int16_t);
151 inline void __C(CHIP,_io_write_4)(void *, bus_space_handle_t,
152 bus_size_t, u_int32_t);
153 inline void __C(CHIP,_io_write_8)(void *, bus_space_handle_t,
154 bus_size_t, u_int64_t);
155
156 /* write multiple */
157 void __C(CHIP,_io_write_multi_1)(void *, bus_space_handle_t,
158 bus_size_t, const u_int8_t *, bus_size_t);
159 void __C(CHIP,_io_write_multi_2)(void *, bus_space_handle_t,
160 bus_size_t, const u_int16_t *, bus_size_t);
161 void __C(CHIP,_io_write_multi_4)(void *, bus_space_handle_t,
162 bus_size_t, const u_int32_t *, bus_size_t);
163 void __C(CHIP,_io_write_multi_8)(void *, bus_space_handle_t,
164 bus_size_t, const u_int64_t *, bus_size_t);
165
166 /* write region */
167 void __C(CHIP,_io_write_region_1)(void *, bus_space_handle_t,
168 bus_size_t, const u_int8_t *, bus_size_t);
169 void __C(CHIP,_io_write_region_2)(void *, bus_space_handle_t,
170 bus_size_t, const u_int16_t *, bus_size_t);
171 void __C(CHIP,_io_write_region_4)(void *, bus_space_handle_t,
172 bus_size_t, const u_int32_t *, bus_size_t);
173 void __C(CHIP,_io_write_region_8)(void *, bus_space_handle_t,
174 bus_size_t, const u_int64_t *, bus_size_t);
175
176 /* set multiple */
177 void __C(CHIP,_io_set_multi_1)(void *, bus_space_handle_t,
178 bus_size_t, u_int8_t, bus_size_t);
179 void __C(CHIP,_io_set_multi_2)(void *, bus_space_handle_t,
180 bus_size_t, u_int16_t, bus_size_t);
181 void __C(CHIP,_io_set_multi_4)(void *, bus_space_handle_t,
182 bus_size_t, u_int32_t, bus_size_t);
183 void __C(CHIP,_io_set_multi_8)(void *, bus_space_handle_t,
184 bus_size_t, u_int64_t, bus_size_t);
185
186 /* set region */
187 void __C(CHIP,_io_set_region_1)(void *, bus_space_handle_t,
188 bus_size_t, u_int8_t, bus_size_t);
189 void __C(CHIP,_io_set_region_2)(void *, bus_space_handle_t,
190 bus_size_t, u_int16_t, bus_size_t);
191 void __C(CHIP,_io_set_region_4)(void *, bus_space_handle_t,
192 bus_size_t, u_int32_t, bus_size_t);
193 void __C(CHIP,_io_set_region_8)(void *, bus_space_handle_t,
194 bus_size_t, u_int64_t, bus_size_t);
195
196 /* copy */
197 void __C(CHIP,_io_copy_region_1)(void *, bus_space_handle_t,
198 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
199 void __C(CHIP,_io_copy_region_2)(void *, bus_space_handle_t,
200 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
201 void __C(CHIP,_io_copy_region_4)(void *, bus_space_handle_t,
202 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
203 void __C(CHIP,_io_copy_region_8)(void *, bus_space_handle_t,
204 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t);
205
206 #ifdef CHIP_IO_EXTENT
207 #ifndef CHIP_IO_EX_STORE
208 static long
209 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)];
210 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage))
211 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage))
212 #endif
213 #endif /* CHIP_IO_EXTENT */
214
215 #ifndef CHIP_ALIGN_STRIDE
216 #define CHIP_ALIGN_STRIDE 0
217 #endif
218
219 void
220 __C(CHIP,_bus_io_init)(t, v)
221 bus_space_tag_t t;
222 void *v;
223 {
224 #ifdef CHIP_IO_EXTENT
225 struct extent *ex;
226 #endif
227
228 /*
229 * Initialize the bus space tag.
230 */
231
232 /* cookie */
233 t->bs_cookie = v;
234
235 /* mapping/unmapping */
236 t->bs_map = __C(CHIP,_io_map);
237 t->bs_unmap = __C(CHIP,_io_unmap);
238 t->bs_subregion = __C(CHIP,_io_subregion);
239
240 t->bs_translate = __C(CHIP,_io_translate);
241 t->bs_get_window = __C(CHIP,_io_get_window);
242
243 /* allocation/deallocation */
244 t->bs_alloc = __C(CHIP,_io_alloc);
245 t->bs_free = __C(CHIP,_io_free);
246
247 /* get kernel virtual address */
248 t->bs_vaddr = __C(CHIP,_io_vaddr);
249
250 /* mmap for user */
251 t->bs_mmap = __C(CHIP,_io_mmap);
252
253 /* barrier */
254 t->bs_barrier = __C(CHIP,_io_barrier);
255
256 /* read (single) */
257 t->bs_r_1 = __C(CHIP,_io_read_1);
258 t->bs_r_2 = __C(CHIP,_io_read_2);
259 t->bs_r_4 = __C(CHIP,_io_read_4);
260 t->bs_r_8 = __C(CHIP,_io_read_8);
261
262 /* read multiple */
263 t->bs_rm_1 = __C(CHIP,_io_read_multi_1);
264 t->bs_rm_2 = __C(CHIP,_io_read_multi_2);
265 t->bs_rm_4 = __C(CHIP,_io_read_multi_4);
266 t->bs_rm_8 = __C(CHIP,_io_read_multi_8);
267
268 /* read region */
269 t->bs_rr_1 = __C(CHIP,_io_read_region_1);
270 t->bs_rr_2 = __C(CHIP,_io_read_region_2);
271 t->bs_rr_4 = __C(CHIP,_io_read_region_4);
272 t->bs_rr_8 = __C(CHIP,_io_read_region_8);
273
274 /* write (single) */
275 t->bs_w_1 = __C(CHIP,_io_write_1);
276 t->bs_w_2 = __C(CHIP,_io_write_2);
277 t->bs_w_4 = __C(CHIP,_io_write_4);
278 t->bs_w_8 = __C(CHIP,_io_write_8);
279
280 /* write multiple */
281 t->bs_wm_1 = __C(CHIP,_io_write_multi_1);
282 t->bs_wm_2 = __C(CHIP,_io_write_multi_2);
283 t->bs_wm_4 = __C(CHIP,_io_write_multi_4);
284 t->bs_wm_8 = __C(CHIP,_io_write_multi_8);
285
286 /* write region */
287 t->bs_wr_1 = __C(CHIP,_io_write_region_1);
288 t->bs_wr_2 = __C(CHIP,_io_write_region_2);
289 t->bs_wr_4 = __C(CHIP,_io_write_region_4);
290 t->bs_wr_8 = __C(CHIP,_io_write_region_8);
291
292 /* set multiple */
293 t->bs_sm_1 = __C(CHIP,_io_set_multi_1);
294 t->bs_sm_2 = __C(CHIP,_io_set_multi_2);
295 t->bs_sm_4 = __C(CHIP,_io_set_multi_4);
296 t->bs_sm_8 = __C(CHIP,_io_set_multi_8);
297
298 /* set region */
299 t->bs_sr_1 = __C(CHIP,_io_set_region_1);
300 t->bs_sr_2 = __C(CHIP,_io_set_region_2);
301 t->bs_sr_4 = __C(CHIP,_io_set_region_4);
302 t->bs_sr_8 = __C(CHIP,_io_set_region_8);
303
304 /* copy */
305 t->bs_c_1 = __C(CHIP,_io_copy_region_1);
306 t->bs_c_2 = __C(CHIP,_io_copy_region_2);
307 t->bs_c_4 = __C(CHIP,_io_copy_region_4);
308 t->bs_c_8 = __C(CHIP,_io_copy_region_8);
309
310 #ifdef CHIP_IO_EXTENT
311 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */
312 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL,
313 M_DEVBUF, (void *)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v),
314 EX_NOWAIT);
315 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT);
316
317 #ifdef CHIP_IO_W1_BUS_START
318 /*
319 * The window may be disabled. We notice this by seeing
320 * -1 as the bus base address.
321 */
322 if (CHIP_IO_W1_BUS_START(v) == (bus_addr_t) -1) {
323 #ifdef EXTENT_DEBUG
324 printf("io: this space is disabled\n");
325 #endif
326 return;
327 }
328
329 #ifdef EXTENT_DEBUG
330 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v),
331 CHIP_IO_W1_BUS_END(v));
332 #endif
333 extent_free(ex, CHIP_IO_W1_BUS_START(v),
334 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT);
335 #endif
336 #ifdef CHIP_IO_W2_BUS_START
337 #ifdef EXTENT_DEBUG
338 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v),
339 CHIP_IO_W2_BUS_END(v));
340 #endif
341 extent_free(ex, CHIP_IO_W2_BUS_START(v),
342 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT);
343 #endif
344
345 #ifdef EXTENT_DEBUG
346 extent_print(ex);
347 #endif
348 CHIP_IO_EXTENT(v) = ex;
349 #endif /* CHIP_IO_EXTENT */
350 }
351
352 int
353 __C(CHIP,_io_translate)(v, ioaddr, iolen, flags, mbst)
354 void *v;
355 bus_addr_t ioaddr;
356 bus_size_t iolen;
357 int flags;
358 struct mips_bus_space_translation *mbst;
359 {
360 bus_addr_t ioend = ioaddr + (iolen - 1);
361 int linear = flags & BUS_SPACE_MAP_LINEAR;
362
363 /*
364 * Can't map i/o space linearly.
365 */
366 if (linear)
367 return (EOPNOTSUPP);
368
369 #ifdef CHIP_IO_W1_BUS_START
370 if (ioaddr >= CHIP_IO_W1_BUS_START(v) &&
371 ioend <= CHIP_IO_W1_BUS_END(v))
372 return (__C(CHIP,_io_get_window)(v, 0, mbst));
373 #endif
374
375 #ifdef CHIP_IO_W2_BUS_START
376 if (ioaddr >= CHIP_IO_W2_BUS_START(v) &&
377 ioend <= CHIP_IO_W2_BUS_END(v))
378 return (__C(CHIP,_io_get_window)(v, 1, mbst));
379 #endif
380
381 #ifdef EXTENT_DEBUG
382 printf("\n");
383 #ifdef CHIP_IO_W1_BUS_START
384 printf("%s: window[1]=0x%lx-0x%lx\n",
385 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v),
386 CHIP_IO_W1_BUS_END(v));
387 #endif
388 #ifdef CHIP_IO_W2_BUS_START
389 printf("%s: window[2]=0x%lx-0x%lx\n",
390 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v),
391 CHIP_IO_W2_BUS_END(v));
392 #endif
393 #endif /* EXTENT_DEBUG */
394 /* No translation. */
395 return (EINVAL);
396 }
397
398 int
399 __C(CHIP,_io_get_window)(v, window, mbst)
400 void *v;
401 int window;
402 struct mips_bus_space_translation *mbst;
403 {
404
405 switch (window) {
406 #ifdef CHIP_IO_W1_BUS_START
407 case 0:
408 mbst->mbst_bus_start = CHIP_IO_W1_BUS_START(v);
409 mbst->mbst_bus_end = CHIP_IO_W1_BUS_END(v);
410 mbst->mbst_sys_start = CHIP_IO_W1_SYS_START(v);
411 mbst->mbst_sys_end = CHIP_IO_W1_SYS_END(v);
412 mbst->mbst_align_stride = CHIP_ALIGN_STRIDE;
413 mbst->mbst_flags = 0;
414 break;
415 #endif
416
417 #ifdef CHIP_IO_W2_BUS_START
418 case 1:
419 mbst->mbst_bus_start = CHIP_IO_W2_BUS_START(v);
420 mbst->mbst_bus_end = CHIP_IO_W2_BUS_END(v);
421 mbst->mbst_sys_start = CHIP_IO_W2_SYS_START(v);
422 mbst->mbst_sys_end = CHIP_IO_W2_SYS_END(v);
423 mbst->mbst_align_stride = CHIP_ALIGN_STRIDE;
424 mbst->mbst_flags = 0;
425 break;
426 #endif
427
428 default:
429 panic(__S(__C(CHIP,_io_get_window)) ": invalid window %d",
430 window);
431 }
432
433 return (0);
434 }
435
436 int
437 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp, acct)
438 void *v;
439 bus_addr_t ioaddr;
440 bus_size_t iosize;
441 int flags;
442 bus_space_handle_t *iohp;
443 int acct;
444 {
445 struct mips_bus_space_translation mbst;
446 int error;
447
448 /*
449 * Get the translation for this address.
450 */
451 error = __C(CHIP,_io_translate)(v, ioaddr, iosize, flags, &mbst);
452 if (error)
453 return (error);
454
455 #ifdef CHIP_IO_EXTENT
456 if (acct == 0)
457 goto mapit;
458
459 #ifdef EXTENT_DEBUG
460 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
461 #endif
462 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize,
463 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
464 if (error) {
465 #ifdef EXTENT_DEBUG
466 printf("io: allocation failed (%d)\n", error);
467 extent_print(CHIP_IO_EXTENT(v));
468 #endif
469 return (error);
470 }
471
472 mapit:
473 #endif /* CHIP_IO_EXTENT */
474 if (flags & BUS_SPACE_MAP_CACHEABLE)
475 *iohp = MIPS_PHYS_TO_KSEG0(mbst.mbst_sys_start +
476 (ioaddr - mbst.mbst_bus_start));
477 else
478 *iohp = MIPS_PHYS_TO_KSEG1(mbst.mbst_sys_start +
479 (ioaddr - mbst.mbst_bus_start));
480
481 return (0);
482 }
483
484 void
485 __C(CHIP,_io_unmap)(v, ioh, iosize, acct)
486 void *v;
487 bus_space_handle_t ioh;
488 bus_size_t iosize;
489 int acct;
490 {
491 #ifdef CHIP_IO_EXTENT
492 bus_addr_t ioaddr;
493 int error;
494
495 if (acct == 0)
496 return;
497
498 #ifdef EXTENT_DEBUG
499 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize);
500 #endif
501
502 if (ioh >= MIPS_KSEG0_START && ioh < MIPS_KSEG1_START)
503 ioh = MIPS_KSEG0_TO_PHYS(ioh);
504 else
505 ioh = MIPS_KSEG1_TO_PHYS(ioh);
506
507 #ifdef CHIP_IO_W1_BUS_START
508 if (ioh >= CHIP_IO_W1_SYS_START(v) &&
509 ioh <= CHIP_IO_W1_SYS_END(v)) {
510 ioaddr = CHIP_IO_W1_BUS_START(v) +
511 (ioh - CHIP_IO_W1_SYS_START(v));
512 } else
513 #endif
514 #ifdef CHIP_IO_W2_BUS_START
515 if (ioh >= CHIP_IO_W2_SYS_START(v) &&
516 ioh <= CHIP_IO_W2_SYS_END(v)) {
517 ioaddr = CHIP_IO_W2_BUS_START(v) +
518 (ioh - CHIP_IO_W2_SYS_START(v));
519 } else
520 #endif
521 {
522 printf("\n");
523 #ifdef CHIP_IO_W1_BUS_START
524 printf("%s: sys window[1]=0x%lx-0x%lx\n",
525 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v),
526 CHIP_IO_W1_SYS_END(v));
527 #endif
528 #ifdef CHIP_IO_W2_BUS_START
529 printf("%s: sys window[2]=0x%lx-0x%lx\n",
530 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v),
531 CHIP_IO_W2_SYS_END(v));
532 #endif
533 panic("%s: don't know how to unmap %lx",
534 __S(__C(CHIP,_io_unmap)), ioh);
535 }
536
537 #ifdef EXTENT_DEBUG
538 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1);
539 #endif
540 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize,
541 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
542 if (error) {
543 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n",
544 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1,
545 error);
546 #ifdef EXTENT_DEBUG
547 extent_print(CHIP_IO_EXTENT(v));
548 #endif
549 }
550 #endif /* CHIP_IO_EXTENT */
551 }
552
553 int
554 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh)
555 void *v;
556 bus_space_handle_t ioh, *nioh;
557 bus_size_t offset, size;
558 {
559
560 *nioh = ioh + (offset << CHIP_ALIGN_STRIDE);
561 return (0);
562 }
563
564 int
565 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags,
566 addrp, bshp)
567 void *v;
568 bus_addr_t rstart, rend, *addrp;
569 bus_size_t size, align, boundary;
570 int flags;
571 bus_space_handle_t *bshp;
572 {
573 #ifdef CHIP_IO_EXTENT
574 struct mips_bus_space_translation mbst;
575 int linear = flags & BUS_SPACE_MAP_LINEAR;
576 bus_addr_t ioaddr;
577 int error;
578
579 /*
580 * Can't map i/o space linearly.
581 */
582 if (linear)
583 return (EOPNOTSUPP);
584
585 /*
586 * Do the requested allocation.
587 */
588 #ifdef EXTENT_DEBUG
589 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend);
590 #endif
591 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend,
592 size, align, boundary,
593 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0),
594 &ioaddr);
595 if (error) {
596 #ifdef EXTENT_DEBUG
597 printf("io: allocation failed (%d)\n", error);
598 extent_print(CHIP_IO_EXTENT(v));
599 #endif
600 return (error);
601 }
602
603 #ifdef EXTENT_DEBUG
604 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1);
605 #endif
606
607 error = __C(CHIP,_io_translate)(v, ioaddr, size, flags, &mbst);
608 if (error) {
609 (void) extent_free(CHIP_IO_EXTENT(v), ioaddr, size,
610 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0));
611 return (error);
612 }
613
614 *addrp = ioaddr;
615 if (flags & BUS_SPACE_MAP_CACHEABLE)
616 *bshp = MIPS_PHYS_TO_KSEG0(mbst.mbst_sys_start +
617 (ioaddr - mbst.mbst_bus_start));
618 else
619 *bshp = MIPS_PHYS_TO_KSEG1(mbst.mbst_sys_start +
620 (ioaddr - mbst.mbst_bus_start));
621
622 return (0);
623 #else /* ! CHIP_IO_EXTENT */
624 return (EOPNOTSUPP);
625 #endif /* CHIP_IO_EXTENT */
626 }
627
628 void
629 __C(CHIP,_io_free)(v, bsh, size)
630 void *v;
631 bus_space_handle_t bsh;
632 bus_size_t size;
633 {
634
635 /* Unmap does all we need to do. */
636 __C(CHIP,_io_unmap)(v, bsh, size, 1);
637 }
638
639 void *
640 __C(CHIP,_io_vaddr)(v, bsh)
641 void *v;
642 bus_space_handle_t bsh;
643 {
644 /*
645 * _io_translate() catches BUS_SPACE_MAP_LINEAR,
646 * so we shouldn't get here
647 */
648 panic("_io_vaddr");
649 }
650
651 paddr_t
652 __C(CHIP,_io_mmap)(v, addr, off, prot, flags)
653 void *v;
654 bus_addr_t addr;
655 off_t off;
656 int prot;
657 int flags;
658 {
659
660 /* Not supported for I/O space. */
661 return (-1);
662 }
663
664 inline void
665 __C(CHIP,_io_barrier)(v, h, o, l, f)
666 void *v;
667 bus_space_handle_t h;
668 bus_size_t o, l;
669 int f;
670 {
671
672 /* XXX XXX XXX */
673 if ((f & BUS_SPACE_BARRIER_WRITE) != 0)
674 wbflush();
675 }
676
677 inline u_int8_t
678 __C(CHIP,_io_read_1)(v, ioh, off)
679 void *v;
680 bus_space_handle_t ioh;
681 bus_size_t off;
682 {
683 u_int8_t *ptr = (void *)(ioh + (off << CHIP_ALIGN_STRIDE));
684
685 return (*ptr);
686 }
687
688 inline u_int16_t
689 __C(CHIP,_io_read_2)(v, ioh, off)
690 void *v;
691 bus_space_handle_t ioh;
692 bus_size_t off;
693 {
694 #if CHIP_ALIGN_STRIDE >= 1
695 u_int16_t *ptr = (void *)(ioh + (off << (CHIP_ALIGN_STRIDE - 1)));
696 #else
697 u_int16_t *ptr = (void *)(ioh + off);
698 #endif
699
700 return (*ptr);
701 }
702
703 inline u_int32_t
704 __C(CHIP,_io_read_4)(v, ioh, off)
705 void *v;
706 bus_space_handle_t ioh;
707 bus_size_t off;
708 {
709 #if CHIP_ALIGN_STRIDE >= 2
710 u_int32_t *ptr = (void *)(ioh + (off << (CHIP_ALIGN_STRIDE - 2)));
711 #else
712 u_int32_t *ptr = (void *)(ioh + off);
713 #endif
714
715 return (*ptr);
716 }
717
718 inline u_int64_t
719 __C(CHIP,_io_read_8)(v, ioh, off)
720 void *v;
721 bus_space_handle_t ioh;
722 bus_size_t off;
723 {
724
725 /* XXX XXX XXX */
726 panic("%s not implemented", __S(__C(CHIP,_io_read_8)));
727 }
728
729 #define CHIP_io_read_multi_N(BYTES,TYPE) \
730 void \
731 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \
732 void *v; \
733 bus_space_handle_t h; \
734 bus_size_t o, c; \
735 TYPE *a; \
736 { \
737 \
738 while (c-- > 0) { \
739 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
740 BUS_SPACE_BARRIER_READ); \
741 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
742 } \
743 }
744 CHIP_io_read_multi_N(1,u_int8_t)
745 CHIP_io_read_multi_N(2,u_int16_t)
746 CHIP_io_read_multi_N(4,u_int32_t)
747 CHIP_io_read_multi_N(8,u_int64_t)
748
749 #define CHIP_io_read_region_N(BYTES,TYPE) \
750 void \
751 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \
752 void *v; \
753 bus_space_handle_t h; \
754 bus_size_t o, c; \
755 TYPE *a; \
756 { \
757 \
758 while (c-- > 0) { \
759 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \
760 o += sizeof *a; \
761 } \
762 }
763 CHIP_io_read_region_N(1,u_int8_t)
764 CHIP_io_read_region_N(2,u_int16_t)
765 CHIP_io_read_region_N(4,u_int32_t)
766 CHIP_io_read_region_N(8,u_int64_t)
767
768 inline void
769 __C(CHIP,_io_write_1)(v, ioh, off, val)
770 void *v;
771 bus_space_handle_t ioh;
772 bus_size_t off;
773 u_int8_t val;
774 {
775 u_int8_t *ptr = (void *)(ioh + (off << CHIP_ALIGN_STRIDE));
776
777 *ptr = val;
778 }
779
780 inline void
781 __C(CHIP,_io_write_2)(v, ioh, off, val)
782 void *v;
783 bus_space_handle_t ioh;
784 bus_size_t off;
785 u_int16_t val;
786 {
787 #if CHIP_ALIGN_STRIDE >= 1
788 u_int16_t *ptr = (void *)(ioh + (off << (CHIP_ALIGN_STRIDE - 1)));
789 #else
790 u_int16_t *ptr = (void *)(ioh + off);
791 #endif
792
793 *ptr = val;
794 }
795
796 inline void
797 __C(CHIP,_io_write_4)(v, ioh, off, val)
798 void *v;
799 bus_space_handle_t ioh;
800 bus_size_t off;
801 u_int32_t val;
802 {
803 #if CHIP_ALIGN_STRIDE >= 2
804 u_int32_t *ptr = (void *)(ioh + (off << (CHIP_ALIGN_STRIDE - 2)));
805 #else
806 u_int32_t *ptr = (void *)(ioh + off);
807 #endif
808
809 *ptr = val;
810 }
811
812 inline void
813 __C(CHIP,_io_write_8)(v, ioh, off, val)
814 void *v;
815 bus_space_handle_t ioh;
816 bus_size_t off;
817 u_int64_t val;
818 {
819
820 /* XXX XXX XXX */
821 panic("%s not implemented", __S(__C(CHIP,_io_write_8)));
822 }
823
824 #define CHIP_io_write_multi_N(BYTES,TYPE) \
825 void \
826 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \
827 void *v; \
828 bus_space_handle_t h; \
829 bus_size_t o, c; \
830 const TYPE *a; \
831 { \
832 \
833 while (c-- > 0) { \
834 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
835 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \
836 BUS_SPACE_BARRIER_WRITE); \
837 } \
838 }
839 CHIP_io_write_multi_N(1,u_int8_t)
840 CHIP_io_write_multi_N(2,u_int16_t)
841 CHIP_io_write_multi_N(4,u_int32_t)
842 CHIP_io_write_multi_N(8,u_int64_t)
843
844 #define CHIP_io_write_region_N(BYTES,TYPE) \
845 void \
846 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \
847 void *v; \
848 bus_space_handle_t h; \
849 bus_size_t o, c; \
850 const TYPE *a; \
851 { \
852 \
853 while (c-- > 0) { \
854 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \
855 o += sizeof *a; \
856 } \
857 }
858 CHIP_io_write_region_N(1,u_int8_t)
859 CHIP_io_write_region_N(2,u_int16_t)
860 CHIP_io_write_region_N(4,u_int32_t)
861 CHIP_io_write_region_N(8,u_int64_t)
862
863 #define CHIP_io_set_multi_N(BYTES,TYPE) \
864 void \
865 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \
866 void *v; \
867 bus_space_handle_t h; \
868 bus_size_t o, c; \
869 TYPE val; \
870 { \
871 \
872 while (c-- > 0) { \
873 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
874 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \
875 BUS_SPACE_BARRIER_WRITE); \
876 } \
877 }
878 CHIP_io_set_multi_N(1,u_int8_t)
879 CHIP_io_set_multi_N(2,u_int16_t)
880 CHIP_io_set_multi_N(4,u_int32_t)
881 CHIP_io_set_multi_N(8,u_int64_t)
882
883 #define CHIP_io_set_region_N(BYTES,TYPE) \
884 void \
885 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \
886 void *v; \
887 bus_space_handle_t h; \
888 bus_size_t o, c; \
889 TYPE val; \
890 { \
891 \
892 while (c-- > 0) { \
893 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \
894 o += sizeof val; \
895 } \
896 }
897 CHIP_io_set_region_N(1,u_int8_t)
898 CHIP_io_set_region_N(2,u_int16_t)
899 CHIP_io_set_region_N(4,u_int32_t)
900 CHIP_io_set_region_N(8,u_int64_t)
901
902 #define CHIP_io_copy_region_N(BYTES) \
903 void \
904 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \
905 void *v; \
906 bus_space_handle_t h1, h2; \
907 bus_size_t o1, o2, c; \
908 { \
909 bus_size_t o; \
910 \
911 if ((h1 + o1) >= (h2 + o2)) { \
912 /* src after dest: copy forward */ \
913 for (o = 0; c != 0; c--, o += BYTES) \
914 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \
915 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \
916 } else { \
917 /* dest after src: copy backwards */ \
918 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \
919 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \
920 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \
921 } \
922 }
923 CHIP_io_copy_region_N(1)
924 CHIP_io_copy_region_N(2)
925 CHIP_io_copy_region_N(4)
926 CHIP_io_copy_region_N(8)
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