sys/arch/alpha/include/rpb.h

   1 /* $NetBSD: rpb.h,v 1.40 2002/07/25 15:39:42 he Exp $ */
   2
   3 /*
   4  * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
   5  * All rights reserved.
   6  *
   7  * Author: Keith Bostic, Chris G. Demetriou
   8  *
   9  * Permission to use, copy, modify and distribute this software and
  10  * its documentation is hereby granted, provided that both the copyright
  11  * notice and this permission notice appear in all copies of the
  12  * software, derivative works or modified versions, and any portions
  13  * thereof, and that both notices appear in supporting documentation.
  14  *
  15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
  17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  18  *
  19  * Carnegie Mellon requests users of this software to return to
  20  *
  21  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  22  *  School of Computer Science
  23  *  Carnegie Mellon University
  24  *  Pittsburgh PA 15213-3890
  25  *
  26  * any improvements or extensions that they make and grant Carnegie the
  27  * rights to redistribute these changes.
  28  */
  29
  30 /*
  31  * From DEC 3000 300/400/500/600/700/800/900 System Programmer's Manual,
  32  * EK-D3SYS-PM.B01.
  33  */
  34
  35 /*
  36  * HWRPB (Hardware Restart Parameter Block).
  37  */
  38 #define HWRPB_ADDR      0x10000000              /* virtual address, at boot */
  39
  40 #ifndef ASSEMBLER
  41 struct rpb {
  42         u_int64_t       rpb_phys;               /*   0: HWRPB phys. address. */
  43         char            rpb_magic[8];           /*   8: "HWRPB" (in ASCII) */
  44         u_int64_t       rpb_version;            /*  10 */
  45         u_int64_t       rpb_size;               /*  18: HWRPB size in bytes */
  46         u_int64_t       rpb_primary_cpu_id;     /*  20 */
  47         u_int64_t       rpb_page_size;          /*  28: (8192) */
  48         u_int32_t       rpb_phys_addr_size;     /*  30: physical address size */
  49         u_int32_t       rpb_extended_va_size;   /*  34: extended VA size (4L) */
  50         u_int64_t       rpb_max_asn;            /*  38:   (16) */
  51         char            rpb_ssn[16];            /*  40: only first 10 valid */
  52
  53 #define ST_ADU                  1               /* Alpha Demo. Unit (?) */
  54 #define ST_DEC_4000             2               /* "Cobra" */
  55 #define ST_DEC_7000             3               /* "Ruby" */
  56 #define ST_DEC_3000_500         4               /* "Flamingo" family (TC) */
  57 #define ST_DEC_2000_300         6               /* "Jensen" (EISA/ISA) */
  58 #define ST_DEC_3000_300         7               /* "Pelican" (TC) */
  59 #define ST_AVALON_A12           8               /* XXX Avalon Multicomputer */
  60 #define ST_DEC_2100_A500        9               /* "Sable" */
  61 #define ST_DEC_APXVME_64        10              /* "AXPvme" (VME) */
  62 #define ST_DEC_AXPPCI_33        11              /* "NoName" (PCI/ISA) */
  63 #define ST_DEC_21000            12              /* "TurboLaser" (PCI/EISA) */
  64 #define ST_DEC_2100_A50         13              /* "Avanti" (PCI/ISA) */
  65 #define ST_DEC_MUSTANG          14              /* "Mustang" */
  66 #define ST_DEC_KN20AA           15              /* kn20aa (PCI/EISA) */
  67 #define ST_DEC_1000             17              /* "Mikasa" (PCI/EISA) */
  68 #define ST_EB66                 19              /* EB66 (PCI/ISA?) */
  69 #define ST_EB64P                20              /* EB64+ (PCI/ISA?) */
  70 #define ST_ALPHABOOK1           21              /* Alphabook1 */
  71 #define ST_DEC_4100             22              /* "Rawhide" (PCI/EISA) */
  72 #define ST_DEC_EV45_PBP         23              /* "Lego" K2 Passive SBC */
  73 #define ST_DEC_2100A_A500       24              /* "Lynx" */
  74 #define ST_EB164                26              /* EB164 (PCI/ISA) */
  75 #define ST_DEC_1000A            27              /* "Noritake" (PCI/EISA)*/
  76 #define ST_DEC_ALPHAVME_224     28              /* "Cortex" */
  77 #define ST_DEC_550              30              /* "Miata" (PCI/ISA) */
  78 #define ST_DEC_EV56_PBP         32              /* "Takara" */
  79 #define ST_DEC_ALPHAVME_320     33              /* "Yukon" (VME) */
  80 #define ST_DEC_6600             34              /* EV6-Tsunami based systems */
  81 #define ST_DEC_WILDFIRE         35              /* "Wildfire" */
  82 #define ST_DEC_CUSCO            36              /* "CUSCO" */
  83 #define ST_DEC_EIGER            37              /* "Eiger" */
  84 #define ST_DEC_TITAN            38              /* "Titan" */
  85
  86         /* Alpha Processor, Inc. systypes */
  87 #define ST_API_NAUTILUS         201             /* EV6-AMD 751 UP1000 */
  88
  89         u_int64_t       rpb_type;               /*  50: */
  90
  91 #define SV_MPCAP                0x00000001      /* multiprocessor capable */
  92
  93 #define SV_CONSOLE              0x0000001e      /* console hardware mask */
  94 #define SV_CONSOLE_DETACHED     0x00000002
  95 #define SV_CONSOLE_EMBEDDED     0x00000004
  96
  97 #define SV_POWERFAIL            0x000000e0      /* powerfail mask */
  98 #define SV_PF_UNITED            0x00000020
  99 #define SV_PF_SEPARATE          0x00000040
 100 #define SV_PF_BBACKUP           0x00000060
 101 #define SV_PF_ACTION            0x00000100      /* powerfail restart */
 102
 103 #define SV_GRAPHICS             0x00000200      /* graphic engine present */
 104
 105 #define SV_ST_MASK              0x0000fc00      /* system type mask */
 106 #define SV_ST_RESERVED          0x00000000      /* RESERVED */
 107
 108 /*
 109  * System types for the DEC 3000/500 (Flamingo) Family
 110  */
 111 #define SV_ST_SANDPIPER         0x00000400      /* Sandpiper;   3000/400 */
 112 #define SV_ST_FLAMINGO          0x00000800      /* Flamingo;    3000/500 */
 113 #define SV_ST_HOTPINK           0x00000c00      /* "Hot Pink";  3000/500X */
 114 #define SV_ST_FLAMINGOPLUS      0x00001000      /* Flamingo+;   3000/800 */
 115 #define SV_ST_ULTRA             0x00001400      /* "Ultra", aka Flamingo+ */
 116 #define SV_ST_SANDPLUS          0x00001800      /* Sandpiper+;  3000/600 */
 117 #define SV_ST_SANDPIPER45       0x00001c00      /* Sandpiper45; 3000/700 */
 118 #define SV_ST_FLAMINGO45        0x00002000      /* Flamingo45;  3000/900 */
 119
 120 /*
 121  * System types for ???
 122  */
 123 #define SV_ST_SABLE             0x00000400      /* Sable (???) */
 124
 125 /*
 126  * System types for the DEC 3000/300 (Pelican) Family
 127  */
 128 #define SV_ST_PELICAN           0x00000000      /* Pelican;      3000/300 */
 129 #define SV_ST_PELICA            0x00000400      /* Pelica;       3000/300L */
 130 #define SV_ST_PELICANPLUS       0x00000800      /* Pelican+;     3000/300X */
 131 #define SV_ST_PELICAPLUS        0x00000c00      /* Pelica+;      3000/300LX */
 132
 133 /*
 134  * System types for the AlphaStation Family
 135  */
 136 #define SV_ST_AVANTI            0x00000000      /* Avanti;      400 4/233 */
 137 #define SV_ST_MUSTANG2_4_166    0x00000800      /* Mustang II;  200 4/166 */
 138 #define SV_ST_MUSTANG2_4_233    0x00001000      /* Mustang II;  200 4/233 */
 139 #define SV_ST_AVANTI_XXX        0x00001400      /* also Avanti; 400 4/233 */
 140 #define SV_ST_AVANTI_4_266      0x00002000
 141 #define SV_ST_MUSTANG2_4_100    0x00002400      /* Mustang II;  200 4/100 */
 142 #define SV_ST_AVANTI_4_233      0x0000a800      /* AlphaStation 255/233 */
 143
 144 #define SV_ST_KN20AA            0x00000400      /* AlphaStation 500/600 */
 145
 146 /*
 147  * System types for the AXPvme Family
 148  */
 149 #define SV_ST_AXPVME_64         0x00000000      /* 21068, 64MHz */
 150 #define SV_ST_AXPVME_160        0x00000400      /* 21066, 160MHz */
 151 #define SV_ST_AXPVME_100        0x00000c00      /* 21066A, 99MHz */
 152 #define SV_ST_AXPVME_230        0x00001000      /* 21066A, 231MHz */
 153 #define SV_ST_AXPVME_66         0x00001400      /* 21066A, 66MHz */
 154 #define SV_ST_AXPVME_166        0x00001800      /* 21066A, 165MHz */
 155 #define SV_ST_AXPVME_264        0x00001c00      /* 21066A, 264MHz */
 156
 157 /*
 158  * System types for the EB164 Family
 159  */
 160 #define SV_ST_EB164_266         0x00000400      /* EB164, 266MHz */
 161 #define SV_ST_EB164_300         0x00000800      /* EB164, 300MHz */
 162 #define SV_ST_ALPHAPC164_366    0x00000c00      /* AlphaPC164, 366MHz */
 163 #define SV_ST_ALPHAPC164_400    0x00001000      /* AlphaPC164, 400MHz */
 164 #define SV_ST_ALPHAPC164_433    0x00001400      /* AlphaPC164, 433MHz */
 165 #define SV_ST_ALPHAPC164_466    0x00001800      /* AlphaPC164, 466MHz */
 166 #define SV_ST_ALPHAPC164_500    0x00001c00      /* AlphaPC164, 500MHz */
 167 #define SV_ST_ALPHAPC164LX_400  0x00002000      /* AlphaPC164LX, 400MHz */
 168 #define SV_ST_ALPHAPC164LX_466  0x00002400      /* AlphaPC164LX, 466MHz */
 169 #define SV_ST_ALPHAPC164LX_533  0x00002800      /* AlphaPC164LX, 533MHz */
 170 #define SV_ST_ALPHAPC164LX_600  0x00002c00      /* AlphaPC164LX, 600MHz */
 171 #define SV_ST_ALPHAPC164SX_400  0x00003000      /* AlphaPC164SX, 400MHz */
 172 #define SV_ST_ALPHAPC164SX_466  0x00003400      /* AlphaPC164SX, 433MHz */
 173 #define SV_ST_ALPHAPC164SX_533  0x00003800      /* AlphaPC164SX, 533MHz */
 174 #define SV_ST_ALPHAPC164SX_600  0x00003c00      /* AlphaPC164SX, 600MHz */
 175
 176 /*
 177  * System types for the Digital Personal Workstation (Miata) Family
 178  * XXX These are not very complete!
 179  */
 180 #define SV_ST_MIATA_1_5         0x00004c00      /* Miata 1.5 */
 181
 182         u_int64_t       rpb_variation;          /*  58 */
 183
 184         char            rpb_revision[8];        /*  60; only first 4 valid */
 185         u_int64_t       rpb_intr_freq;          /*  68; scaled by 4096 */
 186         u_int64_t       rpb_cc_freq;            /*  70: cycle cntr frequency */
 187         u_long          rpb_vptb;               /*  78: */
 188         u_int64_t       rpb_reserved_arch;      /*  80: */
 189         u_long          rpb_tbhint_off;         /*  88: */
 190         u_int64_t       rpb_pcs_cnt;            /*  90: */
 191         u_int64_t       rpb_pcs_size;           /*  98; pcs size in bytes */
 192         u_long          rpb_pcs_off;            /*  A0: offset to pcs info */
 193         u_int64_t       rpb_ctb_cnt;            /*  A8: console terminal */
 194         u_int64_t       rpb_ctb_size;           /*  B0: ctb size in bytes */
 195         u_long          rpb_ctb_off;            /*  B8: offset to ctb */
 196         u_long          rpb_crb_off;            /*  C0: offset to crb */
 197         u_long          rpb_memdat_off;         /*  C8: memory data offset */
 198         u_long          rpb_condat_off;         /*  D0: config data offset */
 199         u_long          rpb_fru_off;            /*  D8: FRU table offset */
 200         u_int64_t       rpb_save_term;          /*  E0: terminal save */
 201         u_int64_t       rpb_save_term_val;      /*  E8: */
 202         u_int64_t       rpb_rest_term;          /*  F0: terminal restore */
 203         u_int64_t       rpb_rest_term_val;      /*  F8: */
 204         u_int64_t       rpb_restart;            /* 100: restart */
 205         u_int64_t       rpb_restart_val;        /* 108: */
 206         u_int64_t       rpb_reserve_os;         /* 110: */
 207         u_int64_t       rpb_reserve_hw;         /* 118: */
 208         u_int64_t       rpb_checksum;           /* 120: HWRPB checksum */
 209         u_int64_t       rpb_rxrdy;              /* 128: receive ready */
 210         u_int64_t       rpb_txrdy;              /* 130: transmit ready */
 211         u_long          rpb_dsrdb_off;          /* 138: HWRPB + DSRDB offset */
 212         u_int64_t       rpb_tbhint[8];          /* 149: TB hint block */
 213 };
 214
 215 #define LOCATE_PCS(h,cpunumber) ((struct pcs *) \
 216         ((char *)(h) + (h)->rpb_pcs_off + ((cpunumber) * (h)->rpb_pcs_size)))
 217
 218 /*
 219  * PCS: Per-CPU information.
 220  */
 221 struct pcs {
 222         u_int8_t        pcs_hwpcb[128];         /*   0: PAL dependent */
 223
 224 #define PCS_BIP                 0x000001        /* boot in progress */
 225 #define PCS_RC                  0x000002        /* restart possible */
 226 #define PCS_PA                  0x000004        /* processor available */
 227 #define PCS_PP                  0x000008        /* processor present */
 228 #define PCS_OH                  0x000010        /* user halted */
 229 #define PCS_CV                  0x000020        /* context valid */
 230 #define PCS_PV                  0x000040        /* PALcode valid */
 231 #define PCS_PMV                 0x000080        /* PALcode memory valid */
 232 #define PCS_PL                  0x000100        /* PALcode loaded */
 233
 234 #define PCS_HALT_REQ            0xff0000        /* halt request mask */
 235 #define PCS_HALT_DEFAULT        0x000000
 236 #define PCS_HALT_SAVE_EXIT      0x010000
 237 #define PCS_HALT_COLD_BOOT      0x020000
 238 #define PCS_HALT_WARM_BOOT      0x030000
 239 #define PCS_HALT_STAY_HALTED    0x040000
 240 #define PCS_mbz       0xffffffffff000000        /* 24:63 -- must be zero */
 241         u_int64_t       pcs_flags;              /*  80: */
 242
 243         u_int64_t       pcs_pal_memsize;        /*  88: PAL memory size */
 244         u_int64_t       pcs_pal_scrsize;        /*  90: PAL scratch size */
 245         u_long          pcs_pal_memaddr;        /*  98: PAL memory addr */
 246         u_long          pcs_pal_scraddr;        /*  A0: PAL scratch addr */
 247         struct {
 248                 u_int64_t
 249                         minorrev        : 8,    /* alphabetic char 'a' - 'z' */
 250                         majorrev        : 8,    /* alphabetic char 'a' - 'z' */
 251 #define PAL_TYPE_STANDARD       0
 252 #define PAL_TYPE_VMS            1
 253 #define PAL_TYPE_OSF1           2
 254                         pal_type        : 8,    /* PALcode type:
 255                                                  * 0 == standard
 256                                                  * 1 == OpenVMS
 257                                                  * 2 == OSF/1
 258                                                  * 3-127 DIGITAL reserv.
 259                                                  * 128-255 non-DIGITAL reserv.
 260                                                  */
 261                         sbz1            : 8,
 262                         compatibility   : 16,   /* Compatibility revision */
 263                         proc_cnt        : 16;   /* Processor count */
 264         } pcs_pal_rev;                          /*  A8: */
 265 #define pcs_minorrev    pcs_pal_rev.minorrev
 266 #define pcs_majorrev    pcs_pal_rev.majorrev
 267 #define pcs_pal_type    pcs_pal_rev.pal_type
 268 #define pcs_compatibility       pcs_pal_rev.compatibility
 269 #define pcs_proc_cnt    pcs_pal_rev.proc_cnt
 270
 271         u_int64_t       pcs_proc_type;          /*  B0: processor type */
 272
 273 #define PCS_PROC_EV3            1                       /* EV3 */
 274 #define PCS_PROC_EV4            2                       /* EV4: 21064 */
 275 #define PCS_PROC_SIMULATION     3                       /* Simulation */
 276 #define PCS_PROC_LCA4           4                       /* LCA4: 2106[68] */
 277 #define PCS_PROC_EV5            5                       /* EV5: 21164 */
 278 #define PCS_PROC_EV45           6                       /* EV45: 21064A */
 279 #define PCS_PROC_EV56           7                       /* EV56: 21164A */
 280 #define PCS_PROC_EV6            8                       /* EV6: 21264 */
 281 #define PCS_PROC_PCA56          9                       /* PCA56: 21164PC */
 282 #define PCS_PROC_PCA57          10                      /* PCA57: 21164?? */
 283 #define PCS_PROC_EV67           11                      /* EV67: 21246A */
 284 #define PCS_PROC_EV68CB         12                      /* EV68CB: 21264C */
 285 #define PCS_PROC_EV68AL         13                      /* EV68AL: 21264B */
 286 #define PCS_PROC_EV68CX         14                      /* EV68CX: 21264D */
 287
 288 #define PCS_CPU_MAJORTYPE(p) ((p)->pcs_proc_type & 0xffffffff)
 289 #define PCS_CPU_MINORTYPE(p) ((p)->pcs_proc_type >> 32)
 290
 291         /* Minor number interpretation is processor specific.  See cpu.c. */
 292
 293         u_int64_t       pcs_proc_var;           /* B8: processor variation. */
 294
 295 #define PCS_VAR_VAXFP           0x0000000000000001      /* VAX FP support */
 296 #define PCS_VAR_IEEEFP          0x0000000000000002      /* IEEE FP support */
 297 #define PCS_VAR_PE              0x0000000000000004      /* Primary Eligible */
 298 #define PCS_VAR_RESERVED        0xfffffffffffffff8      /* Reserved */
 299
 300         char            pcs_proc_revision[8];   /*  C0: only first 4 valid */
 301         char            pcs_proc_sn[16];        /*  C8: only first 10 valid */
 302         u_long          pcs_machcheck;          /*  D8: mach chk phys addr. */
 303         u_int64_t       pcs_machcheck_len;      /*  E0: length in bytes */
 304         u_long          pcs_halt_pcbb;          /*  E8: phys addr of halt PCB */
 305         u_long          pcs_halt_pc;            /*  F0: halt PC */
 306         u_int64_t       pcs_halt_ps;            /*  F8: halt PS */
 307         u_int64_t       pcs_halt_r25;           /* 100: halt argument list */
 308         u_int64_t       pcs_halt_r26;           /* 108: halt return addr list */
 309         u_int64_t       pcs_halt_r27;           /* 110: halt procedure value */
 310
 311 #define PCS_HALT_RESERVED               0
 312 #define PCS_HALT_POWERUP                1
 313 #define PCS_HALT_CONSOLE_HALT           2
 314 #define PCS_HALT_CONSOLE_CRASH          3
 315 #define PCS_HALT_KERNEL_MODE            4
 316 #define PCS_HALT_KERNEL_STACK_INVALID   5
 317 #define PCS_HALT_DOUBLE_ERROR_ABORT     6
 318 #define PCS_HALT_SCBB                   7
 319 #define PCS_HALT_PTBR                   8       /* 9-FF: reserved */
 320         u_int64_t       pcs_halt_reason;        /* 118: */
 321
 322         u_int64_t       pcs_reserved_soft;      /* 120: preserved software */
 323
 324         struct {                                /* 128: inter-console buffers */
 325                 u_int   iccb_rxlen;
 326                 u_int   iccb_txlen;
 327                 char    iccb_rxbuf[80];
 328                 char    iccb_txbuf[80];
 329         } pcs_iccb;
 330
 331 #define PALvar_reserved 0
 332 #define PALvar_OpenVMS  1
 333 #define PALvar_OSF1     2
 334         u_int64_t       pcs_palrevisions[16];   /* 1D0: PALcode revisions */
 335
 336         u_int64_t       pcs_reserved_arch[6];   /* 250: reserved arch */
 337 };
 338
 339 /*
 340  * CTB: Console Terminal Block
 341  */
 342 struct ctb {
 343         u_int64_t       ctb_type;               /*   0: CTB type */
 344         u_int64_t       ctb_unit;               /*   8: */
 345         u_int64_t       ctb_reserved;           /*  16: */
 346         u_int64_t       ctb_len;                /*  24: bytes of info */
 347         u_int64_t       ctb_ipl;                /*  32: console ipl level */
 348         u_long          ctb_tintr_vec;          /*  40: transmit vec (0x800) */
 349         u_long          ctb_rintr_vec;          /*  48: receive vec (0x800) */
 350
 351 #define CTB_NONE                0x00            /* no console present */
 352 #define CTB_SERVICE             0x01            /* service processor */
 353 #define CTB_PRINTERPORT         0x02            /* printer port on the SCC */
 354 #define CTB_GRAPHICS            0x03            /* graphics device */
 355 #define CTB_TYPE4               0x04            /* type 4 CTB */
 356 #define CTB_NETWORK             0xC0            /* network device */
 357         u_int64_t       ctb_term_type;          /*  56: terminal type */
 358
 359         u_int64_t       ctb_keybd_type;         /*  64: keyboard nationality */
 360         u_long          ctb_keybd_trans;        /*  72: trans. table addr */
 361         u_long          ctb_keybd_map;          /*  80: map table addr */
 362         u_int64_t       ctb_keybd_state;        /*  88: keyboard flags */
 363         u_int64_t       ctb_keybd_last;         /*  96: last key entered */
 364         u_long          ctb_font_us;            /* 104: US font table addr */
 365         u_long          ctb_font_mcs;           /* 112: MCS font table addr */
 366         u_int64_t       ctb_font_width;         /* 120: font width, height */
 367         u_int64_t       ctb_font_height;        /* 128:         in pixels */
 368         u_int64_t       ctb_mon_width;          /* 136: monitor width, height */
 369         u_int64_t       ctb_mon_height;         /* 144:         in pixels */
 370         u_int64_t       ctb_dpi;                /* 152: monitor dots per inch */
 371         u_int64_t       ctb_planes;             /* 160: # of planes */
 372         u_int64_t       ctb_cur_width;          /* 168: cursor width, height */
 373         u_int64_t       ctb_cur_height;         /* 176:         in pixels */
 374         u_int64_t       ctb_head_cnt;           /* 184: # of heads */
 375         u_int64_t       ctb_opwindow;           /* 192: opwindow on screen */
 376         u_long          ctb_head_offset;        /* 200: offset to head info */
 377         u_long          ctb_putchar;            /* 208: output char to TURBO */
 378         u_int64_t       ctb_io_state;           /* 216: I/O flags */
 379         u_int64_t       ctb_listen_state;       /* 224: listener flags */
 380         u_long          ctb_xaddr;              /* 232: extended info addr */
 381         u_int64_t       ctb_turboslot;          /* 248: TURBOchannel slot # */
 382         u_int64_t       ctb_server_off;         /* 256: offset to server info */
 383         u_int64_t       ctb_line_off;           /* 264: line parameter offset */
 384         u_int8_t        ctb_csd;                /* 272: console specific data */
 385 };
 386
 387 struct ctb_tt {
 388         u_int64_t       ctb_type;               /*   0: CTB type */
 389         u_int64_t       ctb_unit;               /*   8: console unit */
 390         u_int64_t       ctb_reserved;           /*  16: reserved */
 391         u_int64_t       ctb_length;             /*  24: length */
 392         u_int64_t       ctb_csr;                /*  32: address */
 393         u_int64_t       ctb_tivec;              /*  40: Tx intr vector */
 394         u_int64_t       ctb_rivec;              /*  48: Rx intr vector */
 395         u_int64_t       ctb_baud;               /*  56: baud rate */
 396         u_int64_t       ctb_put_sts;            /*  64: PUTS status */
 397         u_int64_t       ctb_get_sts;            /*  72: GETS status */
 398         u_int64_t       ctb_reserved0;          /*  80: reserved */
 399 };
 400
 401 /*
 402  * Format of the Console Terminal Block Type 4 `turboslot' field:
 403  *
 404  *  63                   40 39       32 31     24 23      16 15   8 7    0
 405  *  |      reserved        |  channel  |  hose   | bus type |  bus | slot|
 406  */
 407 #define CTB_TURBOSLOT_CHANNEL(x)        (((x) >> 32) & 0xff)
 408 #define CTB_TURBOSLOT_HOSE(x)           (((x) >> 24) & 0xff)
 409 #define CTB_TURBOSLOT_TYPE(x)           (((x) >> 16) & 0xff)
 410 #define CTB_TURBOSLOT_BUS(x)            (((x) >> 8) & 0xff)
 411 #define CTB_TURBOSLOT_SLOT(x)           ((x) & 0xff)
 412
 413 #define CTB_TURBOSLOT_TYPE_TC           0       /* TURBOchannel */
 414 #define CTB_TURBOSLOT_TYPE_ISA          1       /* ISA */
 415 #define CTB_TURBOSLOT_TYPE_EISA         2       /* EISA */
 416 #define CTB_TURBOSLOT_TYPE_PCI          3       /* PCI */
 417
 418 /*
 419  * CRD: Console Routine Descriptor
 420  */
 421 struct crd {
 422         int64_t         descriptor;
 423         u_int64_t       entry_va;
 424 };
 425
 426 /*
 427  * CRB: Console Routine Block
 428  */
 429 struct crb {
 430         struct crd      *crb_v_dispatch;        /*   0: virtual dispatch addr */
 431         u_long           crb_p_dispatch;        /*   8: phys dispatch addr */
 432         struct crd      *crb_v_fixup;           /*  10: virtual fixup addr */
 433         u_long           crb_p_fixup;           /*  18: phys fixup addr */
 434         u_int64_t        crb_map_cnt;           /*  20: phys/virt map entries */
 435         u_int64_t        crb_page_cnt;          /*  28: pages to be mapped */
 436 };
 437
 438 /*
 439  * MDDT: Memory Data Descriptor Table
 440  */
 441 struct mddt {
 442         int64_t         mddt_cksum;             /*   0: 7-N checksum */
 443         u_long          mddt_physaddr;          /*   8: bank config addr
 444                                                  * IMPLEMENTATION SPECIFIC
 445                                                  */
 446         u_int64_t       mddt_cluster_cnt;       /*  10: memory cluster count */
 447         struct mddt_cluster {
 448                 u_long          mddt_pfn;       /*   0: starting PFN */
 449                 u_int64_t       mddt_pg_cnt;    /*   8: 8KB page count */
 450                 u_int64_t       mddt_pg_test;   /*  10: tested page count */
 451                 u_long          mddt_v_bitaddr; /*  18: bitmap virt addr */
 452                 u_long          mddt_p_bitaddr; /*  20: bitmap phys addr */
 453                 int64_t         mddt_bit_cksum; /*  28: bitmap checksum */
 454
 455 #define MDDT_NONVOLATILE                0x10    /* cluster is non-volatile */
 456 #define MDDT_PALCODE                    0x01    /* console and PAL only */
 457 #define MDDT_SYSTEM                     0x00    /* system software only */
 458 #define MDDT_mbz          0xfffffffffffffffc    /* 2:63 -- must be zero */
 459                 int64_t         mddt_usage;     /*  30: bitmap permissions */
 460         } mddt_clusters[1];                     /* variable length array */
 461 };
 462
 463 /*
 464  * DSR: Dynamic System Recognition.  We're interested in the sysname
 465  * offset.  The data pointed to by sysname is:
 466  *
 467  *      [8 bytes: length of system name][N bytes: system name string]
 468  *
 469  * The system name string is NUL-terminated.
 470  */
 471 struct dsrdb {
 472         int64_t         dsr_smm;                /*  0: SMM number */
 473         u_int64_t       dsr_lurt_off;           /*  8: LURT table offset */
 474         u_int64_t       dsr_sysname_off;        /* 16: offset to sysname */
 475 };
 476
 477 /*
 478  * The DSR appeared in version 5 of the HWRPB.
 479  */
 480 #define HWRPB_DSRDB_MINVERS     5
 481
 482 #ifdef  _KERNEL
 483 extern int cputype;
 484 extern struct rpb *hwrpb;
 485 #endif
 486
 487 #endif /* ASSEMBLER */