sys/arch/arc/include/intr.h

   1 /*      $NetBSD: intr.h,v 1.21 2007/12/03 15:33:14 ad Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The NetBSD Foundation
   8  * by Jason R. Thorpe.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #ifndef _ARC_INTR_H_
  33 #define _ARC_INTR_H_
  34
  35 #define IPL_NONE        0       /* disable only this interrupt */
  36 #define IPL_SOFTCLOCK   1       /* generic software interrupts (SI 0) */
  37 #define IPL_SOFTBIO     1       /* clock software interrupts (SI 0) */
  38 #define IPL_SOFTNET     2       /* network software interrupts (SI 1) */
  39 #define IPL_SOFTSERIAL  2       /* serial software interrupts (SI 1) */
  40 #define IPL_VM          3
  41 #define IPL_SCHED       4
  42 #define IPL_HIGH        4
  43
  44 #define _IPL_N          5
  45
  46 #define _IPL_SI0_FIRST  IPL_SOFTCLOCK
  47 #define _IPL_SI0_LAST   IPL_SOFTBIO
  48
  49 #define _IPL_SI1_FIRST  IPL_SOFTNET
  50 #define _IPL_SI1_LAST   IPL_SOFTSERIAL
  51
  52 /* Interrupt sharing types. */
  53 #define IST_NONE        0       /* none */
  54 #define IST_PULSE       1       /* pulsed */
  55 #define IST_EDGE        2       /* edge-triggered */
  56 #define IST_LEVEL       3       /* level-triggered */
  57
  58 #ifdef _KERNEL
  59 #ifndef _LOCORE
  60
  61 #include <mips/locore.h>
  62
  63 extern const uint32_t *ipl_sr_bits;
  64
  65 #define spl0()          (void)_spllower(0)
  66 #define splx(s)         (void)_splset(s)
  67
  68 typedef int ipl_t;
  69 typedef struct {
  70         ipl_t _sr;
  71 } ipl_cookie_t;
  72
  73 static inline ipl_cookie_t
  74 makeiplcookie(ipl_t ipl)
  75 {
  76
  77         return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
  78 }
  79
  80 static inline int
  81 splraiseipl(ipl_cookie_t icookie)
  82 {
  83
  84         return _splraise(icookie._sr);
  85 }
  86
  87 #include <sys/spl.h>
  88
  89 #include <mips/softintr.h>
  90
  91 struct clockframe;
  92 void arc_set_intr(uint32_t, uint32_t (*)(uint32_t, struct clockframe *), int);
  93 extern uint32_t cpu_int_mask;
  94
  95 /* priority order to handle each CPU INT line specified via set_intr() */
  96 #define ARC_INTPRI_TIMER_INT    0       /* independent CPU INT for timer */
  97 #define ARC_INTPRI_JAZZ         1       /* CPU INT for JAZZ local bus */
  98 #define ARC_INTPRI_PCIISA       2       /* CPU INT for PCI/EISA/ISA */
  99 #define ARC_NINTPRI             3       /* number of total used CPU INTs */
 100
 101 #endif /* !_LOCORE */
 102 #endif /* _KERNEL */
 103
 104 #endif /* _ARC_INTR_H_ */