sys/arch/arc/jazz/dma.h

   1 /*      $NetBSD: dma.h,v 1.2 2001/07/24 16:26:53 tsutsui Exp $  */
   2 /*      $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $    */
   3
   4 /*
   5  * Copyright (c) 1996 Per Fogelstrom
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Per Fogelstrom.
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  *  Hardware dma registers.
  36  */
  37
  38 #define R4030_DMA_MODE          0x00
  39 #define  R4030_DMA_MODE_40NS    0x00    /* Device dma timing */
  40 #define  R4030_DMA_MODE_80NS    0x01    /* Device dma timing */
  41 #define  R4030_DMA_MODE_120NS   0x02    /* Device dma timing */
  42 #define  R4030_DMA_MODE_160NS   0x03    /* Device dma timing */
  43 #define  R4030_DMA_MODE_200NS   0x04    /* Device dma timing */
  44 #define  R4030_DMA_MODE_240NS   0x05    /* Device dma timing */
  45 #define  R4030_DMA_MODE_280NS   0x06    /* Device dma timing */
  46 #define  R4030_DMA_MODE_320NS   0x07    /* Device dma timing */
  47 #define  R4030_DMA_MODE_8       0x08    /* Device 8 bit  */
  48 #define  R4030_DMA_MODE_16      0x10    /* Device 16 bit */
  49 #define  R4030_DMA_MODE_32      0x18    /* Device 32 bit */
  50 #define  R4030_DMA_MODE_INT     0x20    /* Interrupt when done */
  51 #define  R4030_DMA_MODE_BURST   0x40    /* Burst mode (Rev 2 only) */
  52 #define  R4030_DMA_MODE_FAST    0x80    /* Fast dma cycle (Rev 2 only) */
  53
  54 #define R4030_DMA_ENAB          0x08
  55 #define  R4030_DMA_ENAB_RUN     0x0001  /* Enable dma */
  56 #define  R4030_DMA_ENAB_READ    0x0000  /* Read from device */
  57 #define  R4030_DMA_ENAB_WRITE   0x0002  /* Write to device */
  58 #define  R4030_DMA_ENAB_TC_IE   0x0100  /* Terminal count int enable */
  59 #define  R4030_DMA_ENAB_ME_IE   0x0200  /* Memory error int enable */
  60 #define  R4030_DMA_ENAB_TL_IE   0x0400  /* Translation limit int enable */
  61
  62 #define R4030_DMA_COUNT         0x10
  63 #define  R4030_DMA_COUNT_MASK   0x000fffff /* Byte count mask */
  64
  65 #define R4030_DMA_ADDR          0x18
  66
  67 #define R4030_DMA_RANGE         0x20