sys/arch/arm/arm32/cpu.c

   1 /*      $NetBSD: cpu.c,v 1.70 2008/10/24 13:23:45 matt Exp $    */
   2
   3 /*
   4  * Copyright (c) 1995 Mark Brinicombe.
   5  * Copyright (c) 1995 Brini.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Brini.
  19  * 4. The name of the company nor the name of the author may be used to
  20  *    endorse or promote products derived from this software without specific
  21  *    prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * RiscBSD kernel project
  36  *
  37  * cpu.c
  38  *
  39  * Probing and configuration for the master CPU
  40  *
  41  * Created      : 10/10/95
  42  */
  43
  44 #include "opt_armfpe.h"
  45 #include "opt_multiprocessor.h"
  46
  47 #include <sys/param.h>
  48
  49 __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.70 2008/10/24 13:23:45 matt Exp $");
  50
  51 #include <sys/systm.h>
  52 #include <sys/malloc.h>
  53 #include <sys/device.h>
  54 #include <sys/proc.h>
  55 #include <sys/conf.h>
  56 #include <uvm/uvm_extern.h>
  57 #include <machine/cpu.h>
  58
  59 #include <arm/cpuconf.h>
  60 #include <arm/undefined.h>
  61
  62 #ifdef ARMFPE
  63 #include <machine/bootconfig.h> /* For boot args */
  64 #include <arm/fpe-arm/armfpe.h>
  65 #endif
  66
  67 #ifdef FPU_VFP
  68 #include <arm/vfpvar.h>
  69 #endif
  70
  71 char cpu_model[256];
  72
  73 /* Prototypes */
  74 void identify_arm_cpu(struct device *dv, struct cpu_info *);
  75
  76 /*
  77  * Identify the master (boot) CPU
  78  */
  79
  80 void
  81 cpu_attach(struct device *dv)
  82 {
  83         int usearmfpe;
  84
  85         usearmfpe = 1;  /* when compiled in, its enabled by default */
  86
  87         curcpu()->ci_dev = dv;
  88
  89         evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC,
  90             NULL, dv->dv_xname, "arm700swibug");
  91
  92         /* Get the CPU ID from coprocessor 15 */
  93
  94         curcpu()->ci_arm_cpuid = cpu_id();
  95         curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK;
  96         curcpu()->ci_arm_cpurev =
  97             curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK;
  98
  99         identify_arm_cpu(dv, curcpu());
 100
 101         if (curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
 102             curcpu()->ci_arm_cpurev < 3) {
 103                 aprint_normal("%s: SA-110 with bugged STM^ instruction\n",
 104                        dv->dv_xname);
 105         }
 106
 107 #ifdef CPU_ARM8
 108         if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
 109                 int clock = arm8_clock_config(0, 0);
 110                 char *fclk;
 111                 aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock);
 112                 aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : "");
 113                 aprint_normal("%s", (clock & 2) ? " sync" : "");
 114                 switch ((clock >> 2) & 3) {
 115                 case 0:
 116                         fclk = "bus clock";
 117                         break;
 118                 case 1:
 119                         fclk = "ref clock";
 120                         break;
 121                 case 3:
 122                         fclk = "pll";
 123                         break;
 124                 default:
 125                         fclk = "illegal";
 126                         break;
 127                 }
 128                 aprint_normal(" fclk source=%s\n", fclk);
 129         }
 130 #endif
 131
 132 #ifdef ARMFPE
 133         /*
 134          * Ok now we test for an FPA
 135          * At this point no floating point emulator has been installed.
 136          * This means any FP instruction will cause undefined exception.
 137          * We install a temporay coproc 1 handler which will modify
 138          * undefined_test if it is called.
 139          * We then try to read the FP status register. If undefined_test
 140          * has been decremented then the instruction was not handled by
 141          * an FPA so we know the FPA is missing. If undefined_test is
 142          * still 1 then we know the instruction was handled by an FPA.
 143          * We then remove our test handler and look at the
 144          * FP status register for identification.
 145          */
 146
 147         /*
 148          * Ok if ARMFPE is defined and the boot options request the
 149          * ARM FPE then it will be installed as the FPE.
 150          * This is just while I work on integrating the new FPE.
 151          * It means the new FPE gets installed if compiled int (ARMFPE
 152          * defined) and also gives me a on/off option when I boot in
 153          * case the new FPE is causing panics.
 154          */
 155
 156
 157         if (boot_args)
 158                 get_bootconf_option(boot_args, "armfpe",
 159                     BOOTOPT_TYPE_BOOLEAN, &usearmfpe);
 160         if (usearmfpe)
 161                 initialise_arm_fpe();
 162 #endif
 163
 164 #ifdef FPU_VFP
 165         vfp_attach();
 166 #endif
 167 }
 168
 169 enum cpu_class {
 170         CPU_CLASS_NONE,
 171         CPU_CLASS_ARM2,
 172         CPU_CLASS_ARM2AS,
 173         CPU_CLASS_ARM3,
 174         CPU_CLASS_ARM6,
 175         CPU_CLASS_ARM7,
 176         CPU_CLASS_ARM7TDMI,
 177         CPU_CLASS_ARM8,
 178         CPU_CLASS_ARM9TDMI,
 179         CPU_CLASS_ARM9ES,
 180         CPU_CLASS_ARM9EJS,
 181         CPU_CLASS_ARM10E,
 182         CPU_CLASS_ARM10EJ,
 183         CPU_CLASS_SA1,
 184         CPU_CLASS_XSCALE,
 185         CPU_CLASS_ARM11J,
 186         CPU_CLASS_ARMV4,
 187 };
 188
 189 static const char * const generic_steppings[16] = {
 190         "rev 0",        "rev 1",        "rev 2",        "rev 3",
 191         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 192         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 193         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 194 };
 195
 196 static const char * const pN_steppings[16] = {
 197         "*p0",  "*p1",  "*p2",  "*p3",  "*p4",  "*p5",  "*p6",  "*p7",
 198         "*p8",  "*p9",  "*p10", "*p11", "*p12", "*p13", "*p14", "*p15",
 199 };
 200
 201 static const char * const sa110_steppings[16] = {
 202         "rev 0",        "step J",       "step K",       "step S",
 203         "step T",       "rev 5",        "rev 6",        "rev 7",
 204         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 205         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 206 };
 207
 208 static const char * const sa1100_steppings[16] = {
 209         "rev 0",        "step B",       "step C",       "rev 3",
 210         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 211         "step D",       "step E",       "rev 10"        "step G",
 212         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 213 };
 214
 215 static const char * const sa1110_steppings[16] = {
 216         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 217         "step B-0",     "step B-1",     "step B-2",     "step B-3",
 218         "step B-4",     "step B-5",     "rev 10",       "rev 11",
 219         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 220 };
 221
 222 static const char * const ixp12x0_steppings[16] = {
 223         "(IXP1200 step A)",             "(IXP1200 step B)",
 224         "rev 2",                        "(IXP1200 step C)",
 225         "(IXP1200 step D)",             "(IXP1240/1250 step A)",
 226         "(IXP1240 step B)",             "(IXP1250 step B)",
 227         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 228         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 229 };
 230
 231 static const char * const xscale_steppings[16] = {
 232         "step A-0",     "step A-1",     "step B-0",     "step C-0",
 233         "step D-0",     "rev 5",        "rev 6",        "rev 7",
 234         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 235         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 236 };
 237
 238 static const char * const i80321_steppings[16] = {
 239         "step A-0",     "step B-0",     "rev 2",        "rev 3",
 240         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 241         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 242         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 243 };
 244
 245 static const char * const i80219_steppings[16] = {
 246         "step A-0",     "rev 1",        "rev 2",        "rev 3",
 247         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 248         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 249         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 250 };
 251
 252 /* Steppings for PXA2[15]0 */
 253 static const char * const pxa2x0_steppings[16] = {
 254         "step A-0",     "step A-1",     "step B-0",     "step B-1",
 255         "step B-2",     "step C-0",     "rev 6",        "rev 7",
 256         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 257         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 258 };
 259
 260 /* Steppings for PXA255/26x.
 261  * rev 5: PXA26x B0, rev 6: PXA255 A0
 262  */
 263 static const char * const pxa255_steppings[16] = {
 264         "rev 0",        "rev 1",        "rev 2",        "step A-0",
 265         "rev 4",        "step B-0",     "step A-0",     "rev 7",
 266         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 267         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 268 };
 269
 270 /* Stepping for PXA27x */
 271 static const char * const pxa27x_steppings[16] = {
 272         "step A-0",     "step A-1",     "step B-0",     "step B-1",
 273         "step C-0",     "rev 5",        "rev 6",        "rev 7",
 274         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 275         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 276 };
 277
 278 static const char * const ixp425_steppings[16] = {
 279         "step 0",       "rev 1",        "rev 2",        "rev 3",
 280         "rev 4",        "rev 5",        "rev 6",        "rev 7",
 281         "rev 8",        "rev 9",        "rev 10",       "rev 11",
 282         "rev 12",       "rev 13",       "rev 14",       "rev 15",
 283 };
 284
 285 struct cpuidtab {
 286         u_int32_t       cpuid;
 287         enum            cpu_class cpu_class;
 288         const char      *cpu_name;
 289         const char * const *cpu_steppings;
 290 };
 291
 292 const struct cpuidtab cpuids[] = {
 293         { CPU_ID_ARM2,          CPU_CLASS_ARM2,         "ARM2",
 294           generic_steppings },
 295         { CPU_ID_ARM250,        CPU_CLASS_ARM2AS,       "ARM250",
 296           generic_steppings },
 297
 298         { CPU_ID_ARM3,          CPU_CLASS_ARM3,         "ARM3",
 299           generic_steppings },
 300
 301         { CPU_ID_ARM600,        CPU_CLASS_ARM6,         "ARM600",
 302           generic_steppings },
 303         { CPU_ID_ARM610,        CPU_CLASS_ARM6,         "ARM610",
 304           generic_steppings },
 305         { CPU_ID_ARM620,        CPU_CLASS_ARM6,         "ARM620",
 306           generic_steppings },
 307
 308         { CPU_ID_ARM700,        CPU_CLASS_ARM7,         "ARM700",
 309           generic_steppings },
 310         { CPU_ID_ARM710,        CPU_CLASS_ARM7,         "ARM710",
 311           generic_steppings },
 312         { CPU_ID_ARM7500,       CPU_CLASS_ARM7,         "ARM7500",
 313           generic_steppings },
 314         { CPU_ID_ARM710A,       CPU_CLASS_ARM7,         "ARM710a",
 315           generic_steppings },
 316         { CPU_ID_ARM7500FE,     CPU_CLASS_ARM7,         "ARM7500FE",
 317           generic_steppings },
 318         { CPU_ID_ARM710T,       CPU_CLASS_ARM7TDMI,     "ARM710T",
 319           generic_steppings },
 320         { CPU_ID_ARM720T,       CPU_CLASS_ARM7TDMI,     "ARM720T",
 321           generic_steppings },
 322         { CPU_ID_ARM740T8K,     CPU_CLASS_ARM7TDMI, "ARM740T (8 KB cache)",
 323           generic_steppings },
 324         { CPU_ID_ARM740T4K,     CPU_CLASS_ARM7TDMI, "ARM740T (4 KB cache)",
 325           generic_steppings },
 326
 327         { CPU_ID_ARM810,        CPU_CLASS_ARM8,         "ARM810",
 328           generic_steppings },
 329
 330         { CPU_ID_ARM920T,       CPU_CLASS_ARM9TDMI,     "ARM920T",
 331           generic_steppings },
 332         { CPU_ID_ARM922T,       CPU_CLASS_ARM9TDMI,     "ARM922T",
 333           generic_steppings },
 334         { CPU_ID_ARM926EJS,     CPU_CLASS_ARM9EJS,      "ARM926EJ-S",
 335           generic_steppings },
 336         { CPU_ID_ARM940T,       CPU_CLASS_ARM9TDMI,     "ARM940T",
 337           generic_steppings },
 338         { CPU_ID_ARM946ES,      CPU_CLASS_ARM9ES,       "ARM946E-S",
 339           generic_steppings },
 340         { CPU_ID_ARM966ES,      CPU_CLASS_ARM9ES,       "ARM966E-S",
 341           generic_steppings },
 342         { CPU_ID_ARM966ESR1,    CPU_CLASS_ARM9ES,       "ARM966E-S",
 343           generic_steppings },
 344         { CPU_ID_TI925T,        CPU_CLASS_ARM9TDMI,     "TI ARM925T",
 345           generic_steppings },
 346
 347         { CPU_ID_ARM1020E,      CPU_CLASS_ARM10E,       "ARM1020E",
 348           generic_steppings },
 349         { CPU_ID_ARM1022ES,     CPU_CLASS_ARM10E,       "ARM1022E-S",
 350           generic_steppings },
 351         { CPU_ID_ARM1026EJS,    CPU_CLASS_ARM10EJ,      "ARM1026EJ-S",
 352           generic_steppings },
 353
 354         { CPU_ID_SA110,         CPU_CLASS_SA1,          "SA-110",
 355           sa110_steppings },
 356         { CPU_ID_SA1100,        CPU_CLASS_SA1,          "SA-1100",
 357           sa1100_steppings },
 358         { CPU_ID_SA1110,        CPU_CLASS_SA1,          "SA-1110",
 359           sa1110_steppings },
 360
 361         { CPU_ID_IXP1200,       CPU_CLASS_SA1,          "IXP1200",
 362           ixp12x0_steppings },
 363
 364         { CPU_ID_80200,         CPU_CLASS_XSCALE,       "i80200",
 365           xscale_steppings },
 366
 367         { CPU_ID_80321_400,     CPU_CLASS_XSCALE,       "i80321 400MHz",
 368           i80321_steppings },
 369         { CPU_ID_80321_600,     CPU_CLASS_XSCALE,       "i80321 600MHz",
 370           i80321_steppings },
 371         { CPU_ID_80321_400_B0,  CPU_CLASS_XSCALE,       "i80321 400MHz",
 372           i80321_steppings },
 373         { CPU_ID_80321_600_B0,  CPU_CLASS_XSCALE,       "i80321 600MHz",
 374           i80321_steppings },
 375
 376         { CPU_ID_80219_400,     CPU_CLASS_XSCALE,       "i80219 400MHz",
 377           i80219_steppings },
 378         { CPU_ID_80219_600,     CPU_CLASS_XSCALE,       "i80219 600MHz",
 379           i80219_steppings },
 380
 381         { CPU_ID_PXA27X,        CPU_CLASS_XSCALE,       "PXA27x",
 382           pxa27x_steppings },
 383         { CPU_ID_PXA250A,       CPU_CLASS_XSCALE,       "PXA250",
 384           pxa2x0_steppings },
 385         { CPU_ID_PXA210A,       CPU_CLASS_XSCALE,       "PXA210",
 386           pxa2x0_steppings },
 387         { CPU_ID_PXA250B,       CPU_CLASS_XSCALE,       "PXA250",
 388           pxa2x0_steppings },
 389         { CPU_ID_PXA210B,       CPU_CLASS_XSCALE,       "PXA210",
 390           pxa2x0_steppings },
 391         { CPU_ID_PXA250C,       CPU_CLASS_XSCALE,       "PXA255/26x",
 392           pxa255_steppings },
 393         { CPU_ID_PXA210C,       CPU_CLASS_XSCALE,       "PXA210",
 394           pxa2x0_steppings },
 395
 396         { CPU_ID_IXP425_533,    CPU_CLASS_XSCALE,       "IXP425 533MHz",
 397           ixp425_steppings },
 398         { CPU_ID_IXP425_400,    CPU_CLASS_XSCALE,       "IXP425 400MHz",
 399           ixp425_steppings },
 400         { CPU_ID_IXP425_266,    CPU_CLASS_XSCALE,       "IXP425 266MHz",
 401           ixp425_steppings },
 402
 403         { CPU_ID_ARM1136JS,     CPU_CLASS_ARM11J,       "ARM1136J-S r0",
 404           pN_steppings },
 405         { CPU_ID_ARM1136JSR1,   CPU_CLASS_ARM11J,       "ARM1136J-S r1",
 406           pN_steppings },
 407         { CPU_ID_ARM1176JS,     CPU_CLASS_ARM11J,       "ARM1176J-S r0",
 408           pN_steppings },
 409         { CPU_ID_CORTEXA8R1,    CPU_CLASS_ARM11J,       "Cortex-A8 r1",
 410           pN_steppings },
 411         { CPU_ID_CORTEXA8R2,    CPU_CLASS_ARM11J,       "Cortex-A8 r2",
 412           pN_steppings },
 413
 414         { CPU_ID_FA526,         CPU_CLASS_ARMV4,        "FA526",
 415           generic_steppings },
 416
 417         { 0, CPU_CLASS_NONE, NULL, NULL }
 418 };
 419
 420 struct cpu_classtab {
 421         const char      *class_name;
 422         const char      *class_option;
 423 };
 424
 425 const struct cpu_classtab cpu_classes[] = {
 426         { "unknown",    NULL },                 /* CPU_CLASS_NONE */
 427         { "ARM2",       "CPU_ARM2" },           /* CPU_CLASS_ARM2 */
 428         { "ARM2as",     "CPU_ARM250" },         /* CPU_CLASS_ARM2AS */
 429         { "ARM3",       "CPU_ARM3" },           /* CPU_CLASS_ARM3 */
 430         { "ARM6",       "CPU_ARM6" },           /* CPU_CLASS_ARM6 */
 431         { "ARM7",       "CPU_ARM7" },           /* CPU_CLASS_ARM7 */
 432         { "ARM7TDMI",   "CPU_ARM7TDMI" },       /* CPU_CLASS_ARM7TDMI */
 433         { "ARM8",       "CPU_ARM8" },           /* CPU_CLASS_ARM8 */
 434         { "ARM9TDMI",   NULL },                 /* CPU_CLASS_ARM9TDMI */
 435         { "ARM9E-S",    "CPU_ARM9E" },          /* CPU_CLASS_ARM9ES */
 436         { "ARM9EJ-S",   "CPU_ARM9E" },          /* CPU_CLASS_ARM9EJS */
 437         { "ARM10E",     "CPU_ARM10" },          /* CPU_CLASS_ARM10E */
 438         { "ARM10EJ",    "CPU_ARM10" },          /* CPU_CLASS_ARM10EJ */
 439         { "SA-1",       "CPU_SA110" },          /* CPU_CLASS_SA1 */
 440         { "XScale",     "CPU_XSCALE_..." },     /* CPU_CLASS_XSCALE */
 441         { "ARM11J",     "CPU_ARM11" },          /* CPU_CLASS_ARM11J */
 442         { "ARMv4",      "CPU_ARMV4" },          /* CPU_CLASS_ARMV4 */
 443 };
 444
 445 /*
 446  * Report the type of the specified arm processor. This uses the generic and
 447  * arm specific information in the CPU structure to identify the processor.
 448  * The remaining fields in the CPU structure are filled in appropriately.
 449  */
 450
 451 static const char * const wtnames[] = {
 452         "write-through",
 453         "write-back",
 454         "write-back",
 455         "**unknown 3**",
 456         "**unknown 4**",
 457         "write-back-locking",           /* XXX XScale-specific? */
 458         "write-back-locking-A",
 459         "write-back-locking-B",
 460         "**unknown 8**",
 461         "**unknown 9**",
 462         "**unknown 10**",
 463         "**unknown 11**",
 464         "**unknown 12**",
 465         "**unknown 13**",
 466         "write-back-locking-C",
 467         "**unknown 15**",
 468 };
 469
 470 void
 471 identify_arm_cpu(struct device *dv, struct cpu_info *ci)
 472 {
 473         u_int cpuid;
 474         enum cpu_class cpu_class = CPU_CLASS_NONE;
 475         int i;
 476         const char *steppingstr;
 477
 478         cpuid = ci->ci_arm_cpuid;
 479
 480         if (cpuid == 0) {
 481                 aprint_error("Processor failed probe - no CPU ID\n");
 482                 return;
 483         }
 484
 485         for (i = 0; cpuids[i].cpuid != 0; i++)
 486                 if (cpuids[i].cpuid == (cpuid & CPU_ID_CPU_MASK)) {
 487                         cpu_class = cpuids[i].cpu_class;
 488                         steppingstr = cpuids[i].cpu_steppings[cpuid &
 489                             CPU_ID_REVISION_MASK],
 490                         sprintf(cpu_model, "%s%s%s (%s core)",
 491                             cpuids[i].cpu_name,
 492                             steppingstr[0] == '*' ? "" : " ",
 493                             &steppingstr[steppingstr[0] == '*'],
 494                             cpu_classes[cpu_class].class_name);
 495                         break;
 496                 }
 497
 498         if (cpuids[i].cpuid == 0)
 499                 sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid);
 500
 501         aprint_naive(": %s\n", cpu_model);
 502         aprint_normal(": %s\n", cpu_model);
 503
 504         aprint_normal("%s:", dv->dv_xname);
 505
 506         switch (cpu_class) {
 507         case CPU_CLASS_ARM6:
 508         case CPU_CLASS_ARM7:
 509         case CPU_CLASS_ARM7TDMI:
 510         case CPU_CLASS_ARM8:
 511                 if ((ci->ci_ctrl & CPU_CONTROL_IDC_ENABLE) == 0)
 512                         aprint_normal(" IDC disabled");
 513                 else
 514                         aprint_normal(" IDC enabled");
 515                 break;
 516         case CPU_CLASS_ARM9TDMI:
 517         case CPU_CLASS_ARM9ES:
 518         case CPU_CLASS_ARM9EJS:
 519         case CPU_CLASS_ARM10E:
 520         case CPU_CLASS_ARM10EJ:
 521         case CPU_CLASS_SA1:
 522         case CPU_CLASS_XSCALE:
 523         case CPU_CLASS_ARM11J:
 524         case CPU_CLASS_ARMV4:
 525                 if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
 526                         aprint_normal(" DC disabled");
 527                 else
 528                         aprint_normal(" DC enabled");
 529                 if ((ci->ci_ctrl & CPU_CONTROL_IC_ENABLE) == 0)
 530                         aprint_normal(" IC disabled");
 531                 else
 532                         aprint_normal(" IC enabled");
 533                 break;
 534         default:
 535                 break;
 536         }
 537         if ((ci->ci_ctrl & CPU_CONTROL_WBUF_ENABLE) == 0)
 538                 aprint_normal(" WB disabled");
 539         else
 540                 aprint_normal(" WB enabled");
 541
 542         if (ci->ci_ctrl & CPU_CONTROL_LABT_ENABLE)
 543                 aprint_normal(" LABT");
 544         else
 545                 aprint_normal(" EABT");
 546
 547         if (ci->ci_ctrl & CPU_CONTROL_BPRD_ENABLE)
 548                 aprint_normal(" branch prediction enabled");
 549
 550         aprint_normal("\n");
 551
 552         /* Print cache info. */
 553         if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
 554                 goto skip_pcache;
 555
 556         if (arm_pcache_unified) {
 557                 aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n",
 558                     dv->dv_xname, arm_pdcache_size / 1024,
 559                     arm_pdcache_line_size, arm_pdcache_ways,
 560                     wtnames[arm_pcache_type]);
 561         } else {
 562                 aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n",
 563                     dv->dv_xname, arm_picache_size / 1024,
 564                     arm_picache_line_size, arm_picache_ways);
 565                 aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n",
 566                     dv->dv_xname, arm_pdcache_size / 1024,
 567                     arm_pdcache_line_size, arm_pdcache_ways,
 568                     wtnames[arm_pcache_type]);
 569         }
 570
 571  skip_pcache:
 572
 573         switch (cpu_class) {
 574 #ifdef CPU_ARM2
 575         case CPU_CLASS_ARM2:
 576 #endif
 577 #ifdef CPU_ARM250
 578         case CPU_CLASS_ARM2AS:
 579 #endif
 580 #ifdef CPU_ARM3
 581         case CPU_CLASS_ARM3:
 582 #endif
 583 #ifdef CPU_ARM6
 584         case CPU_CLASS_ARM6:
 585 #endif
 586 #ifdef CPU_ARM7
 587         case CPU_CLASS_ARM7:
 588 #endif
 589 #ifdef CPU_ARM7TDMI
 590         case CPU_CLASS_ARM7TDMI:
 591 #endif
 592 #ifdef CPU_ARM8
 593         case CPU_CLASS_ARM8:
 594 #endif
 595 #ifdef CPU_ARM9
 596         case CPU_CLASS_ARM9TDMI:
 597 #endif
 598 #ifdef CPU_ARM9E
 599         case CPU_CLASS_ARM9ES:
 600         case CPU_CLASS_ARM9EJS:
 601 #endif
 602 #ifdef CPU_ARM10
 603         case CPU_CLASS_ARM10E:
 604         case CPU_CLASS_ARM10EJ:
 605 #endif
 606 #if defined(CPU_SA110) || defined(CPU_SA1100) || \
 607     defined(CPU_SA1110) || defined(CPU_IXP12X0)
 608         case CPU_CLASS_SA1:
 609 #endif
 610 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
 611     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)
 612         case CPU_CLASS_XSCALE:
 613 #endif
 614 #if defined(CPU_ARM11)
 615         case CPU_CLASS_ARM11J:
 616 #endif
 617 #if defined(CPU_FA526)
 618         case CPU_CLASS_ARMV4:
 619 #endif
 620                 break;
 621         default:
 622                 if (cpu_classes[cpu_class].class_option == NULL)
 623                         aprint_error("%s: %s does not fully support this CPU."
 624                                "\n", dv->dv_xname, ostype);
 625                 else {
 626                         aprint_error("%s: This kernel does not fully support "
 627                                "this CPU.\n", dv->dv_xname);
 628                         aprint_normal("%s: Recompile with \"options %s\" to "
 629                                "correct this.\n", dv->dv_xname,
 630                                cpu_classes[cpu_class].class_option);
 631                 }
 632                 break;
 633         }
 634
 635 }
 636
 637 /* End of cpu.c */