sys/arch/arm/at91/at91dbgureg.h

   1 /*      $NetBSD: at91dbgureg.h,v 1.2 2008/07/03 01:15:38 matt Exp $     */
   2
   3 /*
   4  * Copyright (c) 2007 Embedtronics Oy
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _AT91DBGUREG_H_
  30 #define _AT91DBGUREG_H_
  31
  32 #define AT91DBGU_BASE   0xFFFFF200      /* DBGU unit base addresses (physical) */
  33 #define AT91DBGU_SIZE   0x200           /* DBGU peripheral address space size */
  34
  35 #define DBGU_CR         0x00UL  /* Control Register                     */
  36 #define DBGU_MR         0x04UL  /* Mode Register                        */
  37 #define DBGU_IER        0x08UL  /* Interrupt Enable Register            */
  38 #define DBGU_IDR        0x0CUL  /* Interrupt Disable Register           */
  39 #define DBGU_IMR        0x10UL  /* Interrupt Mask Register              */
  40 #define DBGU_SR         0x14UL  /* Status Register                      */
  41 #define DBGU_RHR        0x18UL  /* Receive Holding Register             */
  42 #define DBGU_THR        0x1CUL  /* Transmit Holding Register            */
  43 #define DBGU_BRGR       0x20UL  /* Baud Rate Generator Register         */
  44 #define DBGU_CIDR       0x40UL  /* Chip ID Register                     */
  45 #define DBGU_EXID       0x44UL  /* Chip ID Extension Register           */
  46 #define DBGU_FNR        0x48UL  /* Force NTRST Register                 */
  47 #define DBGU_PDC        0x100UL
  48
  49 /* Control Register bits: */
  50 #define DBGU_CR_RSTSTA          0x100   /* 1 = reset the status bits    */
  51 #define DBGU_CR_TXDIS           0x080   /* 1 = disable transmitter      */
  52 #define DBGU_CR_TXEN            0x040   /* 1 = enable transmitter       */
  53 #define DBGU_CR_RXDIS           0x020   /* 1 = disable receiver         */
  54 #define DBGU_CR_RXEN            0x010   /* 1 = enable receiver          */
  55 #define DBGU_CR_RSTTX           0x008   /* 1 = reset transmitter        */
  56 #define DBGU_CR_RSTRX           0x004   /* 1 = reset receiver           */
  57
  58 /* Mode Register bits: */
  59 #define DBGU_MR_CHMODE          0xC000  /* channel mode                 */
  60 #define DBGU_MR_CHMOD_NORMAL    0x0000
  61 #define DBGU_MR_CHMOD_ECHO      0x4000
  62 #define DBGU_MR_CHMOD_LOCAL_LOOP 0x8000
  63 #define DBGU_MR_CHMOD_REMOTE_LOOP 0xC000
  64
  65 #define DBGU_MR_PAR             0x0E00  /* parity type                  */
  66 #define DBGU_MR_PAR_EVEN        0x0000
  67 #define DBGU_MR_PAR_ODD         0x0200
  68 #define DBGU_MR_PAR_SPACE       0x0400
  69 #define DBGU_MR_PAR_MARK        0x0600
  70 #define DBGU_MR_PAR_NONE        0x0800
  71
  72 /* Interrupt bits: */
  73 #define DBGU_INT_COMMRX         0x80000000
  74 #define DBGU_INT_COMMTX         0x40000000
  75 #define DBGU_INT_RXBUFF         0x00001000
  76 #define DBGU_INT_TXBUFE         0x00000800
  77 #define DBGU_INT_TXEMPTY        0x00000200
  78 #define DBGU_INT_PARE           0x00000080
  79 #define DBGU_INT_FRAME          0x00000040
  80 #define DBGU_INT_OVRE           0x00000020
  81 #define DBGU_INT_ENDTX          0x00000010
  82 #define DBGU_INT_ENDRX          0x00000008
  83 #define DBGU_INT_TXRDY          0x00000002
  84 #define DBGU_INT_RXRDY          0x00000001
  85
  86 /* Status register bits: */
  87 #define DBGU_SR_COMMRX          0x80000000
  88 #define DBGU_SR_COMMTX          0x40000000
  89 #define DBGU_SR_RXBUFF          0x00001000
  90 #define DBGU_SR_TXBUFE          0x00000800
  91 #define DBGU_SR_TXEMPTY         0x00000200
  92 #define DBGU_SR_PARE            0x00000080
  93 #define DBGU_SR_FRAME           0x00000040
  94 #define DBGU_SR_OVRE            0x00000020
  95 #define DBGU_SR_ENDTX           0x00000010
  96 #define DBGU_SR_ENDRX           0x00000008
  97 #define DBGU_SR_TXRDY           0x00000002
  98 #define DBGU_SR_RXRDY           0x00000001
  99
 100
 101 /* Chip ID Register bits: */
 102 #define DBGU_CIDR_EXT           0x80000000      /* 1 = Extended Chip ID exists */
 103
 104 #define DBGU_CIDR_NVPTYP        0x70000000      /* Nonvolatile Pgm Mem Type */
 105 #define DBGU_CIDR_NVPTYP_ROM    0x00000000
 106 #define DBGU_CIDR_NVPTYP_ROMLESS 0x10000000
 107 #define DBGU_CIDR_NVPTYP_SRAM   0x40000000
 108 #define DBGU_CIDR_NVPTYP_FLASH  0x20000000
 109 #define DBGU_CIDR_NVTYP_ROM_FLASH 0x30000000    /* NVPSIZ is ROM size, NVPSIZ2 is Flash Size */
 110
 111 #define DBGU_CIDR_ARCH          0x0FF00000      /* Architecture identifier      */
 112 #define DBGU_CIDR_ARCH_AT91SAM9XX 0x01900000    /* AT91SAM9xx Series */
 113 #define DBGU_CIDR_ARCH_AT91SAM9XEXX 0x02900000  /* AT91SAM9XExx Series */
 114 #define DBGU_CIDR_ARCH_AT91X34  0x03400000      /* AT91x34 Series */
 115 #define DBGU_CIDR_ARCH_CAP9     0x03900000      /* CAP9 Series */
 116 #define DBGU_CIDR_ARCH_AT91X40  0x04000000      /* AT91x40 Series */
 117 #define DBGU_CIDR_ARCH_AT91X42  0x04200000      /* AT91x42 Series */
 118 #define DBGU_CIDR_ARCH_AT91X55  0x05500000      /* AT91x55 Series */
 119 #define DBGU_CIDR_ARCH_AT91SAM7AXX 0x06000000   /* AT91SAM7Axx Series */
 120 #define DBGU_CIDR_ARCH_AT91X63  0x06300000      /* AT91x63 Series */
 121 #define DBGU_CIDR_ARCH_AT91SAM7SXX 0x07000000   /* AT91SAM7Sxx Series */
 122 #define DBGU_CIDR_ARCH_AT91SAM7XCXX 0x07100000  /* AT91SAM7XCxx Series */
 123 #define DBGU_CIDR_ARCH_AT91SAM7SEXX 0x07200000  /* AT91SAM7SExx Series */
 124 #define DBGU_CIDR_ARCH_AT91SAM7LXX 0x07300000   /* AT91SAM7LExx Series */
 125 #define DBGU_CIDR_ARCH_AT91SAM7XXX 0x07500000   /* AT91SAM7Xxx Series */
 126 #define DBGU_CIDR_ARCH_AT91X92  0x09200000      /* AT91x92 Series */
 127 #define DBGU_CIDR_ARCH_AT75CXX  0x0F000000      /* AT75Cxx Series */
 128
 129 #define DBGU_CIDR_SRAMSIZ       0x000F0000      /* Internal SRAM Size   */
 130 #define DBGU_CIDR_SRAMSIZ_1K    0x00010000
 131 #define DBGU_CIDR_SRAMSIZ_2K    0x00020000
 132 #define DBGU_CIDR_SRAMSIZ_4K    0x00050000
 133 #define DBGU_CIDR_SRAMSIZ_8K    0x00080000
 134 #define DBGU_CIDR_SRAMSIZ_16K   0x00090000
 135 #define DBGU_CIDR_SRAMSIZ_32K   0x000A0000
 136 #define DBGU_CIDR_SRAMSIZ_64K   0x000B0000
 137 #define DBGU_CIDR_SRAMSIZ_128K  0x000C0000
 138 #define DBGU_CIDR_SRAMSIZ_256K  0x000D0000
 139 #define DBGU_CIDR_SRAMSIZ_96K   0x000E0000
 140 #define DBGU_CIDR_SRAMSIZ_512K  0x000F0000
 141
 142 #define DBGU_CIDR_NVPSIZ        0x00000F00      /* Nonvolatile Pgm Mem Size */
 143 #define DBGU_CIDR_NVPSIZ_NONE   0x00000000
 144 #define DBGU_CIDR_NVPSIZ_8K     0x00000100
 145 #define DBGU_CIDR_NVPSIZ_16K    0x00000200
 146 #define DBGU_CIDR_NVPSIZ_32K    0x00000300
 147 #define DBGU_CIDR_NVPSIZ_64K    0x00000500
 148 #define DBGU_CIDR_NVPSIZ_128K   0x00000700
 149 #define DBGU_CIDR_NVPSIZ_256K   0x00000900
 150 #define DBGU_CIDR_NVPSIZ_512K   0x00000A00
 151 #define DBGU_CIDR_NVPSIZ_1024K  0x00000C00
 152 #define DBGU_CIDR_NVPSIZ_2048K  0x00000E00
 153
 154 #define DBGU_CIDR_NPVSIZ2       0x0000F000      /* Nonvolatile Pgm 2 Mem Size */
 155 #define DBGU_CIDR_NVPSIZ2_NONE  0x00000000
 156 #define DBGU_CIDR_NVPSIZ2_8K    0x00001000
 157 #define DBGU_CIDR_NVPSIZ2_16K   0x00002000
 158 #define DBGU_CIDR_NVPSIZ2_32K   0x00003000
 159 #define DBGU_CIDR_NVPSIZ2_64K   0x00005000
 160 #define DBGU_CIDR_NVPSIZ2_128K  0x00007000
 161 #define DBGU_CIDR_NVPSIZ2_256K  0x00009000
 162 #define DBGU_CIDR_NVPSIZ2_512K  0x0000A000
 163 #define DBGU_CIDR_NVPSIZ2_1024K 0x0000C000
 164 #define DBGU_CIDR_NVPSIZ2_2048K 0x0000E000
 165
 166 #define DBGU_CIDR_EPROC         0x000000E0      /* Embedded Processor ID */
 167 #define DBGU_CIDR_EPROC_946ES   0x00000020
 168 #define DBGU_CIDR_EPROC_7TDMI   0x00000040
 169 #define DBGU_CIDR_EPROC_920T    0x00000080
 170 #define DBGU_CIDR_EPROC_926EJS  0x000000E0
 171
 172 #define DBGU_CIDR_VERSION       0x0000001F      /* version of the device */
 173
 174 #define DBGU_CIDR_AT91RM9200    0x09290781
 175 #define DBGU_CIDR_AT91SAM9260   0x019803A0
 176 #define DBGU_CIDR_AT91SAM9261   0x019703A0
 177 #define DBGU_CIDR_AT91SAM9263   0x019607A0
 178
 179 #define AT91RM9200_CHIP_ID      DBGU_CIDR_AT91RM9200
 180 #define AT91SAM9260_CHIP_ID     DBGU_CIDR_AT91SAM9260
 181 #define AT91SAM9261_CHIP_ID     DBGU_CIDR_AT91SAM9261
 182 #define AT91SAM9263_CHIP_ID     DBGU_CIDR_AT91SAM9263
 183
 184 #define DBGUREG(reg)            *((volatile u_int32_t*)(AT91DBGU_BASE + (reg)))
 185
 186 #define DBGU_INIT(mstclk, speed) do {                                   \
 187   DBGUREG(DBGU_PDC + PDC_PTCR) = PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS;     \
 188   DBGUREG(DBGU_BRGR) = ((mstclk) / 16 + (speed) / 2) / (speed);         \
 189   DBGUREG(DBGU_MR) = DBGU_MR_PAR_NONE;                                  \
 190   DBGUREG(DBGU_CR) = DBGU_CR_RSTSTA | DBGU_CR_RSTTX | DBGU_CR_RSTRX;    \
 191   DBGUREG(DBGU_CR) = DBGU_CR_TXEN | DBGU_CR_RXEN;                       \
 192   (void)DBGUREG(DBGU_SR);                                               \
 193 } while (/*CONSTCOND*/0)
 194
 195 #define DBGU_PUTC(ch) do {                                              \
 196   int s = splserial();                                                  \
 197   while ((DBGUREG(DBGU_SR) & DBGU_SR_TXRDY) == 0) {                     \
 198     splx(s); s = splserial();                                           \
 199   };                                                                    \
 200   DBGUREG(DBGU_THR) = ch;                                               \
 201   splx(s);                                                              \
 202 } while (/*CONSTCOND*/0)
 203
 204 #define DBGU_PEEKC() ((DBGUREG(DBGU_SR) & DBGU_SR_RXRDY) ? DBGUREG(DBGU_RHR) : -1)
 205
 206 #define DBGU_PUTS(string) do {                                          \
 207   const char *_ptr = (string);                                          \
 208   while (*_ptr) {                                                       \
 209     DBGU_PUTC(*_ptr);                                                   \
 210     _ptr++;                                                             \
 211   }                                                                     \
 212 } while (/*CONSTCOND*/0)
 213
 214 #endif  // _AT91DBGUREG_H_
 215