1 /* $Id: at91emacreg.h,v 1.3 2009/10/23 06:53:13 snj Exp $ */
2 /* $NetBSD: at91emacreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
4 * Copyright (c) 2007 Embedtronics Oy
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _AT91EMACREG_H_
31 #define _AT91EMACREG_H_ 1
33 /* Ethernet MAC (EMAC),
34 * at91rm9200.pdf, page 573 */
36 #define ETH_CTL 0x00U /* 0x00: Control Register */
37 #define ETH_CFG 0x04U /* 0x04: Configuration Register */
38 #define ETH_SR 0x08U /* 0x08: Status Register */
39 #define ETH_TAR 0x0CU /* 0x0C: Transmit Address Register */
40 #define ETH_TCR 0x10U /* 0x10: Transmit Control Register */
41 #define ETH_TSR 0x14U /* 0x14: Transmit Status Register */
42 #define ETH_RBQP 0x18U /* 0x18: Receive Buffer Queue Pointer */
43 #define ETH_RSR 0x20U /* 0x20: Receive Status Register */
44 #define ETH_ISR 0x24U /* 0x24: Interrupt Status Register */
45 #define ETH_IER 0x28U /* 0x28: Interrupt Enable Register */
46 #define ETH_IDR 0x2CU /* 0x2C: Interrupt Disable Register */
47 #define ETH_IMR 0x30U /* 0x30: Interrupt Mask Register */
48 #define ETH_MAN 0x34U /* 0x34: PHY Maintenance Register */
50 #define ETH_FRA 0x40U /* 0x40: Frames Transmitted OK */
51 #define ETH_SCOL 0x44U /* 0x44: Single Collision Frames */
52 #define ETH_MCOL 0x48U /* 0x48: Multiple Collision Frames */
53 #define ETH_OK 0x4CU /* 0x4C: Frames Received OK */
54 #define ETH_SEQE 0x50U /* 0x50: Frame Check Sequence Errors */
55 #define ETH_ALE 0x54U /* 0x54: Alignment Errors */
56 #define ETH_DTE 0x58U /* 0x58: Deferred Transmission Frame */
57 #define ETH_LCOL 0x5CU /* 0x5C: Late Collisions */
58 #define ETH_ECOL 0x60U /* 0x60: Excessive Collisions */
59 #define ETH_CSE 0x64U /* 0x64: Carrier Sense Errors */
60 #define ETH_TUE 0x68U /* 0x68: Transmit Underrun Errors */
61 #define ETH_CDE 0x6CU /* 0x6C: Code Errors */
62 #define ETH_ELR 0x70U /* 0x70: Excessive Length Errors */
63 #define ETH_RJB 0x74U /* 0x74: Receive Jabbers */
64 #define ETH_USF 0x78U /* 0x78: Undersize Frames */
65 #define ETH_SQEE 0x7CU /* 0x7C: SQE Test Errors */
66 #define ETH_DRFC 0x80U /* 0x80: Discarded RX Frames */
68 #define ETH_HSH 0x90U /* 0x90: Hash Address High */
69 #define ETH_HSL 0x94U /* 0x94: Hash Address Low */
71 #define ETH_SA1L 0x98U /* 0x98: Specific Address 1 Low */
72 #define ETH_SA1H 0x9CU /* 0x9C: Specific Address 1 High */
74 #define ETH_SA2L 0xA0U /* 0xA0: Specific Address 2 Low */
75 #define ETH_SA2H 0xA4U /* 0xA4: Specific Address 2 High */
77 #define ETH_SA3L 0xA8U /* 0xA8: Specific Address 3 Low */
78 #define ETH_SA3H 0xACU /* 0xAC: Specific Address 3 High */
80 #define ETH_SA4L 0xB0U /* 0xB0: Specific Address 4 Low */
81 #define ETH_SA4H 0xB4U /* 0xB4: Specific Address 4 High */
84 /* Control Register bits: */
85 #define ETH_CTL_BP 0x100U /* 1 = back pressure enabled */
86 #define ETH_CTL_WES 0x080U /* 1 = statistics registers writeable */
87 #define ETH_CTL_ISR 0x040U /* 1 = increment statistics registers */
88 #define ETH_CTL_CSR 0x020U /* 1 = clear statistics registers */
89 #define ETH_CTL_MPE 0x010U /* 1 = management port enabled */
90 #define ETH_CTL_TE 0x008U /* 1 = transmit enable */
91 #define ETH_CTL_RE 0x004U /* 1 = receive enable */
92 #define ETH_CTL_LBL 0x002U /* 1 = local loopback enabled */
93 #define ETH_CTL_LB 0x001U /* 1 = loopback signal is at high level */
96 /* Configuration Register bits: */
97 #define ETH_CFG_RMII 0x2000U /* 1 = enable RMII (Reduce MII) */
98 #define ETH_CFG_RTY 0x1000U /* 1 = retry test enabled */
100 #define ETH_CFG_CLK 0x0C00U /* clock */
101 #define ETH_CFG_CLK_8 0x0000U
102 #define ETH_CFG_CLK_16 0x0400U
103 #define ETH_CFG_CLK_32 0x0800U
104 #define ETH_CFG_CLK_64 0x0C00U
106 #define ETH_CFG_EAE 0x0200U /* 1 = external address match enable */
107 #define ETH_CFG_BIG 0x0100U /* 1 = receive up to 1522 bytes (VLAN) */
108 #define ETH_CFG_UNI 0x0080U /* 1 = enable unicast hash */
109 #define ETH_CFG_MTI 0x0040U /* 1 = enable multicast hash */
110 #define ETH_CFG_NBC 0x0020U /* 1 = ignore received broadcasts */
111 #define ETH_CFG_CAF 0x0010U /* 1 = receive all valid frames */
112 #define ETH_CFG_BR 0x0004U
113 #define ETH_CFG_FD 0x0002U /* 1 = force full duplex */
114 #define ETH_CFG_SPD 0x0001U /* 1 = 100 Mbps */
117 /* Status Register bits: */
118 #define ETH_SR_IDLE 0x0004U /* 1 = PHY logic is running */
119 #define ETH_SR_MDIO 0x0002U /* 1 = MDIO pin set */
120 #define ETH_SR_LINK 0x0001U
123 /* Transmit Control Register bits: */
124 #define ETH_TCR_NCRC 0x8000U /* 1 = don't append CRC */
125 #define ETH_TCR_LEN 0x07FFU /* transmit frame length */
128 /* Transmit Status Register bits: */
129 #define ETH_TSR_UND 0x40U /* 1 = transmit underrun detected */
130 #define ETH_TSR_COMP 0x20U /* 1 = transmit complete */
131 #define ETH_TSR_BNQ 0x10U /* 1 = transmit buffer not queued */
132 #define ETH_TSR_IDLE 0x08U /* 1 = transmitter idle */
133 #define ETH_TSR_RLE 0x04U /* 1 = retry limit exceeded */
134 #define ETH_TSR_COL 0x02U /* 1 = collision occurred */
135 #define ETH_TSR_OVR 0x01U /* 1 = transmit buffer overrun */
138 /* Receive Status Register bits: */
139 #define ETH_RSR_OVR 0x04U /* 1 = RX overrun */
140 #define ETH_RSR_REC 0x02U /* 1 = frame received */
141 #define ETH_RSR_BNA 0x01U /* 1 = buffer not available */
144 /* Interrupt bits: */
145 #define ETH_ISR_ABT 0x0800U /* 1 = abort during DMA transfer */
146 #define ETH_ISR_ROVR 0x0400U /* 1 = RX overrun */
147 #define ETH_ISR_LINK 0x0200U /* 1 = link pin changed */
148 #define ETH_ISR_TIDLE 0x0100U /* 1 = transmitter idle */
149 #define ETH_ISR_TCOM 0x0080U /* 1 = transmit complete */
150 #define ETH_ISR_TBRE 0x0040U /* 1 = transmit buffer register empty */
151 #define ETH_ISR_RTRY 0x0020U /* 1 = retry limit exceeded */
152 #define ETH_ISR_TUND 0x0010U /* 1 = transmit buffer underrun */
153 #define ETH_ISR_TOVR 0x0008U /* 1 = transmit buffer overrun */
154 #define ETH_ISR_RBNA 0x0004U /* 1 = receive buffer not available */
155 #define ETH_ISR_RCOM 0x0002U /* 1 = receive complete */
156 #define ETH_ISR_DONE 0x0001U /* 1 = management done */
159 /* PHY Maintenance Register bits: */
160 #define ETH_MAN_LOW 0x80000000U /* must not be set */
161 #define ETH_MAN_HIGH 0x40000000U /* must be set */
163 #define ETH_MAN_RW 0x30000000U
164 #define ETH_MAN_RW_RD 0x20000000U
165 #define ETH_MAN_RW_WR 0x10000000U
167 #define ETH_MAN_PHYA 0x0F800000U /* PHY address (normally 0) */
168 #define ETH_MAN_PHYA_SHIFT 23U
169 #define ETH_MAN_REGA 0x007C0000U
170 #define ETH_MAN_REGA_SHIFT 18U
171 #define ETH_MAN_CODE 0x00030000U /* must be 10 */
172 #define ETH_MAN_CODE_IEEE802_3 \
174 #define ETH_MAN_DATA 0x0000FFFFU /* data to be written to the PHY */
176 #define ETH_MAN_VAL (ETH_MAN_HIGH|ETH_MAN_CODE_IEEE802_3)
179 /* received buffer descriptor: */
180 #define ETH_RDSC_ADDR 0x00U
181 #define ETH_RDSC_FLAGS 0x00U
182 #define ETH_RDSC_INFO 0x04U
183 #define ETH_RDSC_SIZE 0x08U
185 typedef struct eth_rdsc
{
186 volatile u_int32_t Addr
;
187 volatile u_int32_t Info
;
188 } __attribute__ ((aligned(4))) eth_rdsc_t
;
191 #define ETH_RDSC_F_WRAP 0x00000002U
192 #define ETH_RDSC_F_USED 0x00000001U
194 /* frame info bits: */
195 #define ETH_RDSC_I_BCAST 0x80000000U
196 #define ETH_RDSC_I_MULTICAST 0x40000000U
197 #define ETH_RDSC_I_UNICAST 0x20000000U
198 #define ETH_RDSC_I_VLAN 0x10000000U
199 #define ETH_RDSC_I_UNKNOWN_SRC 0x08000000U
200 #define ETH_RDSC_I_MATCH1 0x04000000U
201 #define ETH_RDSC_I_MATCH2 0x02000000U
202 #define ETH_RDSC_I_MATCH3 0x01000000U
203 #define ETH_RDSC_I_MATCH4 0x00800000U
204 #define ETH_RDSC_I_LEN 0x000007FFU
206 #define ETHREG(offset) *((volatile uint32_t *)(0xfffbc000 + (offset)))
208 #endif /* !_AT91EMACREG_H_ */
