sys/arch/arm/at91/at91pdcreg.h

   1 /*      $NetBSD: at91pdcreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $      */
   2
   3 /*
   4  * Copyright (c) 2007 Embedtronics Oy.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _AT91PDCREG_H_
  30 #define _AT91PDCREG_H_
  31
  32 #define PDC_RPR         0x00UL          /* Receive Pointer Register     */
  33 #define PDC_RCR         0x04UL          /* Receive Counter Register     */
  34 #define PDC_TPR         0x08UL          /* Transmit Pointer Register    */
  35 #define PDC_TCR         0x0CUL          /* Transmit Counter Register    */
  36 #define PDC_RNPR        0x10UL          /* Receive Next Pointer Reg     */
  37 #define PDC_RNCR        0x14UL          /* Receive Next Counter Reg     */
  38 #define PDC_TNPR        0x18UL          /* Transmit Next Ptt Register   */
  39 #define PDC_TNCR        0x1CUL          /* Transmit Next Counter Reg    */
  40 #define PDC_PTCR        0x20UL          /* PDC Transfer Ctl Reg PDC_    */
  41 #define PDC_PTSR        0x24UL          /* PDC Transfer Status Reg      */
  42
  43 /* Transfer Control Register bits: */
  44 #define PDC_PTCR_TXTDIS 0x200           /* disable transmitter          */
  45 #define PDC_PTCR_TXTEN  0x100           /* enable transmitter           */
  46 #define PDC_PTCR_RXTDIS 0x002           /* disable receiver             */
  47 #define PDC_PTCR_RXTEN  0x001           /* enable receiver              */
  48
  49 /* Transfer Status Register bits: */
  50 #define PDC_PTSR_TXTEN  PDC_PTCR_TXTEN
  51 #define PDC_PTSR_RXTEN  PDC_PTCR_RXTEN
  52
  53 #endif  // _AT91PDCREG_H_
  54