sys/arch/arm/at91/at91pioreg.h

   1 /*      $Id: at91pioreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $  */
   2 /*      $NetBSD$        */
   3
   4 /*
   5  * Copyright (c) 2007 Embedtronics Oy. All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _AT91GPIOREG_H_
  30 #define _AT91GPIOREG_H_
  31
  32 #define PIO_PER         0x00U   /* 00: PIO Enable Register              */
  33 #define PIO_PDR         0x04U   /* 04: PIO Disable Register             */
  34 #define PIO_PSR         0x08U   /* 08: PIO Status Register              */
  35 #define PIO_OER         0x10U   /* 10: PIO Output Enable Register       */
  36 #define PIO_ODR         0x14U   /* 14: PIO Output Disable Register      */
  37 #define PIO_OSR         0x18U   /* 18: PIO Output Status Register       */
  38 #define PIO_IFER        0x20U   /* 20: PIO Glitch Inp. Filter Ena. Reg  */
  39 #define PIO_IFDR        0x24U   /* 24: PIO Glitch Inp. Filter Dis. Reg  */
  40 #define PIO_IFSR        0x28U   /* 28: PIO Glitch Inp. Filter Sta. Reg  */
  41 #define PIO_SODR        0x30U   /* 30: PIO Set Output Data Reg          */
  42 #define PIO_CODR        0x34U   /* 34: PIO Clr Output Data Reg          */
  43 #define PIO_ODSR        0x38U   /* 38: PIO Output Data Status Reg       */
  44 #define PIO_PDSR        0x3CU   /* 3C: PIO Pin Data Status Reg          */
  45 #define PIO_IER         0x40U   /* 40: PIO Interrupt Enable Reg         */
  46 #define PIO_IDR         0x44U   /* 44: PIO Interrupt Disable Reg        */
  47 #define PIO_IMR         0x48U   /* 48: PIO Interrupt Mask Reg           */
  48 #define PIO_ISR         0x4CU   /* 4C: PIO Interrupt Status Reg         */
  49 #define PIO_MDER        0x50U   /* 50: PIO Multi-driver Enable Reg      */
  50 #define PIO_MDDR        0x54U   /* 54: PIO Multi-driver Disable Reg     */
  51 #define PIO_MDSR        0x58U   /* 58: PIO Multi-driver Status Reg      */
  52 #define PIO_PUDR        0x60U   /* 60: PIO Pull-up Disable Reg          */
  53 #define PIO_PUER        0x64U   /* 64: PIO Pull-up Enable Reg           */
  54 #define PIO_PUSR        0x68U   /* 68: PIO Pull-up Status Reg           */
  55 #define PIO_ASR         0x70U   /* 70: PIO Peripheral A Select Reg      */
  56 #define PIO_BSR         0x74U   /* 74: PIO Peripheral B Select Reg      */
  57 #define PIO_ABSR        0x78U   /* 78: PIO AB Status Reg                */
  58 #define PIO_OWER        0xA0U   /* A0: PIO Output Write Enable          */
  59 #define PIO_OWDR        0xA4U   /* A4: PIO Output Write Disable         */
  60 #define PIO_OWSR        0xA8U   /* A8: PIO Output Write Status Reg      */
  61 #define PIO_VERSION     0xFCU   /* FC: version reqister (AT91SAM92xx)   */
  62
  63 #endif  /* _AT91GPIOREG_H_ */