sys/arch/arm/at91/at91streg.h

   1 /*      $Id: at91streg.h,v 1.3 2009/10/23 06:53:13 snj Exp $    */
   2 /*      $NetBSD: at91streg.h,v 1.2 2008/07/03 01:15:38 matt Exp $       */
   3
   4 /*-
   5  * Copyright (c) 2007 Embedtronics Oy
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  */
  29
  30 #ifndef _AT91STREG_H_
  31 #define _AT91STREG_H_
  32
  33 #define AT91ST_BASE     0xFFFFFD00UL
  34
  35 /* System Timer (ST),
  36  * at91rm9200.pdf, page 289: */
  37
  38 #define ST_CR           0x00UL  /* 0x00: Control Register (W/O)         */
  39 #define ST_PIMR         0x04UL  /* 0x04: Period Interval Mode Reg       */
  40 #define ST_WDMR         0x08UL  /* 0x08: Watchdog Mode Reg              */
  41 #define ST_RTMR         0x0CUL  /* 0x0C: Real-time Mode Reg             */
  42 #define ST_SR           0x10UL  /* 0x10: Status Register                */
  43 #define ST_IER          0x14UL  /* 0x14: Interrupt Enable Register      */
  44 #define ST_IDR          0x18UL  /* 0x18: Interrupt Disable Register     */
  45 #define ST_IMR          0x1CUL  /* 0x1C: Interrupt Mask Register        */
  46 #define ST_RTAR         0x20UL  /* 0x20: Real-time Alarm Register       */
  47 #define ST_CRTR         0x24UL  /* 0x24: Current Real-time Register     */
  48
  49 /* Control Register bits: */
  50 #define ST_CR_WDRST     0x1     /* 1=reload the start-up value in wdt   */
  51
  52 /* Watchdog Mode Register bits: */
  53 #define ST_WDMR_EXTEN   0x20000 /* 1 = external signal assertion enable */
  54 #define ST_WDMR_RSTEN   0x10000 /* 1 = generate internal reset on wdt   */
  55 #define ST_WDMR_WDV     0xFFFF
  56
  57 /* Status Register bits: */
  58 #define ST_SR_ALMS      0x8     /* 1 = alarm compare detected           */
  59 #define ST_SR_RTTINC    0x4     /* 1 = real-time timer incremented      */
  60 #define ST_SR_WDOVF     0x2     /* 1 = watchdog overflowed              */
  61 #define ST_SR_PITS      0x1     /* 1 = period interval timer overflowed */
  62
  63 /* CRTR */
  64 #define ST_CRTR_CRTV    0xFFFFF
  65 #define ST_CRTR_CRTV_BITS 20
  66
  67 /* watchdog macros */
  68 #define WDT_TIMEOUT     20000   /* milliseconds                         */
  69
  70 //
  71 #define STREG(reg)      *((volatile u_int32_t *)(AT91ST_BASE + (reg)))
  72 #define WDog()          do {CPUReg->ST.CR = ST_CR_WDRST;} while (0)
  73
  74 #endif /* _AT91STREG_H_ */