| blob | 90b1c92f9bf3c4dfbac8c92962890139f39357a1 |
1 /* $NetBSD: ep93xxreg.h,v 1.6 2006/02/13 12:13:20 hamajima Exp $ */
3 /*
4 * Copyright (c) 2004 Jesse Off
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
29 #ifndef _EP93XXREG_H_
30 #define _EP93XXREG_H_
32 /*
33 * Physical memory map for the Cirrus Logic EP93XX
34 */
36 /*
37 * FFFF FFFF ---------------------------
38 * Device 12
39 * External SMC CS#0 ROM/SRAM
40 * F000 0000 ---------------------------
41 * Device 11
42 * SDRAM CS#2
43 * E000 0000 ---------------------------
44 * Device 10
45 * SDRAM CS#1
46 * D000 0000 ---------------------------
47 * Device 9
48 * SDRAM CS#0
49 * C000 0000 ---------------------------
50 * Device 8
51 * Not used
52 * 9000 0000 ---------------------------
53 * Device 7
54 * EP93XX System Registers
55 * 8080 0000 - 8094 FFFF
56 * APB Mapped Registers
57 * 8010 0000 - 807F FFFF
58 * Reserved
59 * 8000 0000 - 800F FFFF
60 * AHB Mapped Registers
61 * 8000 0000 ---------------------------
62 * Device 6
63 * External SMC CS#7 ROM/SRAM
64 * 7000 0000 ---------------------------
65 * Device 5
66 * External SMC CS#6 ROM/SRAM
67 * 6000 0000 ---------------------------
68 * Device 4
69 * PCMCIA/CompactFlash
70 * 5000 0000 - 5fff ffff
71 * Reserved
72 * 4c00 0000 - 4fff ffff
73 * Slot0 Memory space
74 * 4800 0000 - 4bff ffff
75 * Slot0 Attribute space
76 * 4400 0000 - 47ff ffff
77 * Reserved
78 * 4000 0000 - 43ff ffff
79 * Slot0 I/O space
80 * 4000 0000 ---------------------------
81 * Device 3
82 * External SMC CS#3 ROM/SRAM
83 * 3000 0000 ---------------------------
84 * Device 2
85 * External SMC CS#2 ROM/SRAM
86 * 2000 0000 ---------------------------
87 * Device 1
88 * External SMC CS#1 ROM/SRAM
89 * 1000 0000 ---------------------------
90 * Device 0
91 * SDRAM CS#3
92 * 0000 0000 ---------------------------
93 */
96 /*
97 * Virtual memory map for the Cirrus Logic EP93XX integrated devices
98 *
99 * Some device registers are staticaly mapped on upper address region.
100 * because we have to access them before bus_space is initialized.
101 * Most device is dynamicaly mapped by bus_space_map(). In this case,
102 * the actual mapped (virtual) address are not cared by device drivers.
103 */
105 /*
106 * FFFF FFFF ---------------------------
107 * not used
108 * F030 0000 ---------------------------
109 * APB bus (2Mbyte)
110 * F010 0000 ---------------------------
111 * AHB bus (1Mbyte)
112 * F000 0000 ---------------------------
113 * PCMCIA slot0 space
114 * E000 0000 ---------------------------
115 * Kernel text and data
116 * C000 0000 ---------------------------
117 * 0000 0000 ---------------------------
118 *
119 */
121 /* Virtual address for I/O space */
122 #define EP93XX_IO_VBASE 0xf0000000UL
124 /* EP93xx System and Peripheral Registers */
125 #define EP93XX_AHB_VBASE 0xf0000000UL
126 #define EP93XX_AHB_HWBASE 0x80000000UL
128 #define EP93XX_AHB_VIC1 0x000b0000UL
129 #define EP93XX_AHB_VIC2 0x000c0000UL
130 #define EP93XX_VIC_IRQStatus 0x00000000UL
131 #define EP93XX_VIC_FIQStatus 0x00000004UL
132 #define EP93XX_VIC_RawIntr 0x00000008UL
133 #define EP93XX_VIC_IntSelect 0x0000000cUL
134 #define EP93XX_VIC_IntEnable 0x00000010UL
135 #define EP93XX_VIC_IntEnClear 0x00000014UL
136 #define EP93XX_VIC_SoftInt 0x00000018UL
137 #define EP93XX_VIC_SoftIntClear 0x0000001cUL
138 #define EP93XX_VIC_Protection 0x00000020UL
139 #define EP93XX_VIC_VectAddr 0x00000030UL
140 #define EP93XX_VIC_DefVectAddr 0x00000034UL
141 #define EP93XX_VIC_VectAddr0 0x00000100UL
142 #define EP93XX_VIC_VectCntl0 0x00000200UL
143 #define EP93XX_VIC_PeriphID0 0x00000fe0UL
144 #define EP93XX_AHB_SMC 0x00080000UL
146 #define EP93XX_APB_VBASE 0xf0100000UL
147 #define EP93XX_APB_HWBASE 0x80800000UL
149 #define EP93XX_APB_GPIO 0x00040000UL
150 #define EP93XX_APB_GPIO_SIZE 0x000000d0UL
151 #define EP93XX_APB_SSP 0x000a0000UL
152 #define EP93XX_APB_SSP_SIZE 0x00000018UL
153 #define EP93XX_SSP_SSPCR0 0x00000000UL
154 #define EP93XX_SSP_SSPCR1 0x00000004UL
155 #define EP93XX_SSP_SSPDR 0x00000008UL
156 #define EP93XX_SSP_SSPSR 0x0000000cUL
157 #define EP93XX_SSP_SSPCPSR 0x00000010UL
158 #define EP93XX_SSP_SSPIIR 0x00000014UL
159 #define EP93XX_SSP_SSPICR 0x00000014UL
160 #define EP93XX_APB_SYSCON 0x00130000UL
161 #define EP93XX_APB_SYSCON_SIZE 0x000000c0UL
162 #define EP93XX_SYSCON_PwrSts 0x00000000UL
163 #define EP93XX_SYSCON_PwrCnt 0x00000004UL
164 #define PwrCnt_UARTBAUD 0x20000000UL
165 #define EP93XX_SYSCON_TEOI 0x00000018UL
166 #define EP93XX_SYSCON_ClkSet1 0x00000020UL
167 #define EP93XX_SYSCON_ClkSet2 0x00000024UL
168 #define EP93XX_SYSCON_DeviceCfg 0x00000080UL
169 #define EP93XX_SYSCON_ChipID 0x00000094UL
170 #define EP93XX_APB_TIMERS 0x00010000UL
171 #define EP93XX_APB_UART1 0x000c0000UL
172 #define EP93XX_APB_UART2 0x000d0000UL
173 #define EP93XX_APB_UART_SIZE 0x00000220UL
174 #define EP93XX_UART_Flag 0x00000018UL
175 #define EP93XX_UART_Data 0x00000000UL
176 #define EP93XX_APB_RTC 0x00120000UL
177 #define EP93XX_APB_RTC_SIZE 0x00000112UL
178 #define EP93XX_APB_WDOG 0x00140000UL
179 #define EP93XX_APB_WDOG_SIZE 0x00000008UL
181 /* EP93xx PCMCIA space */
182 #define EP93XX_PCMCIA0_VBASE 0xe0000000UL
183 #define EP93XX_PCMCIA0_HWBASE 0x40000000UL
184 #define EP93XX_PCMCIA_SIZE 0x10000000UL
185 #define EP93XX_PCMCIA_IO 0x00000000UL
186 #define EP93XX_PCMCIA_IO_SIZE 0x04000000UL
187 #define EP93XX_PCMCIA_ATTRIBUTE 0x08000000UL
188 #define EP93XX_PCMCIA_ATTRIBUTE_SIZE 0x04000000UL
189 #define EP93XX_PCMCIA_COMMON 0x0c000000UL
190 #define EP93XX_PCMCIA_COMMON_SIZE 0x04000000UL
192 #define NIRQ 64
193 #define VIC_NIRQ 32
195 #define EP93XX_INTR_bit31 31
196 #define EP93XX_INTR_bit30 30
197 #define EP93XX_INTR_bit29 29
198 #define EP93XX_INTR_bit28 28
199 #define EP93XX_INTR_bit27 27
200 #define EP93XX_INTR_bit26 26
201 #define EP93XX_INTR_bit25 25
202 #define EP93XX_INTR_bit24 24
203 #define EP93XX_INTR_bit23 23
204 #define EP93XX_INTR_bit22 22
205 #define EP93XX_INTR_bit21 21
206 #define EP93XX_INTR_bit20 20
207 #define EP93XX_INTR_bit19 19
208 #define EP93XX_INTR_bit18 18
209 #define EP93XX_INTR_bit17 17
210 #define EP93XX_INTR_bit16 16
211 #define EP93XX_INTR_bit15 15
212 #define EP93XX_INTR_bit14 14
213 #define EP93XX_INTR_bit13 13
214 #define EP93XX_INTR_bit12 12
215 #define EP93XX_INTR_bit11 11
216 #define EP93XX_INTR_bit10 10
217 #define EP93XX_INTR_bit9 9
218 #define EP93XX_INTR_bit8 8
219 #define EP93XX_INTR_bit7 7
220 #define EP93XX_INTR_bit6 6
221 #define EP93XX_INTR_bit5 5
222 #define EP93XX_INTR_bit4 4
223 #define EP93XX_INTR_bit3 3
224 #define EP93XX_INTR_bit2 2
225 #define EP93XX_INTR_bit1 1
226 #define EP93XX_INTR_bit0 0