sys/arch/arm/ep93xx/epereg.h

   1 /*      $NetBSD: epereg.h,v 1.3 2005/12/11 12:16:45 christos Exp $ */
   2
   3 /*
   4  * Copyright (c) 2004 Jesse Off
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
  20  * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  21  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef _EPEREG_H_
  30 #define _EPEREG_H_
  31
  32 #define EP93XX_AHB_EPE  0x00010000UL
  33 #define EPE_SIZE        0x000000f0UL
  34 #define EPE_RXCtl       0x00000000UL    /* Receiver Control */
  35 #define  RXCtl_IA0      0x00000001UL
  36 #define  RXCtl_IA1      0x00000002UL
  37 #define  RXCtl_IA2      0x00000004UL
  38 #define  RXCtl_IA3      0x00000008UL
  39 #define  RXCtl_IAHA     0x00000100UL
  40 #define  RXCtl_MA       0x00000200UL
  41 #define  RXCtl_BA       0x00000400UL
  42 #define  RXCtl_PA       0x00000800UL
  43 #define  RXCtl_RA       0x00001000UL
  44 #define  RXCtl_RCRCA    0x00002000UL
  45 #define  RXCtl_SRxON    0x00010000UL
  46 #define  RXCtl_BCRC     0x00020000UL
  47 #define  RXCtl_RxFCE0   0x00040000UL
  48 #define  RXCtl_RxFCE1   0x00080000UL
  49 #define  RXCtl_PauseA   0x00100000UL
  50 #define EPE_TXCtl       0x00000004UL    /* Transmitter Control */
  51 #define  TXCtl_STxON    0x00000001UL
  52 #define EPE_TestCtl     0x00000008UL    /* Test Control */
  53 #define  TestCtl_MFDX   0x00000040UL
  54 #define EPE_MIICmd      0x00000010UL    /* MII Command */
  55 #define  MIICmd_READ    0x00008000UL
  56 #define  MIICmd_WRITE   0x00004000UL
  57 #define EPE_MIIData     0x00000014UL    /* MII Data */
  58 #define EPE_MIISts      0x00000018UL    /* MII Status */
  59 #define MIISts_BUSY     0x00000001UL
  60 #define EPE_SelfCtl     0x00000020UL    /* Self Control */
  61 #define  SelfCtl_RESET  0x00000001UL
  62 #define  SelfCtl_PSPRS  0x00000100UL
  63 #define  SelfCtl_MDCDIV(x)      (((x) - 1) << 9)
  64 #define EPE_IntEn       0x00000024UL    /* Interrupt Enable */
  65 #define  IntEn_TSQIE    0x00000008UL
  66 #define  IntEn_REOFIE   0x00000004UL
  67 #define  IntEn_ECIE     0x02000000UL
  68 #define EPE_IntStsP     0x00000028UL    /* Interrupt Status Preserve */
  69 #define EPE_IntStsC     0x0000002cUL    /* Interrupt Status Clear */
  70 #define  IntSts_RxSQ    0x00000004UL
  71 #define  IntSts_TxSQ    0x00000008UL
  72 #define  IntSts_ECI     0x02000000UL
  73 #define  IntSts_MIII    0x00001000UL
  74 #define EPE_DiagAd      0x00000038UL    /* Diagnostic Address */
  75 #define EPE_DiagDa      0x0000003cUL    /* Diagnostic Data */
  76 #define EPE_GT          0x00000040UL    /* General Timer */
  77 #define EPE_FCT         0x00000044UL    /* Flow Control Timer */
  78 #define EPE_FCF         0x00000048UL    /* Flow Control Format */
  79 #define EPE_AFP         0x0000004cUL    /* Address Filter Pointer */
  80 #define EPE_IndAd       0x00000050UL    /* Individual Address */
  81 #define EPE_IndAd_SIZE  0x6
  82 #define EPE_HashTbl     0x00000050UL    /* Hash Table */
  83 #define EPE_HashTbl_SIZE        0x8
  84 #define EPE_GIIntSts    0x00000060UL    /* Global Interrupt Status */
  85 #define EPE_GIIntMsk    0x00000064UL    /* Global Interrupt Mask */
  86 #define  GIIntMsk_INT   0x00008000UL
  87 #define EPE_GIIntROSts  0x00000068UL    /* Global Interrupt Read-Only Status */
  88 #define EPE_GIIntFrc    0x0000006cUL    /* Global Interrupt Force */
  89 #define EPE_TXCollCnt   0x00000070UL    /* Transmit Collision Count */
  90 #define EPE_RXMissCnt   0x00000074UL    /* Receive Miss Count */
  91 #define EPE_RXRuntCnt   0x00000078UL    /* Receive Runt Count */
  92 #define EPE_BMCtl       0x00000080UL    /* Bus Master Control */
  93 #define  BMCtl_RxEn     0x00000001UL
  94 #define  BMCtl_TxEn     0x00000100UL
  95 #define EPE_BMSts       0x00000084UL    /* Bus Master Status */
  96 #define  BMSts_RxAct    0x00000080UL
  97 #define EPE_RXBCA       0x00000088UL    /* Receive Buffer Current Address */
  98 #define EPE_RXDQBAdd    0x00000090UL    /* Receive Descriptor Queue Base Addr */
  99 #define EPE_RXDQBLen    0x00000094UL    /* Receive Descriptor Queue Base Len */
 100 #define EPE_RXDQCurLen  0x00000096UL    /* Recv Descriptor Queue Current Len */
 101 #define EPE_RXDCurAdd   0x00000098UL    /* Recv Descriptor Current Address */
 102 #define EPE_RXDEnq      0x0000009cUL    /* Receive Descriptor Enqueue */
 103 #define EPE_RXStsQBAdd  0x000000a0UL    /* Receive Status Queue Base Address */
 104 #define EPE_RXStsQBLen  0x000000a4UL    /* Receive Status Queue Base Length */
 105 #define EPE_RXStsQCurLen        0x000000a6UL    /* Recv Sts Q Current Length */
 106 #define EPE_RXStsQCurAdd        0x000000a8UL    /* Recv Sts Q Current Address */
 107 #define EPE_RXStsEnq    0x000000acUL    /* Receive Status Enqueue */
 108 #define EPE_TXDQBAdd    0x000000b0UL    /* Transmit Descriptor Q Base Addr */
 109 #define EPE_TXDQBLen    0x000000b4UL    /* Transmit Descriptor Q Base Length */
 110 #define EPE_TXDQCurLen  0x000000b6UL    /* Transmit Descriptor Q Current Len */
 111 #define EPE_TXDQCurAdd  0x000000b8UL    /* Transmit Descriptor Q Current Addr */
 112 #define EPE_TXDEnq      0x000000bcUL    /* Transmit Descriptor Enqueue */
 113 #define EPE_TXStsQBAdd  0x000000c0UL    /* Transmit Status Queue Base Address */
 114 #define EPE_TXStsQBLen  0x000000c4UL    /* Transmit Status Queue Base Length */
 115 #define EPE_TXStsQCurLen        0x000000c6UL    /* Transmit Sts Q Current Len */
 116 #define EPE_TXStsQCurAdd        0x000000c8UL    /* Transmit Sts Q Current Adr */
 117 #define EPE_RXBufThrshld        0x000000d0UL    /* Receive Buffer Threshold */
 118 #define EPE_TXBufThrshld        0x000000d4UL    /* Transmit Buffer Threshold */
 119 #define EPE_RXStsThrshld        0x000000d8UL    /* Receive Status Threshold */
 120 #define EPE_TXStsThrshld        0x000000dcUL    /* Transmit Status Threshold */
 121 #define EPE_RXDThrshld  0x000000e0UL    /* Receive Descriptor Threshold */
 122 #define EPE_TXDThrshld  0x000000e4UL    /* Transmit Descriptor Threshold */
 123 #define EPE_MaxFrmLen   0x000000e8UL    /* Maximum Frame Length */
 124 #define EPE_RXHdrLen    0x000000ecUL    /* Receive Header Length */
 125 #define EPE_MACFIFO     0x00004000UL    /* FIFO RAM */
 126 #define EPE_MACFIFO_SIZE        0xc000UL
 127
 128 /* Receive Status Queue, First Word */
 129 #define RXStsQ_RFP      0x80000000UL
 130 #define RXStsQ_RWE      0x40000000UL
 131 #define RXStsQ_EOF      0x20000000UL
 132 #define RXStsQ_EOB      0x10000000UL
 133 #define RXStsQ_RX_Err   0x00200000UL
 134 #define RXStsQ_OE       0x00100000UL
 135 #define RXStsQ_FE       0x00080000UL
 136 #define RXStsQ_Runt     0x00040000UL
 137 #define RXStsQ_EData    0x00020000UL
 138 #define RXStsQ_CRCE     0x00010000UL
 139 #define RXStsQ_CRCI     0x00008000UL
 140
 141 /* Transmit Status Queue */
 142 #define TXStsQ_TxFP     0x80000000UL
 143 #define TXStsQ_TxWE     0x40000000UL
 144 #define TXStsQ_FA       0x20000000UL
 145 #define TXStsQ_LCRS     0x10000000UL
 146 #define TXStsQ_OW       0x04000000UL
 147 #define TXStsQ_TxU      0x02000000UL
 148 #define TXStsQ_EColl    0x01000000UL
 149
 150 #endif /* _EPEREG_H_ */