| blob | 3220f5364ec9c37732435c18df13946191fa299a |
1 /* $NetBSD: dc21285reg.h,v 1.4 2003/01/17 22:29:43 thorpej Exp $ */
3 /*
4 * Copyright (c) 1997,1998 Mark Brinicombe.
5 * Copyright (c) 1997,1998 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Mark Brinicombe
19 * for the NetBSD Project.
20 * 4. The name of the company nor the name of the author may be used to
21 * endorse or promote products derived from this software without specific
22 * prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
37 /*
38 * DC21285 register definitions
39 */
41 /* PCI registers in CSR space */
43 #define VENDOR_ID 0x00
44 #define DC21285_VENDOR_ID 0x1011
45 #define DEVICE_ID 0x02
46 #define DC21285_DEVICE_ID 0x1065
47 #define REVISION 0x08
48 #define CLASS 0x0A
49 #define CSR_BASE_MEMORY_ADDR 0x10
50 #define CSR_BASE_IO_ADDR 0x14
51 #define SDRAM_MEMORY_ADDR 0x18
53 /* Other PCI control / status registers */
55 #define OUTBOUND_INT_STATUS 0x030
56 #define OUTBOUND_INT_MASK 0x034
57 #define I2O_INBOUND_FIFO 0x040
58 #define I2O_OUTBOUND_FIFO 0x044
60 /* Mailbox registers */
62 #define MAILBOX_0 0x050
63 #define MAILBOX_1 0x054
64 #define MAILBOX_2 0x058
65 #define MAILBOX_3 0x05C
67 #define DOORBELL 0x060
68 #define DOORBELL_SETUP 0x064
69 #define ROM_WRITE_BYTE_ADDRESS 0x068
71 /* DMA Channel registers */
73 #define DMA_CHAN_1_BYTE_COUNT 0x80
74 #define DMA_CHAN_1_PCI_ADDR 0x84
75 #define DMA_CHAN_1_SDRAM_ADDR 0x88
76 #define DMA_CHAN_1_DESCRIPT 0x8C
77 #define DMA_CHAN_1_CONTROL 0x90
78 #define DMA_CHAN_2_BYTE_COUNT 0xA0
79 #define DMA_CHAN_2_PCI_ADDR 0xA4
80 #define DMA_CHAN_2_SDRAM_ADDR 0xA8
81 #define DMA_CHAN_2_DESCRIPTOR 0xAC
82 #define DMA_CHAN_2_CONTROL 0xB0
84 /* Offsets into DMA descriptor */
86 #define DMA_BYTE_COUNT 0
87 #define DMA_PCI_ADDRESS 4
88 #define DMA_SDRAM_ADDRESS 8
89 #define DMA_NEXT_DESCRIPTOR 12
91 /* DMA byte count register bits */
93 #define DMA_INTERBURST_SHIFT 24
94 #define DMA_PCI_TO_SDRAM 0
95 #define DMA_SDRAM_TO_PCI (1 << 30)
96 #define DMA_END_CHAIN (1 << 31)
98 /* DMA control bits */
100 #define DMA_ENABLE (1 << 0)
101 #define DMA_TRANSFER_DONE (1 << 2)
102 #define DMA_ERROR (1 << 3)
103 #define DMA_REGISTOR_DESCRIPTOR (1 << 4)
104 #define DMA_PCI_MEM_READ (0 << 5)
105 #define DMA_PCI_MEM_READ_LINE (1 << 5)
106 #define DMA_PCI_MEM_READ_MULTI1 (2 << 5)
107 #define DMA_PCI_MEM_READ_MULTI2 (3 << 5)
108 #define DMA_CHAIN_DONE (1 << 7)
109 #define DMA_INTERBURST_4 (0 << 8)
110 #define DMA_INTERBURST_8 (1 << 8)
111 #define DMA_INTERBURST_16 (2 << 8)
112 #define DMA_INTERBURST_32 (3 << 8)
113 #define DMA_PCI_LENGTH_8 0
114 #define DMA_PCI_LENGTH_16 (1 << 15)
115 #define DMA_SDRAM_LENGTH_1 (0 << 16)
116 #define DMA_SDRAM_LENGTH_2 (1 << 16)
117 #define DMA_SDRAM_LENGTH_4 (2 << 16)
118 #define DMA_SDRAM_LENGTH_8 (3 << 16)
119 #define DMA_SDRAM_LENGTH_16 (4 << 16)
121 /* CSR Base Address Mask */
123 #define CSR_BA_MASK 0x0F8
124 #define CSR_MASK_128B 0x00000000
125 #define CSR_MASK_512KB 0x00040000
126 #define CSR_MASK_1MB 0x000C0000
127 #define CSR_MASK_2MB 0x001C0000
128 #define CSR_MASK_4MB 0x003C0000
129 #define CSR_MASK_8MB 0x007C0000
130 #define CSR_MASK_16MB 0x00FC0000
131 #define CSR_MASK_32MB 0x01FC0000
132 #define CSR_MASK_64MB 0x03FC0000
133 #define CSR_MASK_128MB 0x07FC0000
134 #define CSR_MASK_256MB 0x0FFC0000
135 #define CSR_BA_OFFSET 0x0FC
137 /* SDRAM Base Address Mask */
139 #define SDRAM_BA_MASK 0x100
140 #define SDRAM_MASK_256KB 0x00000000
141 #define SDRAM_MASK_512KB 0x00040000
142 #define SDRAM_MASK_1MB 0x000C0000
143 #define SDRAM_MASK_2MB 0x001C0000
144 #define SDRAM_MASK_4MB 0x003C0000
145 #define SDRAM_MASK_8MB 0x007C0000
146 #define SDRAM_MASK_16MB 0x00FC0000
147 #define SDRAM_MASK_32MB 0x01FC0000
148 #define SDRAM_MASK_64MB 0x03FC0000
149 #define SDRAM_MASK_128MB 0x07FC0000
150 #define SDRAM_MASK_256MB 0x0FFC0000
151 #define SDRAM_WINDOW_DISABLE (1 << 31)
152 #define SDRAM_BA_OFFSET 0x104
154 /* Expansion ROM Base Address Mask */
156 #define EXPANSION_ROM_BA_MASK 0x108
157 #define ROM_MASK_1MB 0x00000000
158 #define ROM_MASK_2MB 0x00100000
159 #define ROM_MASK_4MB 0x00300000
160 #define ROM_MASK_8MB 0x00700000
161 #define ROM_MASK_16MB 0x00F00000
162 #define ROM_WINDOW_DISABLE (1 << 31)
164 /* SDRAM configuration */
166 #define SDRAM_TIMING 0x10C
167 #define SDRAM_ARRAY_SIZE_0 0x0
168 #define SDRAM_ARRAY_SIZE_1MB 0x1
169 #define SDRAM_ARRAY_SIZE_2MB 0x2
170 #define SDRAM_ARRAY_SIZE_4MB 0x3
171 #define SDRAM_ARRAY_SIZE_8MB 0x4
172 #define SDRAM_ARRAY_SIZE_16MB 0x5
173 #define SDRAM_ARRAY_SIZE_32MB 0x6
174 #define SDRAM_ARRAY_SIZE_64MB 0x7
175 #define SDRAM_2_BANKS 0
176 #define SDRAM_4_BANKS (1 << 3)
177 #define SDRAM_ADDRESS_MUX_SHIFT 4
178 #define SDRAM_ARRAY_BASE_SHIFT 20
179 #define SDRAM_ADDRESS_SIZE_0 0x110
180 #define SDRAM_ADDRESS_SIZE_1 0x114
181 #define SDRAM_ADDRESS_SIZE_2 0x118
182 #define SDRAM_ADDRESS_SIZE_3 0x11C
184 /* I2O registers */
186 #define I2O_INBOUND_FREE_HEAD 0x120
187 #define I2O_INBOUND_POST_TAIL 0x124
188 #define I2O_OUTBOUND_POST_HEAD 0x128
189 #define I2O_OUTBOUND_FREE_TAIL 0x12c
190 #define I2O_INBOUND_FREE_COUNT 0x130
191 #define I2O_OUTBOUND_POST_COUNT 0x134
192 #define I2O_INBOUND_POST_COUNT 0x138
194 /* Control register */
196 #define SA_CONTROL 0x13C
197 #define INITIALIZE_COMPLETE (1 << 0)
198 #define ASSERT_SERR (1 << 1)
199 #define RECEIVED_SERR (1 << 3)
200 #define SA_SDRAM_PARITY_ERROR (1 << 4)
201 #define PCI_SDRAM_PARITY_ERROR (1 << 5)
202 #define DMA_SDRAM_PARITY_ERROR (1 << 6)
203 #define DISCARD_TIMER_EXPIRED (1 << 8)
204 #define PCI_NOT_RESET (1 << 9)
205 #define WATCHDOG_ENABLE (1 << 13)
206 #define I2O_SIZE_256 (0 << 10)
207 #define I2O_SIZE_512 (1 << 10)
208 #define I2O_SIZE_1024 (2 << 10)
209 #define I2O_SIZE_2048 (3 << 10)
210 #define I2O_SIZE_4096 (4 << 10)
211 #define I2O_SIZE_8192 (5 << 10)
212 #define I2O_SIZE_16384 (6 << 10)
213 #define I2O_SIZE_32768 (7 << 10)
214 #define ROM_WIDTH_8 (3 << 14)
215 #define ROM_WIDTH_16 (1 << 14)
216 #define ROM_WIDTH_32 (2 << 14)
217 #define ROM_ACCESS_TIME_SHIFT 16
218 #define ROM_BURST_TIME_SHIFT 20
219 #define ROM_TRISTATE_TIME_SHIFT 24
220 #define XCS_DIRECTION_SHIFT 28
221 #define PCI_CENTRAL_FUNCTION (1 << 31)
223 #define PCI_ADDRESS_EXTENSION 0x140
224 #define PREFETCHABLE_MEM_RANGE 0x144
226 /* XBUS / PCI Arbiter registers */
228 #define XBUS_CYCLE_ARBITER 0x148
229 #define XBUS_CYCLE_0_SHIFT 0
230 #define XBUS_CYCLE_1_SHIFT 3
231 #define XBUS_CYCLE_2_SHIFT 6
232 #define XBUS_CYCLE_3_SHIFT 9
233 #define XBUS_CYCLE_STROBE_SHIFT 12
234 #define XBUS_PCI_ARBITER (1 << 23)
235 #define XBUS_INT_IN_L0_LOW 0
236 #define XBUS_INT_IN_L0_HIGH (1 << 24)
237 #define XBUS_INT_IN_L1_LOW 0
238 #define XBUS_INT_IN_L1_HIGH (1 << 25)
239 #define XBUS_INT_IN_L2_LOW 0
240 #define XBUS_INT_IN_L2_HIGH (1 << 26)
241 #define XBUS_INT_IN_L3_LOW 0
242 #define XBUS_INT_IN_L3_HIGH (1 << 27)
243 #define XBUS_INT_XCS0_LOW 0
244 #define XBUS_INT_XCS0_HIGH (1 << 28)
245 #define XBUS_INT_XCS1_LOW 0
246 #define XBUS_INT_XCS1_HIGH (1 << 29)
247 #define XBUS_INT_XCS2_LOW 0
248 #define XBUS_INT_XCS2_HIGH (1 << 30)
249 #define XBUS_PCI_INT_REQUEST (1 << 31)
251 #define XBUS_IO_STROBE_MASK 0x14C
252 #define XBUS_IO_STROBE_0_SHIFT 0
253 #define XBUS_IO_STROBE_2_SHIFT 8
254 #define XBUS_IO_STROBE_3_SHIFT 16
255 #define XBUS_IO_STROBE_4_SHIFT 24
257 #define DOORBELL_PCI_MASK 0x150
258 #define DOORBELL_SA_MASK 0x154
260 /* UART registers */
262 #define UART_DATA 0x160
263 #define UART_RX_STAT 0x164
264 #define UART_PARITY_ERROR 0x01
265 #define UART_FRAME_ERROR 0x02
266 #define UART_OVERRUN_ERROR 0x04
267 #define UART_RX_ERROR (UART_PARITY_ERROR | UART_FRAME_ERROR \
268 | UART_OVERRUN_ERROR)
269 #define UART_H_UBRLCR 0x168
270 #define UART_BREAK 0x01
271 #define UART_PARITY_ENABLE 0x02
272 #define UART_ODD_PARITY 0x00
273 #define UART_EVEN_PARITY 0x04
274 #define UART_STOP_BITS_1 0x00
275 #define UART_STOP_BITS_2 0x08
276 #define UART_ENABLE_FIFO 0x10
277 #define UART_DATA_BITS_5 0x00
278 #define UART_DATA_BITS_6 0x20
279 #define UART_DATA_BITS_7 0x40
280 #define UART_DATA_BITS_8 0x60
281 #define UART_M_UBRLCR 0x16C
282 #define UART_L_UBRLCR 0x170
283 #define UART_BRD(fclk, x) (((fclk) / 4 / 16 / x) - 1)
285 #define UART_CONTROL 0x174
286 #define UART_ENABLE 0x01
287 #define UART_SIR_ENABLE 0x02
288 #define UART_IRDA_ENABLE 0x04
289 #define UART_FLAGS 0x178
290 #define UART_TX_BUSY 0x08
291 #define UART_RX_FULL 0x10
292 #define UART_TX_EMPTY 0x20
294 /* Interrupt numbers for IRQ and FIQ registers */
296 #define IRQ_RESERVED0 0x00
297 #define IRQ_SOFTINT 0x01
298 #define IRQ_SERIAL_RX 0x02
299 #define IRQ_SERIAL_TX 0x03
300 #define IRQ_TIMER_1 0x04
301 #define IRQ_TIMER_2 0x05
302 #define IRQ_TIMER_3 0x06
303 #define IRQ_TIMER_4 0x07
304 #define IRQ_IN_L0 0x08
305 #define IRQ_IN_L1 0x09
306 #define IRQ_IN_L2 0x0A
307 #define IRQ_IN_L3 0x0B
308 #define IRQ_XCS_L0 0x0C
309 #define IRQ_XCS_L1 0x0D
310 #define IRQ_XCS_L2 0x0E
311 #define IRQ_DOORBELL 0x0F
312 #define IRQ_DMA_1 0x10
313 #define IRQ_DMA_2 0x11
314 #define IRQ_PCI 0x12
315 #define IRQ_PMCSR 0x13
316 #define IRQ_RESERVED1 0x14
317 #define IRQ_RESERVED2 0x15
318 #define IRQ_BIST 0x16
319 #define IRQ_SERR 0x17
320 #define IRQ_SDRAM_PARITY 0x18
321 #define IRQ_I2O 0x19
322 #define IRQ_RESERVED3 0x1A
323 #define IRQ_DISCARD_TIMER 0x1B
324 #define IRQ_DATA_PARITY 0x1C
325 #define IRQ_MASTER_ABORT 0x1D
326 #define IRQ_TARGET_ABORT 0x1E
327 #define IRQ_PARITY 0x1F
329 /* IRQ and FIQ status / enable registers */
331 #define IRQ_STATUS 0x180
332 #define IRQ_RAW_STATUS 0x184
333 #define IRQ_ENABLE 0x188
334 #define IRQ_ENABLE_SET 0x188
335 #define IRQ_ENABLE_CLEAR 0x18c
336 #define IRQ_SOFT 0x190
338 #define FIQ_STATUS 0x280
339 #define FIQ_RAW_STATUS 0x284
340 #define FIQ_ENABLE 0x288
341 #define FIQ_ENABLE_SET 0x288
342 #define FIQ_ENABLE_CLEAR 0x28c
343 #define FIQ_SOFT 0x290
345 /* Timer registers */
347 /* Relative offsets and bases */
349 #define TIMER_LOAD 0x00
350 #define TIMER_VALUE 0x04
351 #define TIMER_CONTROL 0x08
352 #define TIMER_CLEAR 0x0C
353 #define TIMER_1_BASE 0x300
354 #define TIMER_2_BASE 0x320
355 #define TIMER_3_BASE 0x340
356 #define TIMER_4_BASE 0x360
358 /* Control register bits */
360 #define TIMER_FCLK 0x00
361 #define TIMER_FCLK_16 0x04
362 #define TIMER_FCLK_256 0x08
363 #define TIMER_EXTERNAL 0x0C
364 #define TIMER_MODE_FREERUN 0x00
365 #define TIMER_MODE_PERIODIC 0x40
366 #define TIMER_ENABLE 0x80
368 /* Maximum timer value */
370 #define TIMER_MAX_VAL 0x00FFFFFF
372 /* Specific registers */
374 #define TIMER_1_LOAD 0x300
375 #define TIMER_1_VALUE 0x304
376 #define TIMER_1_CONTROL 0x308
377 #define TIMER_1_CLEAR 0x30C
378 #define TIMER_2_LOAD 0x320
379 #define TIMER_2_VALUE 0x324
380 #define TIMER_2_CONTROL 0x328
381 #define TIMER_2_CLEAR 0x32C
382 #define TIMER_3_LOAD 0x340
383 #define TIMER_3_VALUE 0x344
384 #define TIMER_3_CONTROL 0x348
385 #define TIMER_3_CLEAR 0x34C
386 #define TIMER_4_LOAD 0x360
387 #define TIMER_4_VALUE 0x364
388 #define TIMER_4_CONTROL 0x368
389 #define TIMER_4_CLEAR 0x36C
391 /* Miscellaneous definitions */
393 #ifndef FCLK
394 #define FCLK 50000000
395 #endif