sys/arch/arm/footbridge/footbridge_intr.h

   1 /*      $NetBSD: footbridge_intr.h,v 1.13 2008/04/27 18:58:44 matt Exp $        */
   2
   3 /*
   4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _FOOTBRIDGE_INTR_H_
  39 #define _FOOTBRIDGE_INTR_H_
  40
  41 #include <arm/cpu.h>
  42 #include <arm/armreg.h>
  43
  44 #define IPL_NONE        0       /* nothing */
  45 #define IPL_SOFTCLOCK   1       /* clock soft interrupts */
  46 #define IPL_SOFTBIO     2       /* block i/o */
  47 #define IPL_SOFTNET     3       /* network software interrupts */
  48 #define IPL_SOFTSERIAL  4       /* serial software interrupts */
  49 #define IPL_VM          5       /* memory allocation */
  50 #define IPL_SCHED       6       /* clock */
  51 #define IPL_HIGH        7       /* everything */
  52
  53 #define NIPL            8
  54
  55 #define IST_UNUSABLE    -1      /* interrupt cannot be used */
  56 #define IST_NONE        0       /* none (dummy) */
  57 #define IST_PULSE       1       /* pulsed */
  58 #define IST_EDGE        2       /* edge-triggered */
  59 #define IST_LEVEL       3       /* level-triggered */
  60
  61 #define __NEWINTR       /* enables new hooks in cpu_fork()/cpu_switch() */
  62
  63 #define ARM_IRQ_HANDLER _C_LABEL(footbridge_intr_dispatch)
  64
  65 #ifndef _LOCORE
  66 #include <arm/cpufunc.h>
  67
  68 #include <arm/footbridge/dc21285mem.h>
  69 #include <arm/footbridge/dc21285reg.h>
  70
  71 #define INT_SWMASK                                                      \
  72         ((1U << IRQ_SOFTINT) | (1U << IRQ_RESERVED0) |                  \
  73          (1U << IRQ_RESERVED1) | (1U << IRQ_RESERVED2))
  74 #define ICU_INT_HWMASK  (0xffffffff & ~(INT_SWMASK |  (1U << IRQ_RESERVED3)))
  75
  76 /* only call this with interrupts off */
  77 static inline void __attribute__((__unused__))
  78 footbridge_set_intrmask(void)
  79 {
  80         extern volatile uint32_t intr_enabled;
  81         volatile uint32_t * const dc21285_armcsr_vbase =
  82             (volatile uint32_t *)(DC21285_ARMCSR_VBASE);
  83
  84         /* fetch once so we write the same number to both registers */
  85         uint32_t tmp = intr_enabled & ICU_INT_HWMASK;
  86
  87         dc21285_armcsr_vbase[IRQ_ENABLE_SET>>2] = tmp;
  88         dc21285_armcsr_vbase[IRQ_ENABLE_CLEAR>>2] = ~tmp;
  89 }
  90
  91 static inline void __attribute__((__unused__))
  92 footbridge_splx(int ipl)
  93 {
  94         extern int footbridge_imask[];
  95         extern volatile uint32_t intr_enabled;
  96         extern volatile int footbridge_ipending;
  97         int oldirqstate, hwpend;
  98
  99         /* Don't let the compiler re-order this code with preceding code */
 100         __insn_barrier();
 101
 102         set_curcpl(ipl);
 103
 104         hwpend = footbridge_ipending & ICU_INT_HWMASK & ~footbridge_imask[ipl];
 105         if (hwpend != 0) {
 106                 oldirqstate = disable_interrupts(I32_bit);
 107                 intr_enabled |= hwpend;
 108                 footbridge_set_intrmask();
 109                 restore_interrupts(oldirqstate);
 110         }
 111
 112 #ifdef __HAVE_FAST_SOFTINTS
 113         cpu_dosoftints();
 114 #endif
 115 }
 116
 117 static inline int __attribute__((__unused__))
 118 footbridge_splraise(int ipl)
 119 {
 120         int     old;
 121
 122         old = curcpl();
 123         set_curcpl(ipl);
 124
 125         /* Don't let the compiler re-order this code with subsequent code */
 126         __insn_barrier();
 127
 128         return (old);
 129 }
 130
 131 static inline int __attribute__((__unused__))
 132 footbridge_spllower(int ipl)
 133 {
 134         int old = curcpl();
 135
 136         footbridge_splx(ipl);
 137         return(old);
 138 }
 139
 140 /* should only be defined in footbridge_intr.c */
 141 #if !defined(ARM_SPL_NOINLINE)
 142
 143 #define splx(newspl)            footbridge_splx(newspl)
 144 #define _spllower(ipl)          footbridge_spllower(ipl)
 145 #define _splraise(ipl)          footbridge_splraise(ipl)
 146 void    _setsoftintr(int);
 147
 148 #else
 149
 150 int     _splraise(int);
 151 int     _spllower(int);
 152 void    splx(int);
 153 void    _setsoftintr(int);
 154
 155 #endif /* ! ARM_SPL_NOINLINE */
 156
 157 #include <sys/evcnt.h>
 158 #include <sys/queue.h>
 159 #include <machine/irqhandler.h>
 160
 161 #define splsoft()       _splraise(IPL_SOFT)
 162
 163 #define spl0()          (void)_spllower(IPL_NONE)
 164 #define spllowersoftclock() (void)_spllower(IPL_SOFTCLOCK)
 165
 166 typedef uint8_t ipl_t;
 167 typedef struct {
 168         ipl_t _ipl;
 169 } ipl_cookie_t;
 170
 171 static inline ipl_cookie_t
 172 makeiplcookie(ipl_t ipl)
 173 {
 174
 175         return (ipl_cookie_t){._ipl = ipl};
 176 }
 177
 178 static inline int
 179 splraiseipl(ipl_cookie_t icookie)
 180 {
 181
 182         return _splraise(icookie._ipl);
 183 }
 184
 185 #include <sys/spl.h>
 186
 187 /* footbridge has 32 interrupt lines */
 188 #define NIRQ            32
 189
 190 struct intrhand {
 191         TAILQ_ENTRY(intrhand) ih_list;  /* link on intrq list */
 192         int (*ih_func)(void *);         /* handler */
 193         void *ih_arg;                   /* arg for handler */
 194         int ih_ipl;                     /* IPL_* */
 195         int ih_irq;                     /* IRQ number */
 196 };
 197
 198 #define IRQNAMESIZE     sizeof("footbridge irq 31")
 199
 200 struct intrq {
 201         TAILQ_HEAD(, intrhand) iq_list; /* handler list */
 202         struct evcnt iq_ev;             /* event counter */
 203         int iq_mask;                    /* IRQs to mask while handling */
 204         int iq_levels;                  /* IPL_*'s this IRQ has */
 205         int iq_ist;                     /* share type */
 206         int iq_ipl;                     /* max ipl */
 207         char iq_name[IRQNAMESIZE];      /* interrupt name */
 208 };
 209
 210 #endif /* _LOCORE */
 211
 212 #endif  /* _FOOTBRIDGE_INTR_H */