sys/arch/arm/gemini/gemini_reg.h

   1 /*      $NetBSD: gemini_reg.h,v 1.8 2008/12/15 04:44:27 matt Exp $      */
   2
   3 #ifndef _ARM_GEMINI_REG_H_
   4 #define _ARM_GEMINI_REG_H_
   5
   6 /*
   7  * Register definitions for Gemini SOC
   8  */
   9
  10 #include "opt_gemini.h"
  11 #include <machine/endian.h>
  12 #include <sys/cdefs.h>
  13
  14 #if defined(SL3516)
  15 /*
  16  * Gemini SL3516 memory map
  17  */
  18 #define GEMINI_SRAM_BASE        0x00000000      /* Internal SRAM  */
  19                                                 /* NOTE: use the SHADOW to avoid conflict w/ DRAM */
  20 #define GEMINI_SRAM_SIZE        0x10000000      /* 128 MB */
  21 #define GEMINI_DRAM_BASE        0x00000000      /* DRAM (via DDR Control Module) */
  22                                                 /* NOTE: this is a shadow of 0x10000000 */
  23 #define GEMINI_DRAM_SIZE        0x20000000      /* 512 MB */
  24                                                 /* NOTE: size of addr space, not necessarily populated */
  25 #define GEMINI_FLASH_BASE       0x30000000      /* DRAM (via DDR Control Module) */
  26 #define GEMINI_FLASH_SIZE       0x10000000      /* 128 MB */
  27
  28 /*
  29  * Gemini SL3516 device map
  30  */
  31 #define GEMINI_GLOBAL_BASE      0x40000000      /* Global registers */
  32 #define GEMINI_WATCHDOG_BASE    0x41000000      /* Watch dog timer module */
  33 #define GEMINI_UART_BASE        0x42000000      /* UART control module */
  34 #define GEMINI_UART_SIZE        0x20
  35 #define GEMINI_TIMER_BASE       0x43000000      /* Timer module */
  36 #define GEMINI_LCD_BASE         0x44000000      /* LCD Interface module */
  37 #define GEMINI_RTC_BASE         0x45000000      /* Real Time Clock module */
  38 #define GEMINI_SATA_BASE        0x46000000      /* Serial ATA module */
  39 #define GEMINI_LPCHC_BASE       0x47000000      /* LPC Hosr Controller module */
  40 #define GEMINI_LPCIO_BASE       0x47800000      /* LPC Peripherals IO space */
  41 #define GEMINI_IC0_BASE         0x48000000      /* Interrupt Control module #0 */
  42 #define GEMINI_IC1_BASE         0x49000000      /* Interrupt Control module #1 */
  43 #define GEMINI_SSPC_BASE        0x4a000000      /* Synchronous Serial Port Control module */
  44 #define GEMINI_PWRC_BASE        0x4b000000      /* Power Control module */
  45 #define GEMINI_CIR_BASE         0x4c000000      /* CIR Control module */
  46 #define GEMINI_GPIO0_BASE       0x4d000000      /* GPIO module #0 */
  47 #define GEMINI_GPIO1_BASE       0x4e000000      /* GPIO module #1 */
  48 #define GEMINI_GPIO2_BASE       0x4f000000      /* GPIO module #2 */
  49 #define GEMINI_PCICFG_BASE      0x50000000      /* PCI IO, configuration and control space */
  50 #define GEMINI_PCIIO_BASE       0x50001000      /* PCI IO     space      */
  51 #define GEMINI_PCIIO_SIZE       0x0007f000      /* PCI IO     space size */
  52 #define GEMINI_PCIMEM_BASE      0x58000000      /* PCI Memory space      */
  53 #define GEMINI_PCIMEM_SIZE      0x08000000      /* PCI Memory space size */
  54 #define GEMINI_GMAC_BASE        0x60000000      /* NetEngine & GMAC Configuration registers */
  55 #define GEMINI_GMAC_SIZE        0x00010000      /* NetEngine & GMAC Configuration size */
  56 #define GEMINI_SDC_BASE         0x62000000      /* Security DMA and Configure registers */
  57 #define GEMINI_MIDE_BASE        0x63000000      /* Multi IDE registers */
  58 #define GEMINI_RXDC_BASE        0x64000000      /* RAID XOR DMA Configuration registers */
  59 #define GEMINI_FLASHC_BASE      0x65000000      /* Flash Controller registers */
  60 #define GEMINI_DRAMC_BASE       0x66000000      /* DRAM (DDR/SDR) Controller registers */
  61 #define GEMINI_GDMA_BASE        0x67000000      /* General DMA registers */
  62 #define GEMINI_USB0_BASE        0x68000000      /* USB #0 registers */
  63 #define GEMINI_USB1_BASE        0x69000000      /* USB #1 registers */
  64 #define GEMINI_TVE_BASE         0x6a000000      /* TVE registers */
  65 #define GEMINI_SRAM_SHADOW_BASE 0x70000000      /* Shadow of internal SRAM */
  66
  67 /*
  68  * Gemini SL3516 Global register offsets and bits
  69  */
  70 #define GEMINI_GLOBAL_WORD_ID   0x0             /* Global Word ID */                    /* ro */
  71 #define  GLOBAL_ID_CHIP_ID      __BITS(31,8)
  72 #define  GLOBAL_ID_CHIP_REV     __BITS(7,0)
  73 #define GEMINI_GLOBAL_RESET_CTL 0xc             /* Global Soft Reset Control */         /* rw */
  74 #define GLOBAL_RESET_GLOBAL     __BIT(31)       /* Global Soft Reset */
  75 #define GLOBAL_RESET_CPU1       __BIT(30)       /* CPU#1 reset hold */
  76 #define GLOBAL_RESET_GMAC1      __BIT(6)        /* GMAC1 reset hold */
  77 #define GLOBAL_RESET_GMAC0      __BIT(5)        /* CGMAC reset hold */
  78 #define GEMINI_GLOBAL_MISC_CTL  0x30            /* Miscellaneous Control */             /* rw */
  79 #define GEMINI_GLOBAL_CPU0      0x38            /* CPU #0 Status and Control */         /* rw */
  80 #define  GLOBAL_CPU0_IPICPU1    __BIT(31)       /* IPI to CPU#1 */
  81 #define GEMINI_GLOBAL_CPU1      0x3c            /* CPU #1 Status and Control */         /* rw */
  82 #define  GLOBAL_CPU1_IPICPU0    __BIT(31)       /* IPI to CPU#0 */
  83
  84 /*
  85  * Gemini SL3516 Watchdog device register offsets and bits
  86  */
  87 #define GEMINI_WDT_WDCOUNTER    0x0             /* Watchdog Timer Counter */            /* ro */
  88 #define GEMINI_WDT_WDLOAD       0x4             /* Watchdog Timer Load */               /* rw */
  89 #define  WDT_WDLOAD_DFLT        0x3EF1480       /* default Load reg val */
  90 #define GEMINI_WDT_WDRESTART    0x8             /* Watchdog Timer Restart */            /* wo */
  91 #define  WDT_WDRESTART_Resv     __BITS(31,16)
  92 #define  WDT_WDRESTART_RST      __BITS(15,0)
  93 #define   WDT_WDRESTART_MAGIC   0x5ab9
  94 #define GEMINI_WDT_WDCR         0xc             /* Watchdog Timer Control */            /* rw */
  95 #define  WDT_WDCR_Resv          __BITS(31,5)
  96 #define  WDT_WDCR_CLKSRC        __BIT(4)        /* Timer Clock Source: 5 MHz clock */
  97 #define   WDCR_CLKSRC_PCLK      (0 << 4)        /* Timer Clock Source: PCLK (APB CLK) */
  98 #define   WDCR_CLKSRC_5MHZ      (1 << 4)        /* Timer Clock Source: 5 MHz clock */
  99 #define  WDT_WDCR_EXTSIG_ENB    __BIT(3)        /* Timer External Signal Enable */
 100 #define  WDT_WDCR_INTR_ENB      __BIT(2)        /* Timer System Interrupt Enable */
 101 #define  WDT_WDCR_RESET_ENB     __BIT(1)        /* Timer System Reset Enable */
 102 #define  WDT_WDCR_ENB           __BIT(0)        /* Timer Enable */
 103 #define GEMINI_WDT_WDSTATUS     0x10            /* Watchdog Timer Status */             /* ro */
 104 #define  WDT_WDSTATUS_Resv      __BITS(31,1)
 105 #define  WDT_WDSTATUS_ZERO      __BIT(0)        /* non-zero if timer counted down to zero! */
 106 #define GEMINI_WDT_WDCLEAR      0x14            /* Watchdog Timer Clear */              /* wo */
 107 #define  WDT_WDCLEAR_Resv       __BITS(31,1)
 108 #define  WDT_WDCLEAR_CLEAR      __BIT(0)        /* write this bit to clear Status */
 109 #define GEMINI_WDT_WDINTERLEN   0x18            /* Watchdog Timer Interrupt Length */   /* rw */
 110                                                 /*  duration of signal assertion,  */
 111                                                 /*  in units of clock cycles       */
 112 #define  WDT_WDINTERLEN_DFLT    0xff            /*  default is 256 cycles          */
 113
 114
 115 /*
 116  * Gemini SL3516 Timer device register offsets and bits
 117  *
 118  * have 3 timers, here indexed 1<=(n)<=3 as in the doc
 119  * each has 4 sequential 32bit rw regs
 120  */
 121 #define GEMINI_NTIMERS                  3
 122 #define GEMINI_TIMERn_REG(n, o)         ((((n) - 1) * 0x10) + (o))
 123 #define GEMINI_TIMERn_COUNTER(n)        GEMINI_TIMERn_REG((n), 0x0)                     /* rw */
 124 #define GEMINI_TIMERn_LOAD(n)           GEMINI_TIMERn_REG((n), 0x4)                     /* rw */
 125 #define GEMINI_TIMERn_MATCH1(n)         GEMINI_TIMERn_REG((n), 0x08)                    /* rw */
 126 #define GEMINI_TIMERn_MATCH2(n)         GEMINI_TIMERn_REG((n), 0x0C)                    /* rw */
 127 #define GEMINI_TIMER_TMCR               0x30                                            /* rw */
 128 #define  TIMER_TMCR_Resv                __BITS(31,12)
 129 #define  TIMER_TMCR_TMnUPDOWN(n)        __BIT(9 + (n) - 1)
 130 #define  TIMER_TMCR_TMnOFENABLE(n)      __BIT((((n) - 1) * 3) + 2)
 131 #define  TIMER_TMCR_TMnCLOCK(n)         __BIT((((n) - 1) * 3) + 1)
 132 #define  TIMER_TMCR_TMnENABLE(n)        __BIT((((n) - 1) * 3) + 0)
 133 #define  GEMINI_TIMER_TMnCR_MASK(n)             \
 134                 ( TIMER_TMCR_TMnUPDOWN(n)       \
 135                 | TIMER_TMCR_TMnOFENABLE(n)     \
 136                 | TIMER_TMCR_TMnCLOCK(n)        \
 137                 | TIMER_TMCR_TMnENABLE(n) )
 138 #define GEMINI_TIMER_INTRSTATE          0x34                                            /* rw */
 139 #define  TIMER_INTRSTATE_Resv           __BITS(31,9)
 140 #define  TIMER_INTRSTATE_TMnOVFLOW(n)   __BIT((((n) -1) * 3) + 2)
 141 #define  TIMER_INTRSTATE_TMnMATCH2(n)   __BIT((((n) -1) * 3) + 1)
 142 #define  TIMER_INTRSTATE_TMnMATCH1(n)   __BIT((((n) -1) * 3) + 0)
 143 #define GEMINI_TIMER_INTRMASK           0x38                                            /* rw */
 144 #define  TIMER_INTRMASK_Resv            __BITS(31,9)
 145 #define  TIMER_INTRMASK_TMnOVFLOW(n)    __BIT((((n) -1) * 3) + 2)
 146 #define  TIMER_INTRMASK_TMnMATCH2(n)    __BIT((((n) -1) * 3) + 1)
 147 #define  TIMER_INTRMASK_TMnMATCH1(n)    __BIT((((n) -1) * 3) + 0)
 148 #define GEMINI_TIMERn_INTRMASK(n) \
 149                 ( TIMER_INTRMASK_TMnOVFLOW(n)   \
 150                 | TIMER_INTRMASK_TMnMATCH2(n)   \
 151                 | TIMER_INTRMASK_TMnMATCH1(n) )
 152
 153 /*
 154  * Gemini SL3516 Interrupt Controller device register offsets and bits
 155  */
 156 #define GEMINI_ICU_IRQ_SOURCE           0x0                                             /* ro */
 157 #define GEMINI_ICU_IRQ_ENABLE           0x4                                             /* rw */
 158 #define GEMINI_ICU_IRQ_CLEAR            0x8                                             /* wo */
 159 #define GEMINI_ICU_IRQ_TRIGMODE         0xc                                             /* rw */
 160 #define  ICU_IRQ_TRIGMODE_EDGE          1               /* edge triggered */
 161 #define  ICU_IRQ_TRIGMODE_LEVEL         0               /* level triggered */
 162 #define GEMINI_ICU_IRQ_TRIGLEVEL        0x10                                            /* rw */
 163 #define  ICU_IRQ_TRIGLEVEL_LO           1               /* active low or falling edge */
 164 #define  ICU_IRQ_TRIGLEVEL_HI           0               /* active high or rising edge */
 165 #define GEMINI_ICU_IRQ_STATUS           0x14                                            /* ro */
 166
 167 #define GEMINI_ICU_FIQ_SOURCE           0x20                                            /* ro */
 168 #define GEMINI_ICU_FIQ_ENABLE           0x24                                            /* rw */
 169 #define GEMINI_ICU_FIQ_CLEAR            0x28                                            /* wo */
 170 #define GEMINI_ICU_FIQ_TRIGMODE         0x2c                                            /* rw */
 171 #define GEMINI_ICU_FIQ_TRIGLEVEL        0x30                                            /* rw */
 172 #define GEMINI_ICU_FIQ_STATUS           0x34                                            /* ro */
 173
 174 #define GEMINI_ICU_REVISION             0x50                                            /* ro */
 175 #define GEMINI_ICU_INPUT_NUM            0x54                                            /* ro */
 176 #define  ICU_INPUT_NUM_RESV             __BITS(31,16)
 177 #define  ICU_INPUT_NUM_IRQ              __BITS(15,8)
 178 #define  ICU_INPUT_NUM_FIQ              __BITS(7,0)
 179 #define GEMINI_ICU_IRQ_DEBOUNCE         0x58                                            /* ro */
 180 #define GEMINI_ICU_FIQ_DEBOUNCE         0x5c                                            /* ro */
 181
 182
 183 /*
 184  * Gemini LPC controller register offsets and bits
 185  */
 186 #define GEMINI_LPCHC_ID                 0x00                                            /* ro */
 187 # define LPCHC_ID_DEVICE                __BITS(31,8)    /* Device ID */
 188 # define LPCHC_ID_REV                   __BITS(7,0)     /* Revision */
 189 # define _LPCHC_ID_DEVICE(r)            ((typeof(r))(((r) & LPCHC_ID_DEVICE) >> 8))
 190 # define _LPCHC_ID_REV(r)               ((typeof(r))(((r) & LPCHC_ID_REV) >> 0))
 191 #define GEMINI_LPCHC_CSR                0x04                                            /* rw */
 192 # define LPCHC_CSR_RESa                 __BITS(31,24)
 193 # define LPCHC_CSR_STO                  __BIT(23)       /* Sync Time Out */
 194 # define LPCHC_CSR_SERR                 __BIT(22)       /* Sync Error */
 195 # define LPCHC_CSR_RESb                 __BITS(21,8)
 196 # define LPCHC_CSR_STOE                 __BIT(7)        /* Sync Time Out Enable */
 197 # define LPCHC_CSR_SERRE                __BIT(6)        /* Sync Error Enable */
 198 # define LPCHC_CSR_RESc                 __BITS(5,1)
 199 # define LPCHC_CSR_BEN                  __BIT(0)        /* Bridge Enable */
 200 #define GEMINI_LPCHC_IRQCTL             0x08                                            /* rw */
 201 # define LPCHC_IRQCTL_RESV              __BITS(31,8)
 202 # define LPCHC_IRQCTL_SIRQEN            __BIT(7)        /* Serial IRQ Enable */
 203 # define LPCHC_IRQCTL_SIRQMS            __BIT(6)        /* Serial IRQ Mode Select */
 204 # define LPCHC_IRQCTL_SIRQFN            __BITS(5,2)     /* Serial IRQ Frame Number */
 205 # define LPCHC_IRQCTL_SIRQFW            __BITS(1,0)     /* Serial IRQ Frame Width */
 206 #  define IRQCTL_SIRQFW_4               0
 207 #  define IRQCTL_SIRQFW_6               1
 208 #  define IRQCTL_SIRQFW_8               2
 209 #  define IRQCTL_SIRQFW_RESV            3
 210 #define GEMINI_LPCHC_SERIRQSTS          0x0c                                            /* rwc */
 211 # define LPCHC_SERIRQSTS_RESV           __BITS(31,17)
 212 #define GEMINI_LPCHC_SERIRQTYP          0x10                                            /* rw */
 213 # define LPCHC_SERIRQTYP_RESV           __BITS(31,17)
 214 #  define SERIRQTYP_EDGE                1
 215 #  define SERIRQTYP_LEVEL               0
 216 #define GEMINI_LPCHC_SERIRQPOLARITY     0x14                                            /* rw */
 217 # define LPCHC_SERIRQPOLARITY_RESV      __BITS(31,17)
 218 #  define SERIRQPOLARITY_HI             1
 219 #  define SERIRQPOLARITY_LO             0
 220 #define GEMINI_LPCHC_SIZE               (GEMINI_LPCHC_SERIRQPOLARITY + 4)
 221 #define GEMINI_LPCHC_NSERIRQ            17
 222
 223 /*
 224  * Gemini GPIO controller register offsets and bits
 225  */
 226 #define GEMINI_GPIO_DATAOUT             0x00            /* Data Out */                  /* rw */
 227 #define GEMINI_GPIO_DATAIN              0x04            /* Data Out */                  /* ro */
 228 #define GEMINI_GPIO_PINDIR              0x08            /* Pin Direction */             /* rw */
 229 #define  GPIO_PINDIR_INPUT              0
 230 #define  GPIO_PINDIR_OUTPUT             1
 231 #define GEMINI_GPIO_PINBYPASS           0x0c            /* Pin Bypass */                /* rw */
 232 #define GEMINI_GPIO_DATASET             0x10            /* Data Set */                  /* wo */
 233 #define GEMINI_GPIO_DATACLR             0x14            /* Data Clear */                /* wo */
 234 #define GEMINI_GPIO_PULLENB             0x18            /* Pullup Enable */             /* rw */
 235 #define GEMINI_GPIO_PULLTYPE            0x1c            /* Pullup Type */               /* rw */
 236 #define  GPIO_PULLTYPE_LOW              0
 237 #define  GPIO_PULLTYPE_HIGH             1
 238 #define GEMINI_GPIO_INTRENB             0x20            /* Interrupt Enable */          /* rw */
 239 #define GEMINI_GPIO_INTRRAWSTATE        0x24            /* Interrupt Raw State */       /* ro */
 240 #define GEMINI_GPIO_INTRMSKSTATE        0x28            /* Interrupt Masked State */    /* ro */
 241 #define GEMINI_GPIO_INTRMASK            0x2c            /* Interrupt Mask */            /* rw */
 242 #define GEMINI_GPIO_INTRCLR             0x30            /* Interrupt Clear */           /* wo */
 243 #define GEMINI_GPIO_INTRTRIG            0x34            /* Interrupt Trigger Method */  /* rw */
 244 #define  GPIO_INTRTRIG_EDGE             0
 245 #define  GPIO_INTRTRIG_LEVEL            1
 246 #define GEMINI_GPIO_INTREDGEBOTH        0x38            /* Both edges trigger Intr. */  /* rw */
 247 #define GEMINI_GPIO_INTRDIR             0x3c            /* edge/level direction */      /* rw */
 248 #define  GPIO_INTRDIR_EDGE_RISING       0
 249 #define  GPIO_INTRDIR_EDGE_FALLING      1
 250 #define  GPIO_INTRDIR_LEVEL_HIGH        0
 251 #define  GPIO_INTRDIR_LEVEL_LOW         1
 252 #define GEMINI_GPIO_BOUNCEENB           0x40            /* Bounce Enable */             /* rw */
 253 #define GEMINI_GPIO_BOUNCESCALE         0x44            /* Bounce Pre-Scale */          /* rw */
 254 #define  GPIO_BOUNCESCALE_RESV          __BITS(31,16)
 255 #define  GPIO_BOUNCESCALE_VAL           __BITS(15,0)    /* NOTE:
 256                                                          * if bounce is enabled, and bounce pre-scale == 0
 257                                                          * then the pin will not detect any interrupt
 258                                                          */
 259 #define GEMINI_GPIO_SIZE                (GEMINI_GPIO_BOUNCESCALE + 4)
 260
 261 /*
 262  * Gemini PCI controller register offsets and bits
 263  */
 264 #define GEMINI_PCI_IOSIZE               0x00            /* I/O Space Size */            /* rw */
 265 #define GEMINI_PCI_PROT                 0x04            /* AHB Protection */            /* rw */
 266 #define GEMINI_PCI_PCICTRL              0x08            /* PCI Control Signal */        /* rw */
 267 #define GEMINI_PCI_ERREN                0x0c            /* Soft Reset Counter and
 268                                                          * Response Error Enable */     /* rw */
 269 #define GEMINI_PCI_SOFTRST              0x10            /* Soft Reset */
 270 #define GEMINI_PCI_CFG_CMD              0x28            /* PCI Configuration Command */ /* rw */
 271 #define  PCI_CFG_CMD_ENB                __BIT(31)       /*  Enable */
 272 #define  PCI_CFG_CMD_RESa               __BITS(30,24)
 273 #define  PCI_CFG_CMD_BUSNO              __BITS(23,16)   /*  Bus      Number */
 274 #define  PCI_CFG_CMD_BUSn(n)            (((n) << 16) & PCI_CFG_CMD_BUSNO)
 275 #define  PCI_CFG_CMD_DEVNO              __BITS(15,11)   /*  Device   Number */
 276 #define  PCI_CFG_CMD_DEVn(n)            (((n) << 11) & PCI_CFG_CMD_DEVNO)
 277 #define  PCI_CFG_CMD_FUNCNO             __BITS(10,8)    /*  Function Number */
 278 #define  PCI_CFG_CMD_FUNCn(n)           (((n) << 8) & PCI_CFG_CMD_FUNCNO)
 279 #define  PCI_CFG_CMD_REGNO              __BITS(7,2)     /*  Register Number */
 280 #define  PCI_CFG_CMD_REGn(n)            (((n) << 0) & PCI_CFG_CMD_REGNO)
 281 #define  PCI_CFG_CMD_RESb               __BITS(1,0)
 282 #define  PCI_CFG_CMD_RESV       \
 283                 (PCI_CFG_CMD_RESa | PCI_CFG_CMD_RESb)
 284 #define GEMINI_PCI_CFG_DATA             0x2c            /* PCI Configuration Data */    /* rw */
 285
 286 /*
 287  * Gemini machine dependent PCI config registers
 288  */
 289 #define GEMINI_PCI_CFG_REG_PMR1         0x40            /* Power Management 1 */        /* rw */
 290 #define GEMINI_PCI_CFG_REG_PMR2         0x44            /* Power Management 2 */        /* rw */
 291 #define GEMINI_PCI_CFG_REG_CTL1         0x48            /* Control 1 */                 /* rw */
 292 #define GEMINI_PCI_CFG_REG_CTL2         0x4c            /* Control 2 */                 /* rw */
 293 #define  PCI_CFG_REG_CTL2_INTSTS        __BITS(31,28)
 294 #define   CFG_REG_CTL2_INTSTS_INTD      __BIT(28 + 3)
 295 #define   CFG_REG_CTL2_INTSTS_INTC      __BIT(28 + 2)
 296 #define   CFG_REG_CTL2_INTSTS_INTB      __BIT(28 + 1)
 297 #define   CFG_REG_CTL2_INTSTS_INTA      __BIT(28 + 0)
 298 #define  PCI_CFG_REG_CTL2_INTMASK       __BITS(27,16)
 299 #define   CFG_REG_CTL2_INTMASK_CMDERR   __BIT(16 + 11)
 300 #define   CFG_REG_CTL2_INTMASK_PARERR   __BIT(16 + 10)
 301 #define   CFG_REG_CTL2_INTMASK_INTD     __BIT(16 + 9)
 302 #define   CFG_REG_CTL2_INTMASK_INTC     __BIT(16 + 8)
 303 #define   CFG_REG_CTL2_INTMASK_INTB     __BIT(16 + 7)
 304 #define   CFG_REG_CTL2_INTMASK_INTA     __BIT(16 + 6)
 305 #define   CFG_REG_CTL2_INTMASK_INT_ABCD __BITS(16+9,16+6)
 306 #define   CFG_REG_CTL2_INTMASK_MABRT_RX __BIT(16 + 5)
 307 #define   CFG_REG_CTL2_INTMASK_TABRT_RX __BIT(16 + 4)
 308 #define   CFG_REG_CTL2_INTMASK_TABRT_TX __BIT(16 + 3)
 309 #define   CFG_REG_CTL2_INTMASK_RETRY4   __BIT(16 + 2)
 310 #define   CFG_REG_CTL2_INTMASK_SERR_RX  __BIT(16 + 1)
 311 #define   CFG_REG_CTL2_INTMASK_PERR_RX  __BIT(16 + 0)
 312 #define  PCI_CFG_REG_CTL2_RESa          __BIT(15)
 313 #define  PCI_CFG_REG_CTL2_MSTPRI        __BITS(14,8)
 314 #define   CFG_REG_CTL2_MSTPRI_REQn(n)   __BIT(8 + (n))
 315 #define  PCI_CFG_REG_CTL2_RESb          __BITS(7,4)
 316 #define  PCI_CFG_REG_CTL2_TRDYW         __BITS(3,0)
 317 #define  PCI_CFG_REG_CTL2_RESV  \
 318                 (PCI_CFG_REG_CTL2_RESa | PCI_CFG_REG_CTL2_RESb)
 319 #define GEMINI_PCI_CFG_REG_MEM1         0x50            /* Memory 1 Base */             /* rw */
 320 #define GEMINI_PCI_CFG_REG_MEM2         0x54            /* Memory 2 Base */             /* rw */
 321 #define GEMINI_PCI_CFG_REG_MEM3         0x58            /* Memory 3 Base */             /* rw */
 322 #define  PCI_CFG_REG_MEM_BASE_MASK      __BITS(31,20)
 323 #define  PCI_CFG_REG_MEM_BASE(base)     ((base) & PCI_CFG_REG_MEM_BASE_MASK)
 324 #define  PCI_CFG_REG_MEM_SIZE_MASK      __BITS(19,16)
 325 #define  PCI_CFG_REG_MEM_SIZE_1MB       (0x0 << 16)
 326 #define  PCI_CFG_REG_MEM_SIZE_2MB       (0x1 << 16)
 327 #define  PCI_CFG_REG_MEM_SIZE_4MB       (0x2 << 16)
 328 #define  PCI_CFG_REG_MEM_SIZE_8MB       (0x3 << 16)
 329 #define  PCI_CFG_REG_MEM_SIZE_16MB      (0x4 << 16)
 330 #define  PCI_CFG_REG_MEM_SIZE_32MB      (0x5 << 16)
 331 #define  PCI_CFG_REG_MEM_SIZE_64MB      (0x6 << 16)
 332 #define  PCI_CFG_REG_MEM_SIZE_128MB     (0x7 << 16)
 333 #define  PCI_CFG_REG_MEM_SIZE_256MB     (0x8 << 16)
 334 #define  PCI_CFG_REG_MEM_SIZE_512MB     (0x9 << 16)
 335 #define  PCI_CFG_REG_MEM_SIZE_1GB       (0xa << 16)
 336 #define  PCI_CFG_REG_MEM_SIZE_2GB       (0xb << 16)
 337 #define  PCI_CFG_REG_MEM_RESV           __BITS(19,16)
 338
 339 #ifndef _LOCORE
 340 static inline unsigned int
 341 gemini_pci_cfg_reg_mem_size(size_t sz)
 342 {
 343         switch (sz) {
 344         case (1 << 20):
 345                 return PCI_CFG_REG_MEM_SIZE_1MB;
 346         case (2 << 20):
 347                 return PCI_CFG_REG_MEM_SIZE_2MB;
 348         case (4 << 20):
 349                 return PCI_CFG_REG_MEM_SIZE_4MB;
 350         case (8 << 20):
 351                 return PCI_CFG_REG_MEM_SIZE_8MB;
 352         case (16 << 20):
 353                 return PCI_CFG_REG_MEM_SIZE_16MB;
 354         case (32 << 20):
 355                 return PCI_CFG_REG_MEM_SIZE_32MB;
 356         case (64 << 20):
 357                 return PCI_CFG_REG_MEM_SIZE_64MB;
 358         case (128 << 20):
 359                 return PCI_CFG_REG_MEM_SIZE_128MB;
 360         case (256 << 20):
 361                 return PCI_CFG_REG_MEM_SIZE_256MB;
 362         case (512 << 20):
 363                 return PCI_CFG_REG_MEM_SIZE_512MB;
 364         case (1024 << 20):
 365                 return PCI_CFG_REG_MEM_SIZE_1GB;
 366         case (2048 << 20):
 367                 return PCI_CFG_REG_MEM_SIZE_2GB;
 368         default:
 369                 panic("gemini_pci_cfg_reg_mem_size: bad size %#lx\n", sz);
 370         }
 371         /* NOTREACHED */
 372 }
 373 #endif  /* _LOCORE */
 374
 375 /*
 376  * Gemini SL3516 IDE device register offsets, &etc.
 377  */
 378 #define GEMINI_MIDE_NCHAN               2
 379 #define GEMINI_MIDE_OFFSET(chan)        ((chan == 0) ? 0x0 : 0x400000)
 380 #define GEMINI_MIDE_BASEn(chan)         (GEMINI_MIDE_BASE + GEMINI_MIDE_OFFSET(chan))
 381 #define GEMINI_MIDE_CMDBLK              0x20
 382 #define GEMINI_MIDE_CTLBLK              0x36
 383 #define GEMINI_MIDE_SIZE                0x40
 384
 385
 386 /*
 387  * Gemini DRAM Controller register offsets, &etc.
 388  */
 389 #define GEMINI_DRAMC_RMCR               0x40            /* CPU Remap Control */                         /* rw */
 390 #define  DRAMC_RMCR_RESa                __BITS(31,29)
 391 #define  DRAMC_RMCR_RMBAR               __BITS(28,20)   /* Remap Base Address */
 392 #define  DRAMC_RMCR_RMBAR_SHFT          20
 393 #define  DRAMC_RMCR_RESb                __BITS(19,9)
 394 #define  DRAMC_RMCR_RMSZR               __BITS(8,0)     /* Remap Size Address */
 395 #define  DRAMC_RMCR_RMSZR_SHFT          0
 396
 397 #else
 398 # error unknown gemini cpu type
 399 #endif
 400
 401 #endif  /* _ARM_GEMINI_REG_H_ */