sys/arch/arm/ixp12x0/ixp12x0_clkreg.h

   1 /*      $NetBSD: ixp12x0_clkreg.h,v 1.3 2003/03/06 06:14:16 igy Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002
   5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
  20  * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  21  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * IXP12X0 TIMER registers
  31  *  TIMER_1 v0xf0010300 p0x42000300
  32  *  TIMER_2 v0xf0010320 p0x42000320
  33  *  TIMER_3 v0xf0010340 p0x42000340
  34  *  TIMER_4 v0xf0010360 p0x42000360
  35  */
  36
  37 #ifndef _IXP12X0_CLKREG_H_
  38 #define _IXP12X0_CLKREG_H_
  39
  40 #include <arm/ixp12x0/ixp12x0reg.h>
  41
  42 #define IXPCLK_PLL_CFG_OFFSET   (0x90000c00U - 0x42000300U)
  43 #define IXPCLK_PLL_CFG_SIZE     0x04
  44
  45 /* timer load register */
  46 #define IXPCLK_LOAD             0x00000000
  47 #define IXPCL_ITV               0x00ffffff
  48
  49 /* timer value register */
  50 #define IXPCLK_VALUE            0x00000004
  51 #define IXPCL_CTV               0x00ffffff
  52
  53 /* timer control register */
  54 #define IXPCLK_CONTROL          0x00000008
  55 #define IXPCL_STP               0x0c
  56 #define  IXPCL_STP_CORE         0x00
  57 #define  IXPCL_STP_DIV16        0x04
  58 #define  IXPCL_STP_DIV256       0x08
  59 #define IXPCL_MODE              0x40
  60 #define  IXPCL_FREERUN          0x00
  61 #define  IXPCL_PERIODIC         0x40
  62 #define IXPCL_EN                0x80
  63 #define  IXPCL_DISABLE          0x00
  64 #define  IXPCL_ENABLE           0x80
  65
  66 /* timer clear register */
  67 #define IXPCLK_CLEAR            0x0000000c
  68 #define IXPT_CLEAR              0
  69
  70 /*
  71  * IXP12X0 real time clock registers
  72  * RTC_DIV      0x90002000
  73  * RTC_TINT     0x90002400
  74  * RTC_TVAL     0x90002800
  75  * RTC_CNTR     0x90002c00
  76  * RTC_ALM      0x90003000
  77  */
  78
  79 /* RTC_DIV register */
  80 #define RTC_DIV         0x90002000
  81 #define RTC_RDIV        0x0000ffff
  82 #define RTC_WEN         0x00010000
  83 #define  RTC_WDIVISER   0x00000000
  84 #define  RTC_WINTONLY   0x00010000
  85 #define RTC_IEN         0x00020000
  86 #define  RTC_IEN_E      0x00020000
  87 #define  RTC_IEN_D      0x00000000
  88 #define RTC_IRST        0x00040000
  89 #define  RTC_IRST_NOCLR 0x00040000
  90 #define  RTC_IRST_CLR   0x00000000
  91 #define RTC_IRQS        0x00080000
  92 #define  RTC_IRQS_IRQ   0x00080000
  93 #define  RTC_IRQS_FIQ   0x00000000
  94
  95
  96 /* RTC_TINT register */
  97 #define RTC_TINT        0x90002400
  98 #define RTC_RTINT       0x0000ffff
  99
 100 /* RTC_TVAL register */
 101 #define RTC_TVAL        0x90002800
 102 #define RTC_TVAL_TVAL   0x0000ffff
 103 #define RTC_LD          0x00010000
 104 #define  RTC_LD_LOAD    0x00010000
 105 #define  RTC_LD_NOLOAD  0x00000000
 106 #define RTC_PRE         0x00020000
 107 #define  RTC_PRE_SYSCLK 0x00020000
 108 #define  RTC_PRE_DIV128 0x00000000
 109
 110 /* RTC_CNTR register */
 111 #define RTC_CNTR        0x90002c00
 112 #define RTC_RCN_COUNT   0xffffffff
 113
 114 /* RTC_ALM register */
 115 #define RTC_ALM         0x90003000
 116 #define RTC_RTC_ALARM   0xffffffff
 117
 118 #endif /* _IXP12X0_CLKREG_H_ */