sys/arch/arm/ixp12x0/ixp12x0_pcireg.h

   1 /*      $NetBSD: ixp12x0_pcireg.h,v 1.2 2003/02/17 20:51:52 ichiro Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002, 2003
   5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
  20  * HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  21  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef _IXP12X0_PCIREG_H_
  30 #define _IXP12X0_PCIREG_H_
  31
  32 #include <arm/ixp12x0/ixp12x0reg.h>
  33
  34 /* PCI Configuration Space Registers */
  35
  36 /* base address */
  37 #define IXP_PCI_MEM_BAR         0x10
  38 # define IXP1200_PCI_MEM_BAR    0x40000000UL
  39 # define IXP_PCI_MEM_BAR_MASK   0xffffff80
  40
  41 #define IXP_PCI_IO_BAR          0x14
  42 # define IXP1200_PCI_IO_BAR     0x0000f000UL
  43 # define IXP_PCI_IO_BAR_MASK    0xffffff80
  44
  45 #define IXP_PCI_DRAM_BAR        0x18
  46 # define IXP1200_PCI_DRAM_BAR   0x00000000UL
  47 # define IXP_PCI_DRAM_BAR_MASK  0xfffc0000
  48
  49 #define PCI_CAP_PTR             0x34
  50 #define PCI_INT_LINE            0x3C
  51 #define MAILBOX_0               0x50
  52 #define MAILBOX_1               0x54
  53 #define MAILBOX_2               0x58
  54 #define MAILBOX_3               0x5C
  55 #define DOORBELL                0x60
  56 #define DOORBELL_SETUP          0x64
  57 #define ROM_BYTE_WRITE          0x68
  58 #define CAP_PTR_EXT             0x70
  59 #define PWR_MGMT                0x74
  60
  61 /* Reset Registers*/
  62 #define IXPPCI_IXP1200_RESET    0x7C
  63 # define RESET_UE0              (1U << 0)
  64 # define RESET_UE1              (1U << 1)
  65 # define RESET_UE2              (1U << 2)
  66 # define RESET_UE3              (1U << 3)
  67 # define RESET_UE4              (1U << 4)
  68 # define RESET_UE5              (1U << 5)
  69 # define RESET_PCIRST           (1U << 14)
  70 # define RESET_EXRST            (1U << 15)
  71 # define RESET_FBI              (1U << 16)
  72 # define RESET_CMDARB           (1U << 17)
  73 # define RESET_SDRAM            (1U << 18)
  74 # define RESET_SRAM             (1U << 29)
  75 # define RESET_PCI              (1U << 30)
  76 # define RESET_SACORE           (1U << 31)
  77
  78 # define RESET_FULL             (RESET_UE0 | RESET_UE1 | RESET_UE2 | \
  79                                  RESET_UE3 | RESET_UE4 | RESET_UE5 | \
  80                                  RESET_EXRST | RESET_FBI | \
  81                                  RESET_CMDARB | RESET_SDRAM | RESET_SRAM | \
  82                                  RESET_PCI | RESET_SACORE)
  83
  84 #define CHAN_1_BYTE_COUNT       0x80
  85 #define CHAN_1_PCI_ADDR         0x84
  86 #define CHAN_1_DRAM_ADDR        0x88
  87 #define CHAN_1_DESC_PTR         0x8C
  88 #define CHAN_1_CONTROL          0x90
  89 #define DMA_INF_MODE            0x9C
  90 #define CHAN_2_BYTE_COUNT       0xA0
  91 #define CHAN_2_PCI_ADDR         0xA4
  92 #define CHAN_2_DRAM_ADDR        0xA8
  93 #define CHAN_2_DESC_PTR         0xAC
  94 #define CHAN_2_CONTROL          0xB0
  95
  96 #define CSR_BASE_ADDR_MASK      0x0F8
  97 #define CSR_BASE_ADDR_OFF       0xFC
  98 # define CSR_BASE_ADDR_MASK_1M  0x000c0000UL
  99
 100 #define DRAM_BASE_ADDR_MASK     0x100
 101 #define DRAM_BASE_ADDR_OFF      0x104
 102 # define DRAM_BASE_ADDR_MASK_256MB      0x0ffc0000UL
 103
 104 #define ROM_BASE_ADDR_MASK      0x108
 105 #define DRAM_TIMING             0x10C
 106 #define DRAM_ADDR_SIZE_0        0x110
 107 #define DRAM_ADDR_SIZE_1        0x114
 108 #define DRAM_ADDR_SIZE_2        0x118
 109 #define DRAM_ADDR_SIZE_3        0x11C
 110 #define I2O_IFH                 0x120
 111 #define I2O_IPT                 0x124
 112 #define I2O_OPH                 0x128
 113 #define I2O_OFT                 0x12C
 114 #define I2O_IFC                 0x130
 115 #define I2O_OPC                 0x134
 116 #define I2O_IPC                 0x138
 117 #define SA_CONTROL              0x13C
 118 # define SA_CONTROL_PNR         (1 << 9)
 119 # define SA_CONTROL_COMPLETE    (1 << 0)
 120 #define PCI_ADDR_EXT            0x140
 121 # define PCI_ADDR_EXT_PIOADD(x) ((x) & 0xffff0000)
 122 # define PCI_ADDR_EXT_PMSA(x)   (((x) & 0xe0000000) >> 16)
 123 #define PREFETCH_RANGE          0x144
 124 #define PCI_ABITOR_STATUS       0x148
 125 #define DBELL_PCI_MASK          0x150
 126 #define DBELL_SA_MASK           0x154
 127
 128 /*
 129  * Interrupt index assignment
 130  *
 131  *     FIQ/IRQ bitmap in "PCI Registers Accessible Through StrongARM Core"
 132  *
 133  *        3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 134  * bit    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 135  *       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------+-+-+-+-+---+-+-+
 136  *       |D|R|R|D|D|P|I|S|R|S|D|D| |P|D|D|D|             |T|T|T|T|   |S| |
 137  *       |P|T|M|P|T|W|I|D|S|B|M|M|R|I|M|M|F|             |4|3|2|1|   |I| |
 138  *       |E|A|A|E|E|R|P|P|E| |A|A|E|L|A|A|H|     RES     | | | | |RES| | |
 139  *       | | | |D| |M| |A|R| |2|1|S| |2|1| |             | | | | |   | | |
 140  *       | | | | | | | |R|R| |N|N| | | | | |             | | | | |   | | |
 141  *       | | | | | | | | | | |B|B| | | | | |             | | | | |   | | |
 142  *       +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------+-+-+-+-+---+-+-+
 143  *        3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
 144  * index  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5               7 6 5 4     1 0
 145  *
 146  */
 147
 148 /* PCI_IRQ_STATUS */
 149 #define IXPPCI_IRQ_STATUS       (IXP12X0_PCI_VBASE + 0x180)
 150 #define IXPPCI_FIQ_STATUS       (IXP12X0_PCI_VBASE + 0x280)
 151 #define IXPPCI_IRQ_RAW_STATUS   (IXP12X0_PCI_VBASE + 0x184)
 152 #define IXPPCI_FIQ_RAW_STATUS   (IXP12X0_PCI_VBASE + 0x284)
 153 #define IXPPCI_IRQ_ENABLE       (IXP12X0_PCI_VBASE + 0x188)
 154 #define IXPPCI_FIQ_ENABLE       (IXP12X0_PCI_VBASE + 0x288)
 155 #define IXPPCI_IRQ_ENABLE_SET   (IXP12X0_PCI_VBASE + 0x188)
 156 #define IXPPCI_FIQ_ENABLE_SET   (IXP12X0_PCI_VBASE + 0x288)
 157 #define IXPPCI_IRQ_ENABLE_CLEAR (IXP12X0_PCI_VBASE + 0x18c)
 158 #define IXPPCI_FIQ_ENABLE_CLEAR (IXP12X0_PCI_VBASE + 0x28c)
 159 #define IXPPCI_IRQ_SOFT         (IXP12X0_PCI_VBASE + 0x190)
 160 #define IXPPCI_FIQ_SOFT         (IXP12X0_PCI_VBASE + 0x290)
 161 #define IXPPCI_IRQST_TIMER      (IXP12X0_PCI_VBASE + 0x010)
 162
 163 #define IXPPCI_INTR_DPE         63
 164 #define IXPPCI_INTR_RTA         62
 165 #define IXPPCI_INTR_RMA         61
 166 #define IXPPCI_INTR_DPED        60
 167 #define IXPPCI_INTR_DTE         59
 168 #define IXPPCI_INTR_PWRM        58
 169 #define IXPPCI_INTR_IIP         57
 170 #define IXPPCI_INTR_SDPAR       56
 171 #define IXPPCI_INTR_RSERR       55
 172 #define IXPPCI_INTR_SB          54
 173 #define IXPPCI_INTR_DMA2NB      53
 174 #define IXPPCI_INTR_DMA1NB      52
 175 #define IXPPCI_INTR_bit19       51
 176 #define IXPPCI_INTR_PIL         50
 177 #define IXPPCI_INTR_DMA2        49
 178 #define IXPPCI_INTR_DMA1        48
 179 #define IXPPCI_INTR_DFH         47
 180 #define IXPPCI_INTR_bit14       46
 181 #define IXPPCI_INTR_bit13       45
 182 #define IXPPCI_INTR_bit12       44
 183 #define IXPPCI_INTR_bit11       43
 184 #define IXPPCI_INTR_bit10       42
 185 #define IXPPCI_INTR_bit9        41
 186 #define IXPPCI_INTR_bit8        40
 187 #define IXPPCI_INTR_T4          39
 188 #define IXPPCI_INTR_T3          38
 189 #define IXPPCI_INTR_T2          37
 190 #define IXPPCI_INTR_T1          36
 191 #define IXPPCI_INTR_bit3        35
 192 #define IXPPCI_INTR_bit2        34
 193 #define IXPPCI_INTR_SI          33
 194 #define IXPPCI_INTR_bit0        32
 195
 196 #endif /* _IXP12X0_PCIREG_H_ */