sys/arch/arm/omap/omap2_gpio.c

   1 /*      $NetBSD: omap2_gpio.c,v 1.6 2008/11/19 06:26:27 matt Exp $      */
   2 /*-
   3  * Copyright (c) 2007 The NetBSD Foundation, Inc.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to The NetBSD Foundation
   7  * by Matt Thomas
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28  * POSSIBILITY OF SUCH DAMAGE.
  29  */
  30 #include <sys/cdefs.h>
  31 __KERNEL_RCSID(0, "$NetBSD: omap2_gpio.c,v 1.6 2008/11/19 06:26:27 matt Exp $");
  32
  33 #define _INTR_PRIVATE
  34
  35 #include "locators.h"
  36 #include "gpio.h"
  37 #include "opt_omap.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/evcnt.h>
  41 #include <sys/atomic.h>
  42
  43 #include <uvm/uvm_extern.h>
  44
  45 #include <machine/intr.h>
  46
  47 #include <arm/cpu.h>
  48 #include <arm/armreg.h>
  49 #include <arm/cpufunc.h>
  50
  51 #include <machine/bus.h>
  52
  53 #include <arm/omap/omap2_reg.h>
  54 #include <arm/omap/omap2_obiovar.h>
  55 #include <arm/pic/picvar.h>
  56
  57 #if NGPIO > 0
  58 #include <sys/gpio.h>
  59 #include <dev/gpio/gpiovar.h>
  60 #endif
  61
  62 static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
  63 static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
  64 static int gpio_pic_find_pending_irqs(struct pic_softc *);
  65 static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *);
  66
  67 const struct pic_ops gpio_pic_ops = {
  68         .pic_block_irqs = gpio_pic_block_irqs,
  69         .pic_unblock_irqs = gpio_pic_unblock_irqs,
  70         .pic_find_pending_irqs = gpio_pic_find_pending_irqs,
  71         .pic_establish_irq = gpio_pic_establish_irq,
  72 };
  73
  74 struct gpio_softc {
  75         device_t gpio_dev;
  76         struct pic_softc gpio_pic;
  77         struct intrsource *gpio_is;
  78         bus_space_tag_t gpio_memt;
  79         bus_space_handle_t gpio_memh;
  80         uint32_t gpio_enable_mask;
  81         uint32_t gpio_edge_mask;
  82         uint32_t gpio_edge_falling_mask;
  83         uint32_t gpio_edge_rising_mask;
  84         uint32_t gpio_level_mask;
  85         uint32_t gpio_level_hi_mask;
  86         uint32_t gpio_level_lo_mask;
  87         uint32_t gpio_inuse_mask;
  88 #if NGPIO > 0
  89         struct gpio_chipset_tag gpio_chipset;
  90         gpio_pin_t gpio_pins[32];
  91 #endif
  92 };
  93
  94 #define PIC_TO_SOFTC(pic) \
  95         ((struct gpio_softc *)((char *)(pic) - \
  96                 offsetof(struct gpio_softc, gpio_pic)))
  97
  98 #define GPIO_READ(gpio, reg) \
  99         bus_space_read_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg))
 100 #define GPIO_WRITE(gpio, reg, val) \
 101         bus_space_write_4((gpio)->gpio_memt, (gpio)->gpio_memh, (reg), (val))
 102
 103 void
 104 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
 105 {
 106         struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
 107         KASSERT(irq_base == 0);
 108
 109         gpio->gpio_enable_mask |= irq_mask;
 110         /*
 111          * If this a level source, ack it now.  If it's still asserted
 112          * it'll come back.
 113          */
 114         GPIO_WRITE(gpio, GPIO_SETIRQENABLE1, gpio->gpio_enable_mask);
 115         if (irq_mask & gpio->gpio_level_mask)
 116                 GPIO_WRITE(gpio, GPIO_IRQSTATUS1,
 117                     irq_mask & gpio->gpio_level_mask);
 118 }
 119
 120 void
 121 gpio_pic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
 122 {
 123         struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
 124         KASSERT(irq_base == 0);
 125
 126         gpio->gpio_enable_mask &= ~irq_mask;
 127         GPIO_WRITE(gpio, GPIO_CLEARIRQENABLE1, irq_mask);
 128         /*
 129          * If any of the sources are edge triggered, ack them now so
 130          * we won't lose them.
 131          */
 132         if (irq_mask & gpio->gpio_edge_mask)
 133                 GPIO_WRITE(gpio, GPIO_IRQSTATUS1,
 134                     irq_mask & gpio->gpio_edge_mask);
 135 }
 136
 137 int
 138 gpio_pic_find_pending_irqs(struct pic_softc *pic)
 139 {
 140         struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
 141         uint32_t v;
 142         uint32_t pending;
 143
 144         v = GPIO_READ(gpio, GPIO_IRQSTATUS1);
 145         pending = (v & gpio->gpio_enable_mask);
 146         if (pending == 0)
 147                 return 0;
 148
 149         /*
 150          * Now find all the pending bits and mark them as pending.
 151          */
 152         (void) pic_mark_pending_sources(&gpio->gpio_pic, 0, pending);
 153
 154         return 1;
 155 }
 156
 157 void
 158 gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
 159 {
 160         struct gpio_softc * const gpio = PIC_TO_SOFTC(pic);
 161         KASSERT(is->is_irq < 32);
 162         uint32_t irq_mask = __BIT(is->is_irq);
 163         uint32_t v;
 164 #if 0
 165         unsigned int i;
 166         struct intrsource *maybe_is;
 167 #endif
 168
 169         /*
 170          * Make sure the irq isn't enabled and not asserting.
 171          */
 172         gpio->gpio_enable_mask &= ~irq_mask;
 173         GPIO_WRITE(gpio, GPIO_IRQENABLE1, gpio->gpio_enable_mask);
 174         GPIO_WRITE(gpio, GPIO_IRQSTATUS1, irq_mask);
 175
 176         /*
 177          * Convert the type to a gpio type and figure out which bits in what
 178          * register we have to tweak.
 179          */
 180         gpio->gpio_edge_rising_mask &= ~irq_mask;
 181         gpio->gpio_edge_falling_mask &= ~irq_mask;
 182         gpio->gpio_level_hi_mask &= ~irq_mask;
 183         gpio->gpio_level_lo_mask &= ~irq_mask;
 184         switch (is->is_type) {
 185         case IST_LEVEL_LOW: gpio->gpio_level_lo_mask |= irq_mask; break;
 186         case IST_LEVEL_HIGH: gpio->gpio_level_hi_mask |= irq_mask; break;
 187         case IST_EDGE_FALLING: gpio->gpio_edge_falling_mask |= irq_mask; break;
 188         case IST_EDGE_RISING: gpio->gpio_edge_rising_mask |= irq_mask; break;
 189         }
 190         gpio->gpio_edge_mask =
 191             gpio->gpio_edge_rising_mask | gpio->gpio_edge_falling_mask;
 192         gpio->gpio_level_mask =
 193             gpio->gpio_level_hi_mask|gpio->gpio_level_lo_mask;
 194         gpio->gpio_inuse_mask |= irq_mask;
 195
 196         /*
 197          * Set the interrupt type.
 198          */
 199         GPIO_WRITE(gpio, GPIO_LEVELDETECT0, gpio->gpio_level_lo_mask);
 200         GPIO_WRITE(gpio, GPIO_LEVELDETECT1, gpio->gpio_level_hi_mask);
 201         GPIO_WRITE(gpio, GPIO_RISINGDETECT, gpio->gpio_edge_rising_mask);
 202         GPIO_WRITE(gpio, GPIO_FALLINGDETECT, gpio->gpio_edge_falling_mask);
 203
 204         /*
 205          * Mark it as input.
 206          */
 207         v = GPIO_READ(gpio, GPIO_OE);
 208         v |= irq_mask;
 209         GPIO_WRITE(gpio, GPIO_OE, v);
 210 #if 0
 211         for (i = 0, maybe_is = NULL; i < 32; i++) {
 212                 if ((is = pic->pic_sources[i]) != NULL) {
 213                         if (maybe_is == NULL || is->is_ipl > maybe_is->is_ipl)
 214                                 maybe_is = is;
 215                 }
 216         }
 217         if (maybe_is != NULL) {
 218                 is = gpio->gpio_is;
 219                 KASSERT(is != NULL);
 220                 is->is_ipl = maybe_is->is_ipl;
 221                 (*is->is_pic->pic_ops->pic_establish_irq)(is->is_pic, is);
 222         }
 223 #endif
 224 }
 225
 226 static int gpio_match(device_t, cfdata_t, void *);
 227 static void gpio_attach(device_t, device_t, void *);
 228
 229 CFATTACH_DECL_NEW(omap2gpio,
 230         sizeof(struct gpio_softc),
 231         gpio_match, gpio_attach,
 232         NULL, NULL);
 233
 234 #if NGPIO > 0
 235
 236 static int
 237 omap2gpio_pin_read(void *arg, int pin)
 238 {
 239         struct gpio_softc * const gpio = arg;
 240
 241         return (GPIO_READ(gpio, GPIO_DATAIN) >> pin) & 1;
 242 }
 243
 244 static void
 245 omap2gpio_pin_write(void *arg, int pin, int value)
 246 {
 247         struct gpio_softc * const gpio = arg;
 248         uint32_t mask = 1 << pin;
 249         uint32_t old, new;
 250
 251         old = GPIO_READ(gpio, GPIO_DATAOUT);
 252         if (value)
 253                 new = old | mask;
 254         else
 255                 new = old & ~mask;
 256
 257         if (old != new)
 258                 GPIO_WRITE(gpio, GPIO_DATAOUT, new);
 259 }
 260
 261 static void
 262 omap2gpio_pin_ctl(void *arg, int pin, int flags)
 263 {
 264         struct gpio_softc * const gpio = arg;
 265         uint32_t mask = 1 << pin;
 266         uint32_t old, new;
 267
 268         old = GPIO_READ(gpio, GPIO_OE);
 269         new = old;
 270         switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
 271         case GPIO_PIN_INPUT:    new |= mask; break;
 272         case GPIO_PIN_OUTPUT:   new &= ~mask; break;
 273         default:                return;
 274         }
 275         if (old != new)
 276                 GPIO_WRITE(gpio, GPIO_OE, new);
 277 }
 278
 279 static void
 280 gpio_defer(device_t self)
 281 {
 282         struct gpio_softc * const gpio = device_private(self);
 283         struct gpio_chipset_tag * const gp = &gpio->gpio_chipset;
 284         struct gpiobus_attach_args gba;
 285         gpio_pin_t *pins;
 286         uint32_t mask, dir, valueout, valuein;
 287         int pin;
 288
 289         gp->gp_cookie = gpio;
 290         gp->gp_pin_read = omap2gpio_pin_read;
 291         gp->gp_pin_write = omap2gpio_pin_write;
 292         gp->gp_pin_ctl = omap2gpio_pin_ctl;
 293
 294         gba.gba_gc = gp;
 295         gba.gba_pins = gpio->gpio_pins;
 296         gba.gba_npins = __arraycount(gpio->gpio_pins);
 297
 298         dir = GPIO_READ(gpio, GPIO_OE);
 299         valueout = GPIO_READ(gpio, GPIO_DATAOUT);
 300         valuein = GPIO_READ(gpio, GPIO_DATAIN);
 301         for (pin = 0, mask = 1, pins = gpio->gpio_pins;
 302              pin < 32; pin++, mask <<= 1, pins++) {
 303                 pins->pin_num = pin;
 304                 if (gpio->gpio_inuse_mask & mask)
 305                         pins->pin_caps = GPIO_PIN_INPUT;
 306                 else
 307                         pins->pin_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT;
 308                 pins->pin_flags =
 309                     (dir & mask) ? GPIO_PIN_INPUT : GPIO_PIN_OUTPUT;
 310                 pins->pin_state =
 311                     (((dir & mask) ? valuein : valueout) & mask)
 312                         ? GPIO_PIN_HIGH
 313                         : GPIO_PIN_LOW;
 314         }
 315
 316         config_found_ia(self, "gpiobus", &gba, gpiobus_print);
 317 }
 318 #endif /* NGPIO > 0 */
 319
 320 int
 321 gpio_match(device_t parent, cfdata_t cfdata, void *aux)
 322 {
 323         struct obio_attach_args *oa = aux;
 324
 325 #ifdef OMAP_2420
 326         if (oa->obio_addr == GPIO1_BASE_2420
 327             || oa->obio_addr == GPIO2_BASE_2420
 328             || oa->obio_addr == GPIO3_BASE_2420
 329             || oa->obio_addr == GPIO4_BASE_2420)
 330                 return 1;
 331 #endif
 332
 333 #ifdef OMAP_2430
 334         if (oa->obio_addr == GPIO1_BASE_2430
 335             || oa->obio_addr == GPIO2_BASE_2430
 336             || oa->obio_addr == GPIO3_BASE_2430
 337             || oa->obio_addr == GPIO4_BASE_2430
 338             || oa->obio_addr == GPIO5_BASE_2430)
 339                 return 1;
 340 #endif
 341
 342 #ifdef OMAP_3530
 343         if (oa->obio_addr == GPIO1_BASE_3530
 344             || oa->obio_addr == GPIO2_BASE_3530
 345             || oa->obio_addr == GPIO3_BASE_3530
 346             || oa->obio_addr == GPIO4_BASE_3530
 347             || oa->obio_addr == GPIO5_BASE_3530
 348             || oa->obio_addr == GPIO6_BASE_3530)
 349                 return 1;
 350 #endif
 351
 352         return 0;
 353 }
 354
 355 void
 356 gpio_attach(device_t parent, device_t self, void *aux)
 357 {
 358         struct obio_attach_args * const oa = aux;
 359         struct gpio_softc * const gpio = device_private(self);
 360         int error;
 361
 362         gpio->gpio_dev = self;
 363
 364         if (oa->obio_intr == OBIOCF_INTR_DEFAULT)
 365                 panic("\n%s: no intr assigned", device_xname(self));
 366
 367         if (oa->obio_size == OBIOCF_SIZE_DEFAULT)
 368                 panic("\n%s: no size assigned", device_xname(self));
 369
 370         gpio->gpio_memt = oa->obio_iot;
 371         error = bus_space_map(oa->obio_iot, oa->obio_addr, oa->obio_size,
 372             0, &gpio->gpio_memh);
 373
 374         if (error) {
 375                 aprint_error(": failed to map register %#lx@%#lx: %d\n",
 376                     oa->obio_size, oa->obio_addr, error);
 377                 return;
 378         }
 379
 380         if (oa->obio_intrbase != OBIOCF_INTRBASE_DEFAULT) {
 381                 gpio->gpio_pic.pic_ops = &gpio_pic_ops;
 382                 strlcpy(gpio->gpio_pic.pic_name, self->dv_xname,
 383                     sizeof(gpio->gpio_pic.pic_name));
 384                 gpio->gpio_pic.pic_maxsources = 32;
 385                 pic_add(&gpio->gpio_pic, oa->obio_intrbase);
 386                 aprint_normal(": interrupts %d..%d",
 387                     oa->obio_intrbase, oa->obio_intrbase + 31);
 388                 gpio->gpio_is = intr_establish(oa->obio_intr,
 389                     IPL_HIGH, IST_LEVEL, pic_handle_intr, &gpio->gpio_pic);
 390                 KASSERT(gpio->gpio_is != NULL);
 391                 aprint_normal(", intr %d", oa->obio_intr);
 392         }
 393         aprint_normal("\n");
 394 #if NGPIO > 0
 395         config_interrupts(self, gpio_defer);
 396 #endif
 397 }