sys/arch/arm/omap/omap2_mputmrreg.h

   1 /*
   2  * $NetBSD$
   3  *
   4  * OMAP GP Timer Register offsets and values
   5  *
   6  * Copyright (c) 2007 Microsoft
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by Microsoft
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  */
  33 #ifndef _OMAP2_MPUTMRREG_H
  34 #define _OMAP2_MPUTMRREG_H
  35
  36 #define MPU_CNTL_TIMER  0x00
  37 #define  MPU_FREE               (1<<6)
  38 #define  MPU_CLOCK_ENABLE       (1<<5)
  39 #define  MPU_PTV_SHIFT          2
  40 #define  MPU_AR                 (1<<1)
  41 #define  MPU_ST                 (1<<0)
  42 #define MPU_LOAD_TIMER  0x04
  43 #define MPU_READ_TIMER  0x08
  44
  45 #endif  /* _OMAP2_MPUTMRREG_H */