sys/arch/arm/omap/omap_gpioreg.h

   1 /*      $NetBSD: $ */
   2
   3 /*
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain this list of conditions
   8  *    and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce this list of conditions
  10  *    and the following disclaimer in the documentation and/or other materials
  11  *    provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  14  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  15  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ANY
  16  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  17  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  18  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  19  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  20  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  21  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  22  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  23  */
  24
  25 #ifndef _ARM_OMAP_OMAP_GPIOREG_H_
  26 #define _ARM_OMAP_OMAP_GPIOREG_H_
  27
  28 /* OMAP GPIO Controller Registers. */
  29 #define GPIO_REVISION           0x0000
  30 #define GPIO_SYSCONFIG          0x0010
  31 #define GPIO_SYSSTATUS          0x0014
  32 #define GPIO_IRQSTATUS          0x0018
  33 #define GPIO_IRQENABLE          0x001c
  34 #define GPIO_WAKEUPENABLE       0x0028
  35 #define GPIO_DATAIN             0x002c
  36 #define GPIO_DATAOUT            0x0030
  37 #define GPIO_DIRECTION          0x0034
  38 #define GPIO_EDGE_CTRL1         0x0038
  39 #define GPIO_EDGE_CTRL2         0x003C
  40 #define GPIO_CLEAR_IRQENABLE    0x009C
  41 #define GPIO_CLEAR_WAKEUPENA    0x00A8
  42 #define GPIO_CLEAR_DATAOUT      0x00B0
  43 #define GPIO_SET_IRQENABLE      0x00DC
  44 #define GPIO_SET_WAKEUPENA      0x00E8
  45 #define GPIO_SET_DATAOUT        0x00F0
  46
  47 /*
  48  * Most of the OMAP GPIO block's registers have the upper 16
  49  * bits tagged as reserved.
  50  */
  51 #define GPIO_REG_MASK           0x0000FFFF
  52
  53 #define OMAP_GPIO_SIZE  1024
  54 #define GPIO_NPINS      16
  55
  56 #define GPIO_MODULE(pin)        ((pin) / GPIO_NPINS)
  57 #define GPIO_RELNUM(pin)        ((pin) & (GPIO_NPINS - 1))
  58 #define GPIO_BIT(pin)           (1 << GPIO_RELNUM(pin))
  59
  60 /* GPIO_SYSCONFIG bits of interest */
  61
  62 #define GPIO_SYSCONFIG_IDLEMODE         3
  63 #define GPIO_SYSCONFIG_ENAWAKEUP        2
  64 #define GPIO_SYSCONFIG_SOFTRESET        1
  65 #define GPIO_SYSCONFIG_AUTOIDLE         0
  66
  67 /* GPIO_SYSCONFIG IDLEMODE values */
  68
  69 #define GPIO_SYSCONFIG_IDLEMODE_MASK    0x3
  70 #define GPIO_SYSCONFIG_SMARTIDLE        0x2
  71
  72 #endif /* _ARM_OMAP_OMAP_GPIOREG_H_ */