sys/arch/arm/omap/omap_gptmrreg.h

   1 #ifndef _ARM_OMAP_OMAP_GPTMRREG_H_
   2 #define _ARM_OMAP_OMAP_GPTMRREG_H_
   3
   4 /* Registers */
   5 #define TIDR            0x00
   6 #define TIOCP_CFG       0x10
   7 #define TISTAT          0x14
   8 #define TISR            0x18
   9 #define TIER            0x1C
  10 #define TWER            0x20
  11 #define TCLR            0x24
  12 #define TCRR            0x28
  13 #define TLDR            0x2C
  14 #define TTGR            0x30
  15 #define TWPS            0x34
  16 #define TMAR            0x38
  17 #define TCAR            0x3C
  18 #define TSICR           0x40
  19
  20
  21 #define TIDR_TID_REV_MASK               0xF
  22
  23 #define TIOCP_CFG_AUTOIDLE              (1<<0)
  24 #define TIOCP_CFG_SOFTRESET             (1<<1)
  25 #define TIOCP_CFG_ENAWAKEUP             (1<<2)
  26 #define TIOCP_CFG_IDLEMODE_MASK (3<<3)
  27 #define TIOCP_CFG_IDLEMODE(n)   (((n)&0x3)<<3)
  28 #define TIOCP_CFG_EMUFREE               (1<<5)
  29
  30 #define TISTAT_RESETDONE                (1<<0)
  31
  32 #define TISR_MAT_IT_FLAG                (1<<0)
  33 #define TISR_OVF_IT_FLAG                (1<<1)
  34 #define TISR_TCAR_IT_FLAG               (1<<2)
  35
  36 #define TIER_MAT_IT_ENA                 (1<<0)
  37 #define TIER_OVF_IT_ENA                 (1<<1)
  38 #define TIER_TCAR_IT_ENA                (1<<2)
  39
  40 #define TWER_MAT_WUP_ENA                (1<<0)
  41 #define TWER_OVF_WUP_ENA                (1<<2)
  42 #define TWER_TCAR_WUP_ENA               (1<<3)
  43
  44 #define TCLR_ST                                 (1<<0)
  45 #define TCLR_AR                                 (1<<1)
  46 #define TCLR_PTV_MASK                   (7<<2)
  47 #define TCLR_PTV(n)                             ((n)<<2)
  48 #define TCLR_PRE(n)                             ((n)<<5)
  49 #define TCLR_CE                                 (1<<6)
  50 #define TCLR_SCPWM                              (1<<7)
  51 #define TCLR_TCM(n)                             ((n)<<8)
  52 #define TCLR_TCM_MASK                   (3<<8)
  53 #define TCLR_TRG(n)                             ((n)<<10)
  54 #define TCLR_TRG_MASK                   (3<<10)
  55 #define TCLR_PT                                 (1<<12)
  56
  57 #define TCLR_TCM_NONE                   0
  58 #define TCLR_TCM_RISING                 1
  59 #define TCLR_TCM_FALLING                2
  60 #define TCLR_TCM_BOTH                   3
  61
  62 #define TCLR_TRG_NONE                   0
  63 #define TCLR_TRG_OVERFLOW               1
  64 #define TCLR_TRG_OVERFLOW_AND_MATCH 2
  65
  66 #define TWPS_W_PEND__TCLR               (1<<0)
  67 #define TWPS_W_PEND__TCRR               (1<<1)
  68 #define TWPS_W_PEND__TLDR               (1<<2)
  69 #define TWPS_W_PEND__TTGR               (1<<3)
  70 #define TWPS_W_PEND__TMAR               (1<<4)
  71
  72 #define TSICR_POSTED                    (1<<2)
  73 #define TSICR_SFT                               (1<<1)
  74
  75 #endif