sys/arch/arm/s3c2xx0/s3c2xx0_intr.h

   1 /*      $NetBSD: s3c2xx0_intr.h,v 1.12 2008/04/27 18:58:45 matt Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002, 2003 Fujitsu Component Limited
   5  * Copyright (c) 2002, 2003 Genetec Corporation
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the name of The Fujitsu Component Limited nor the name of
  17  *    Genetec corporation may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
  21  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
  25  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 /* Derived from i80321_intr.h */
  36
  37 /*
  38  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
  39  * All rights reserved.
  40  *
  41  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
  42  *
  43  * Redistribution and use in source and binary forms, with or without
  44  * modification, are permitted provided that the following conditions
  45  * are met:
  46  * 1. Redistributions of source code must retain the above copyright
  47  *    notice, this list of conditions and the following disclaimer.
  48  * 2. Redistributions in binary form must reproduce the above copyright
  49  *    notice, this list of conditions and the following disclaimer in the
  50  *    documentation and/or other materials provided with the distribution.
  51  * 3. All advertising materials mentioning features or use of this software
  52  *    must display the following acknowledgement:
  53  *      This product includes software developed for the NetBSD Project by
  54  *      Wasabi Systems, Inc.
  55  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  56  *    or promote products derived from this software without specific prior
  57  *    written permission.
  58  *
  59  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  60  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  61  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  62  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  63  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  64  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  65  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  66  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  67  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  68  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  69  * POSSIBILITY OF SUCH DAMAGE.
  70  */
  71
  72 #ifndef _S3C2XX0_INTR_H_
  73 #define _S3C2XX0_INTR_H_
  74
  75 #include <arm/cpu.h>
  76 #include <arm/armreg.h>
  77 #include <arm/cpufunc.h>
  78 #include <machine/intr.h>
  79
  80 #include <arm/s3c2xx0/s3c2xx0reg.h>
  81
  82 typedef int (* s3c2xx0_irq_handler_t)(void *);
  83
  84 extern volatile uint32_t *s3c2xx0_intr_mask_reg;
  85
  86 extern volatile int intr_mask;
  87 extern volatile int global_intr_mask;
  88 #ifdef __HAVE_FAST_SOFTINTS
  89 extern volatile int softint_pending;
  90 #endif
  91 extern int s3c2xx0_imask[];
  92 extern int s3c2xx0_ilevel[];
  93
  94 void s3c2xx0_update_intr_masks( int, int );
  95
  96 static inline void
  97 s3c2xx0_mask_interrupts(int mask)
  98 {
  99         int save = disable_interrupts(I32_bit);
 100         global_intr_mask &= ~mask;
 101         s3c2xx0_update_hw_mask();
 102         restore_interrupts(save);
 103 }
 104
 105 static inline void
 106 s3c2xx0_unmask_interrupts(int mask)
 107 {
 108         int save = disable_interrupts(I32_bit);
 109         global_intr_mask |= mask;
 110         s3c2xx0_update_hw_mask();
 111         restore_interrupts(save);
 112 }
 113
 114 static inline void
 115 s3c2xx0_setipl(int new)
 116 {
 117         set_curcpl(new);
 118         intr_mask = s3c2xx0_imask[curcpl()];
 119         s3c2xx0_update_hw_mask();
 120 #ifdef __HAVE_FAST_SOFTINTS
 121         update_softintr_mask();
 122 #endif
 123 }
 124
 125
 126 static inline void
 127 s3c2xx0_splx(int new)
 128 {
 129         int psw;
 130
 131         psw = disable_interrupts(I32_bit);
 132         s3c2xx0_setipl(new);
 133         restore_interrupts(psw);
 134
 135 #ifdef __HAVE_FAST_SOFTINTS
 136         cpu_dosoftints();
 137 #endif
 138 }
 139
 140
 141 static inline int
 142 s3c2xx0_splraise(int ipl)
 143 {
 144         int     old, psw;
 145
 146         old = curcpl();
 147         if( ipl > old ){
 148                 psw = disable_interrupts(I32_bit);
 149                 s3c2xx0_setipl(ipl);
 150                 restore_interrupts(psw);
 151         }
 152
 153         return (old);
 154 }
 155
 156 static inline int
 157 s3c2xx0_spllower(int ipl)
 158 {
 159         int old = curcpl();
 160         int psw = disable_interrupts(I32_bit);
 161         s3c2xx0_splx(ipl);
 162         restore_interrupts(psw);
 163         return(old);
 164 }
 165
 166 int     _splraise(int);
 167 int     _spllower(int);
 168 void    splx(int);
 169
 170 #if !defined(EVBARM_SPL_NOINLINE)
 171
 172 #define splx(new)               s3c2xx0_splx(new)
 173 #define _spllower(ipl)          s3c2xx0_spllower(ipl)
 174 #define _splraise(ipl)          s3c2xx0_splraise(ipl)
 175
 176 #endif  /* !EVBARM_SPL_NOINTR */
 177
 178
 179 /*
 180  * interrupt dispatch table.
 181  */
 182 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
 183 struct intrhand {
 184         TAILQ_ENTRY(intrhand) ih_list;  /* link on intrq list */
 185         s3c2xx0_irq_handler_t ih_func;  /* handler */
 186         void *ih_arg;                   /* arg for handler */
 187 };
 188 #endif
 189
 190 struct s3c2xx0_intr_dispatch {
 191 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
 192         TAILQ_HEAD(,intrhand) list;
 193 #else
 194         s3c2xx0_irq_handler_t func;
 195 #endif
 196         void *cookie;           /* NULL for stackframe */
 197         int level;
 198         /* struct evbnt ev; */
 199 };
 200
 201 /* used by s3c2{80,40,41}0 interrupt handler */
 202 void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int );
 203
 204 /* initialize some variable so that splfoo() doesn't touch ileegal
 205    address during bootstrap */
 206 void s3c2xx0_intr_bootstrap(vaddr_t);
 207
 208 #endif /* _S3C2XX0_INTR_H_ */