sys/arch/arm/s3c2xx0/s3c2xx0reg.h

   1 /* $NetBSD: s3c2xx0reg.h,v 1.2.2.3 2004/09/21 13:13:32 skrll Exp $ */
   2
   3 /*
   4  * Copyright (c) 2002, 2003 Fujitsu Component Limited
   5  * Copyright (c) 2002, 2003 Genetec Corporation
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the name of The Fujitsu Component Limited nor the name of
  17  *    Genetec corporation may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
  21  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
  25  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35
  36 /*
  37  * Register definitions common to S3C2800 and S3C24[01]0
  38  */
  39 #ifndef _ARM_S3C2XX0_S3C2XX0REG_H_
  40 #define _ARM_S3C2XX0_S3C2XX0REG_H_
  41
  42 /* UART */
  43 /*
  44  * S3C2800, 2410 and 2400 have a common built-in UART block. However,
  45  * there are small diffs in bit position of some registers.
  46  * Following definitions can be foune in s3c{2800,24x0}reg.h for
  47  * that reason.
  48  *
  49  *  ULCON_IR                 (Infra-red mode)
  50  *  ULCON_PARITY_SHIFT       (Parity mode bit position)
  51  *  UMCON_AFC                (Auto flow control)
  52  *  UMSTAT_DCTS              (CTS change)
  53  */
  54
  55 #define SSCOM_ULCON 0x00 /* UART line control */
  56 /*       ULCON_PARITY_SHIFT and ULCON_IR is defined in s3c{2800,24x0}reg.h */
  57 #define  ULCON_PARITY_NONE  (0<<ULCON_PARITY_SHIFT)
  58 #define  ULCON_PARITY_ODD   (4<<ULCON_PARITY_SHIFT)
  59 #define  ULCON_PARITY_EVEN  (5<<ULCON_PARITY_SHIFT)
  60 #define  ULCON_PARITY_ONE   (6<<ULCON_PARITY_SHIFT)
  61 #define  ULCON_PARITY_ZERO  (7<<ULCON_PARITY_SHIFT)
  62 #define  ULCON_STOP     (1<<2)
  63 #define  ULCON_LENGTH_5 0
  64 #define  ULCON_LENGTH_6 1
  65 #define  ULCON_LENGTH_7 2
  66 #define  ULCON_LENGTH_8 3
  67 #define SSCOM_UCON      0x04    /* UART control */
  68 #define  UCON_TXINT_TYPE        (1<<9)  /* Tx interrupt. 0=pulse,1=level */
  69 #define  UCON_TXINT_TYPE_LEVEL  UCON_TXINT_TYPE
  70 #define  UCON_TXINT_TYPE_PULSE  0
  71 #define  UCON_RXINT_TYPE        (1<<8)  /* Rx interrupt */
  72 #define  UCON_RXINT_TYPE_LEVEL  UCON_RXINT_TYPE
  73 #define  UCON_RXINT_TYPE_PULSE  0
  74 #define  UCON_TOINT     (1<<7)  /* Rx timeout interrupt */
  75 #define  UCON_ERRINT    (1<<6)  /* receive error interrupt */
  76 #define  UCON_LOOP      (1<<5)  /* loopback */
  77 #define  UCON_SBREAK    (1<<4)  /* send break */
  78 #define  UCON_TXMODE_DISABLE (0<<2)
  79 #define  UCON_TXMODE_INT     (1<<2)
  80 #define  UCON_TXMODE_DMA     (2<<2)
  81 #define  UCON_TXMODE_MASK    (3<<2)
  82 #define  UCON_RXMODE_DISABLE (0<<0)
  83 #define  UCON_RXMODE_INT     (1<<0)
  84 #define  UCON_RXMODE_DMA     (2<<0)
  85 #define  UCON_RXMODE_MASK    (3<<0)
  86 #define SSCOM_UFCON     0x08    /* FIFO control */
  87 #define  UFCON_TXTRIGGER_0      (0<<6)
  88 #define  UFCON_TXTRIGGER_4      (1<<6)
  89 #define  UFCON_TXTRIGGER_8      (2<<6)
  90 #define  UFCON_TXTRIGGER_16     (3<<6)
  91 #define  UFCON_RXTRIGGER_4      (0<<4)
  92 #define  UFCON_RXTRIGGER_8      (1<<4)
  93 #define  UFCON_RXTRIGGER_12     (2<<4)
  94 #define  UFCON_RXTRIGGER_16     (3<<4)
  95 #define  UFCON_TXFIFO_RESET     (1<<2)
  96 #define  UFCON_RXFIFO_RESET     (1<<1)
  97 #define  UFCON_FIFO_ENABLE      (1<<0)
  98 #define SSCOM_UMCON     0x0c    /* MODEM control */
  99 /*       UMCON_AFC is defined in s3c{2800,24x0}reg.h */
 100 #define  UMCON_RTS      (1<<0)  /* Request to send */
 101 #define SSCOM_UTRSTAT   0x10    /* Status register */
 102 #define  UTRSTAT_TXSHIFTER_EMPTY   (1<<2)
 103 #define  UTRSTAT_TXEMPTY           (1<<1) /* TX fifo or buffer empty */
 104 #define  UTRSTAT_RXREADY           (1<<0) /* RX fifo or buffer is not empty */
 105 #define SSCOM_UERSTAT   0x14    /* Error status register */
 106 #define  UERSTAT_BREAK    (1<<3) /* Break signal */
 107 #define  UERSTAT_FRAME    (1<<2) /* Frame error */
 108 #define  UERSTAT_PARITY   (1<<1) /* Parity error */
 109 #define  UERSTAT_OVERRUN  (1<<0) /* Overrun */
 110 #define  UERSTAT_ALL_ERRORS (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
 111 #define SSCOM_UFSTAT    0x18    /* Fifo status register */
 112 #define  UFSTAT_TXFULL    (1<<9) /* Tx fifo full */
 113 #define  UFSTAT_RXFULL    (1<<8) /* Rx fifo full */
 114 #define  UFSTAT_TXCOUNT_SHIFT 4         /* TX FIFO count */
 115 #define  UFSTAT_TXCOUNT   (0x0f<<UFSTAT_TXCOUNT_SHIFT)
 116 #define  UFSTAT_RXCOUNT_SHIFT 0         /* RX FIFO count */
 117 #define  UFSTAT_RXCOUNT   (0x0f<<UFSTAT_RXCOUNT_SHIFT)
 118 #define SSCOM_UMSTAT    0x1c    /* Modem status register */
 119 /*       UMSTAT_DCTS is defined in s3c{2800,24x0}reg.h */
 120 #define  UMSTAT_CTS       (1<<0) /* Clear to send */
 121 #if _BYTE_ORDER == _LITTLE_ENDIAN
 122 #define SSCOM_UTXH      0x20    /* Transmit data register */
 123 #define SSCOM_URXH      0x24    /* Receive data register */
 124 #else
 125 #define SSCOM_UTXH      0x23    /* Transmit data register */
 126 #define SSCOM_URXH      0x27    /* Receive data register */
 127 #endif
 128 #define SSCOM_UBRDIV    0x28    /* baud-reate divisor */
 129 #define SSCOM_SIZE  0x2c
 130
 131 /* Interrupt controller (Common to S3c2800/2400X/2410X) */
 132 #define INTCTL_SRCPND   0x00    /* Interrupt request status */
 133 #define INTCTL_INTMOD   0x04    /* Interrupt mode (FIQ/IRQ) */
 134 #define INTCTL_INTMSK   0x08    /* Interrupt mask */
 135
 136 #endif /* _ARM_S3C2XX0_S3C2XX0REG_H_ */