sys/arch/arm/xscale/becc_timer.c

   1 /*      $NetBSD: becc_timer.c,v 1.13 2008/01/06 01:37:57 matt Exp $     */
   2
   3 /*
   4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * Timer/clock support for the ADI Engineering Big Endian Companion Chip.
  40  */
  41
  42 #include <sys/cdefs.h>
  43 __KERNEL_RCSID(0, "$NetBSD: becc_timer.c,v 1.13 2008/01/06 01:37:57 matt Exp $");
  44
  45 #include <sys/param.h>
  46 #include <sys/systm.h>
  47 #include <sys/kernel.h>
  48 #include <sys/atomic.h>
  49 #include <sys/time.h>
  50 #include <sys/timetc.h>
  51
  52 #include <dev/clock_subr.h>
  53
  54 #include <machine/bus.h>
  55 #include <arm/cpufunc.h>
  56
  57 #include <arm/xscale/beccreg.h>
  58 #include <arm/xscale/beccvar.h>
  59
  60 void    (*becc_hardclock_hook)(void);
  61
  62 /*
  63  * Note, since COUNTS_PER_USEC doesn't divide evenly, we round up.
  64  */
  65 #define COUNTS_PER_SEC          BECC_PERIPH_CLOCK
  66 #define COUNTS_PER_USEC         ((COUNTS_PER_SEC / 1000000) + 1)
  67
  68 static void *clock_ih;
  69
  70 static u_int    becc_get_timecount(struct timecounter *);
  71
  72 static struct timecounter becc_timecounter = {
  73         becc_get_timecount,     /* get_timecount */
  74         0,                      /* no poll_pps */
  75         0xffffffff,             /* counter_mask */
  76         COUNTS_PER_SEC,         /* frequency */
  77         "becc",                 /* name */
  78         100,                    /* quality */
  79         NULL,                   /* prev */
  80         NULL,                   /* next */
  81 };
  82
  83 static volatile uint32_t becc_base;
  84
  85 /*
  86  * Since the timer interrupts when the counter underflows, we need to
  87  * subtract 1 from counts_per_hz when loading the preload register.
  88  */
  89 static uint32_t counts_per_hz;
  90
  91 int     clockhandler(void *);
  92
  93 /*
  94  * becc_calibrate_delay:
  95  *
  96  *      Calibrate the delay loop.
  97  */
  98 void
  99 becc_calibrate_delay(void)
 100 {
 101
 102         /*
 103          * Just use hz=100 for now -- we'll adjust it, if necessary,
 104          * in cpu_initclocks().
 105          */
 106         counts_per_hz = COUNTS_PER_SEC / 100;
 107
 108         /* Stop both timers, clear interrupts. */
 109         BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TIF);
 110         BECC_CSR_WRITE(BECC_TSCRB, TSCRx_TIF);
 111
 112         /* Set the timer preload value. */
 113         BECC_CSR_WRITE(BECC_TPRA, counts_per_hz - 1);
 114
 115         /* Start the timer. */
 116         BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM);
 117 }
 118
 119 /*
 120  * cpu_initclocks:
 121  *
 122  *      Initialize the clock and get them going.
 123  */
 124 void
 125 cpu_initclocks(void)
 126 {
 127         u_int oldirqstate;
 128
 129 #if 0
 130         if (hz < 50 || COUNTS_PER_SEC % hz) {
 131                 printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
 132                 hz = 100;
 133         }
 134 #endif
 135
 136         /*
 137          * We only have one timer available; stathz and profhz are
 138          * always left as 0 (the upper-layer clock code deals with
 139          * this situation).
 140          */
 141         if (stathz != 0)
 142                 printf("Cannot get %d Hz statclock\n", stathz);
 143         stathz = 0;
 144
 145         if (profhz != 0)
 146                 printf("Cannot get %d Hz profclock\n", profhz);
 147         profhz = 0;
 148
 149         /* Report the clock frequency. */
 150         aprint_normal("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz);
 151
 152         oldirqstate = disable_interrupts(I32_bit);
 153
 154         /* Hook up the clock interrupt handler. */
 155         clock_ih = becc_intr_establish(ICU_TIMERA, IPL_CLOCK,
 156             clockhandler, NULL);
 157         if (clock_ih == NULL)
 158                 panic("cpu_initclocks: unable to register timer interrupt");
 159
 160         /* Set up the new clock parameters. */
 161
 162         /* Stop timer, clear interrupt */
 163         BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TIF);
 164
 165         counts_per_hz = COUNTS_PER_SEC / hz;
 166
 167         /* Set the timer preload value. */
 168         BECC_CSR_WRITE(BECC_TPRA, counts_per_hz - 1);
 169
 170         /* ...and start it in motion. */
 171         BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM);
 172
 173 #ifdef __HAVE_FAST_SOFTINTS
 174         /* register soft interrupt handler as well */
 175         becc_intr_establish(ICU_SOFT, IPL_SOFTCLOCK, becc_softint, NULL);
 176 #endif
 177
 178         restore_interrupts(oldirqstate);
 179
 180         tc_init(&becc_timecounter);
 181 }
 182
 183 /*
 184  * setstatclockrate:
 185  *
 186  *      Set the rate of the statistics clock.
 187  *
 188  *      We assume that hz is either stathz or profhz, and that neither
 189  *      will change after being set by cpu_initclocks().  We could
 190  *      recalculate the intervals here, but that would be a pain.
 191  */
 192 void
 193 setstatclockrate(int new_hz)
 194 {
 195
 196         /*
 197          * XXX Use TMR1?
 198          */
 199 }
 200
 201 static u_int
 202 becc_get_timecount(struct timecounter *tc)
 203 {
 204         uint32_t counter, base;
 205         u_int oldirqstate;
 206
 207         oldirqstate = disable_interrupts(I32_bit);
 208         counter = BECC_CSR_READ(BECC_TCVRA);
 209         base = becc_base;
 210         restore_interrupts(oldirqstate);
 211
 212         return base - counter;
 213 }
 214
 215 /*
 216  * delay:
 217  *
 218  *      Delay for at least N microseconds.
 219  */
 220 void
 221 delay(u_int n)
 222 {
 223         uint32_t cur, last, delta, usecs;
 224
 225         /*
 226          * This works by polling the timer and counting the
 227          * number of microseconds that go by.
 228          */
 229         last = BECC_CSR_READ(BECC_TCVRA);
 230         delta = usecs = 0;
 231
 232         while (n > usecs) {
 233                 cur = BECC_CSR_READ(BECC_TCVRA);
 234
 235                 /* Check to see if the timer has wrapped around. */
 236                 if (last < cur)
 237                         delta += (last + (counts_per_hz - cur));
 238                 else
 239                         delta += (last - cur);
 240
 241                 last = cur;
 242
 243                 if (delta >= COUNTS_PER_USEC) {
 244                         usecs += delta / COUNTS_PER_USEC;
 245                         delta %= COUNTS_PER_USEC;
 246                 }
 247         }
 248 }
 249
 250 /*
 251  * clockhandler:
 252  *
 253  *      Handle the hardclock interrupt.
 254  */
 255 int
 256 clockhandler(void *arg)
 257 {
 258         struct clockframe *frame = arg;
 259
 260         /* ACK the interrupt. */
 261         BECC_CSR_WRITE(BECC_TSCRA, TSCRx_TE | TSCRx_CM | TSCRx_TIF);
 262
 263         hardclock(frame);
 264
 265         atomic_add_32(&becc_base, counts_per_hz);
 266
 267         if (becc_hardclock_hook != NULL)
 268                 (*becc_hardclock_hook)();
 269
 270         return (1);
 271 }