sys/arch/arm/xscale/iopaaureg.h

   1 /*      $NetBSD: iopaaureg.h,v 1.2 2002/08/02 06:52:17 thorpej Exp $    */
   2
   3 /*
   4  * Copyright (c) 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _XSCALE_IOPAAUREG_H_
  39 #define _XSCALE_IOPAAUREG_H_
  40
  41 /*
  42  * The AAU can transfer a maximum of 16MB.
  43  *
  44  * XXX The DMA maps are > 32K if we allow the maximum number
  45  * XXX of DMA segments (16MB / 4K + 1) -- fix this bus_dma
  46  * XXX problem.
  47  */
  48 #define AAU_MAX_XFER    (16U * 1024 * 1024)
  49 #if 0
  50 #define AAU_MAX_SEGS    ((AAU_MAX_XFER / PAGE_SIZE) + 1)
  51 #else
  52 #define AAU_MAX_SEGS    1024
  53 #endif
  54
  55 /*
  56  * AAU I/O descriptor for operations with various numbers of inputs.
  57  * Note that all descriptors must be 8-word (32-byte) aligned.
  58  */
  59 struct aau_desc_4 {
  60         struct aau_desc_4 *d_next;      /* pointer to next (va) */
  61         uint32_t d_pa;                  /* our physical address */
  62
  63         /* Hardware portion -- must be 32-byte aligned. */
  64         uint32_t        d_nda;          /* next descriptor address */
  65         uint32_t        d_sar[4];       /* source address */
  66         uint32_t        d_dar;          /* destination address */
  67         uint32_t        d_bc;           /* byte count */
  68         uint32_t        d_dc;           /* descriptor control */
  69 } __attribute__((__packed__));
  70
  71 struct aau_desc_8 {
  72         struct aau_desc_8 *d_next;      /* pointer to next (va) */
  73         uint32_t d_pa;                  /* our physical address */
  74
  75         /* Hardware portion -- must be 32-byte aligned. */
  76         uint32_t        d_nda;          /* next descriptor address */
  77         uint32_t        d_sar[4];       /* source address */
  78         uint32_t        d_dar;          /* destination address */
  79         uint32_t        d_bc;           /* byte count */
  80         uint32_t        d_dc;           /* descriptor control */
  81         /* Mini Descriptor */
  82         uint32_t        d_sar5_8[4];    /* source address */
  83 } __attribute__((__packed__));
  84
  85 struct aau_desc_16 {
  86         struct aau_desc_16 *d_next;     /* pointer to next (va) */
  87         uint32_t d_pa;                  /* our physical address */
  88
  89         /* Hardware portion -- must be 32-byte aligned. */
  90         uint32_t        d_nda;          /* next descriptor address */
  91         uint32_t        d_sar[4];       /* source address */
  92         uint32_t        d_dar;          /* destination address */
  93         uint32_t        d_bc;           /* byte count */
  94         uint32_t        d_dc;           /* descriptor control */
  95         /* Mini Descriptor */
  96         uint32_t        d_sar5_8[4];    /* source address */
  97         /* Extended Descriptor 0 */
  98         uint32_t        d_edc0;         /* ext. descriptor control */
  99         uint32_t        d_sar9_16[8];   /* source address */
 100 } __attribute__((__packed__));
 101
 102 struct aau_desc_32 {
 103         struct aau_desc_32 *d_next;     /* pointer to next (va) */
 104         uint32_t d_pa;                  /* our physical address */
 105
 106         /* Hardware portion -- must be 32-byte aligned. */
 107         uint32_t        d_nda;          /* next descriptor address */
 108         uint32_t        d_sar[4];       /* source address */
 109         uint32_t        d_dar;          /* destination address */
 110         uint32_t        d_bc;           /* byte count */
 111         uint32_t        d_dc;           /* descriptor control */
 112         /* Mini Descriptor */
 113         uint32_t        d_sar5_8[4];    /* source address */
 114         /* Extended Descriptor 0 */
 115         uint32_t        d_edc0;         /* ext. descriptor control */
 116         uint32_t        d_sar9_16[8];   /* source address */
 117         /* Extended Descriptor 1 */
 118         uint32_t        d_edc1;         /* ext. descriptor control */
 119         uint32_t        d_sar17_24[8];  /* source address */
 120         /* Extended Descriptor 2 */
 121         uint32_t        d_edc2;         /* ext. descriptor control */
 122         uint32_t        d_sar25_32[8];  /* source address */
 123 } __attribute__((__packed__));
 124
 125 #define AAU_DESC_SIZE(ninputs)                                          \
 126         ((ninputs > 16) ? sizeof(struct aau_desc_32) :                  \
 127          (ninputs > 8) ? sizeof(struct aau_desc_16) :                   \
 128          (ninputs > 4) ? sizeof(struct aau_desc_8) :                    \
 129          sizeof(struct aau_desc_4))
 130
 131 #define SYNC_DESC_4_OFFSET      offsetof(struct aau_desc_4, d_nda)
 132 #define SYNC_DESC_4_SIZE        (sizeof(struct aau_desc_4) - SYNC_DESC_4_OFFSET)
 133
 134 #define SYNC_DESC(d, size)                                              \
 135         cpu_dcache_wbinv_range(((vaddr_t)(d)) + SYNC_DESC_4_OFFSET, (size))
 136
 137 /* Descriptor control */
 138 #define AAU_DC_IE               (1U << 0)       /* interrupt enable */
 139 #define AAU_DC_B1_CC(x)         ((x) << 1)      /* block command/control */
 140 #define AAU_DC_B2_CC(x)         ((x) << 4)
 141 #define AAU_DC_B3_CC(x)         ((x) << 7)
 142 #define AAU_DC_B4_CC(x)         ((x) << 10)
 143 #define AAU_DC_B5_CC(x)         ((x) << 13)
 144 #define AAU_DC_B6_CC(x)         ((x) << 16)
 145 #define AAU_DC_B7_CC(x)         ((x) << 19)
 146 #define AAU_DC_B8_CC(x)         ((x) << 22)
 147 #define AAU_DC_SBCI_5_8         (1U << 25)      /* SAR5-SAR8 valid */
 148 #define AAU_DC_SBCI_5_16        (2U << 25)      /* SAR5-SAR16 valid */
 149 #define AAU_DC_SBCI_5_32        (3U << 25)      /* SAR5-SAR32 valid */
 150 #define AAU_DC_TC               (1U << 28)      /* transfer complete */
 151 #define AAU_DC_PERR             (1U << 29)      /* parity check error */
 152 #define AAU_DC_PENB             (1U << 30)      /* parity check enable */
 153 #define AAU_DC_DWE              (1U << 31)      /* destination write enable */
 154
 155 #define AAU_DC_CC_NULL          0               /* null command */
 156 #define AAU_DC_CC_XOR           1U              /* XOR command */
 157 #define AAU_DC_CC_FILL          2U              /* fill command */
 158 #define AAU_DC_CC_DIRECT_FILL   7U              /* direct fill (copy) */
 159
 160 /* Extended descriptor control */
 161 #define AAU_EDC_B1_CC(x)        ((x) << 1)      /* block command/control */
 162 #define AAU_EDC_B2_CC(x)        ((x) << 4)      /* block command/control */
 163 #define AAU_EDC_B3_CC(x)        ((x) << 7)      /* block command/control */
 164 #define AAU_EDC_B4_CC(x)        ((x) << 10)     /* block command/control */
 165 #define AAU_EDC_B5_CC(x)        ((x) << 13)     /* block command/control */
 166 #define AAU_EDC_B6_CC(x)        ((x) << 16)     /* block command/control */
 167 #define AAU_EDC_B7_CC(x)        ((x) << 19)     /* block command/control */
 168 #define AAU_EDC_B8_CC(x)        ((x) << 22)     /* block command/control */
 169
 170 /* Hardware registers */
 171 #define AAU_ACR         0x00            /* accelerator control */
 172 #define AAU_ASR         0x04            /* accelerator status */
 173 #define AAU_ADAR        0x08            /* descriptor address */
 174 #define AAU_ANDAR       0x0c            /* next descriptor address */
 175 #define AAU_DAR         0x20            /* destination address */
 176 #define AAU_ABCR        0x24            /* byte count */
 177 #define AAU_ADCR        0x28            /* descriptor control */
 178 /* i80321 only */
 179 #define AAU_EDCR0       0x3c            /* extended descriptor control 0 */
 180 #define AAU_EDCR1       0x60            /* extended descriptor control 1 */
 181 #define AAU_EDCR2       0x84            /* extended descriptor control 2 */
 182
 183 #define AAU_ACR_AAE     (1U << 0)       /* accelerator enable */
 184 #define AAU_ACR_CR      (1U << 1)       /* chain resume */
 185 #define AAU_ACR_512     (1U << 2)       /* 512-byte buffer enable */
 186
 187 #define AAU_ASR_MA      (1U << 5)       /* master abort */
 188 #define AAU_ASR_ECIF    (1U << 8)       /* end of chain interrupt */
 189 #define AAU_ASR_ETIF    (1U << 9)       /* end of transfer interrupt */
 190 #define AAU_ASR_AAF     (1U << 10)      /* acellerator active */
 191
 192 #define AAU_ABCR_MASK   0x00ffffff      /* 24-bit count */
 193
 194 #endif /* _XSCALE_IOPAAUREG_H_ */