sys/arch/arm/xscale/iopi2c.c

   1 /*      $NetBSD: iopi2c.c,v 1.4 2006/06/26 18:21:39 drochner Exp $      */
   2
   3 /*
   4  * Copyright (c) 2003 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * Intel i80321 I/O Processor I2C Controller Unit support.
  40  */
  41
  42 #include <sys/cdefs.h>
  43 __KERNEL_RCSID(0, "$NetBSD: iopi2c.c,v 1.4 2006/06/26 18:21:39 drochner Exp $");
  44
  45 #include <sys/param.h>
  46 #include <sys/mutex.h>
  47 #include <sys/systm.h>
  48 #include <sys/device.h>
  49 #include <sys/kernel.h>
  50
  51 #include <machine/bus.h>
  52 #include <machine/intr.h>
  53
  54 #include <dev/i2c/i2cvar.h>
  55
  56 #include <arm/xscale/iopi2creg.h>
  57 #include <arm/xscale/iopi2cvar.h>
  58
  59 static int iopiic_acquire_bus(void *, int);
  60 static void iopiic_release_bus(void *, int);
  61
  62 static int iopiic_send_start(void *, int);
  63 static int iopiic_send_stop(void *, int);
  64 static int iopiic_initiate_xfer(void *, uint16_t, int);
  65 static int iopiic_read_byte(void *, uint8_t *, int);
  66 static int iopiic_write_byte(void *, uint8_t, int);
  67
  68 void
  69 iopiic_attach(struct iopiic_softc *sc)
  70 {
  71         struct i2cbus_attach_args iba;
  72
  73         sc->sc_i2c.ic_cookie = sc;
  74         sc->sc_i2c.ic_acquire_bus = iopiic_acquire_bus;
  75         sc->sc_i2c.ic_release_bus = iopiic_release_bus;
  76         sc->sc_i2c.ic_send_start = iopiic_send_start;
  77         sc->sc_i2c.ic_send_stop = iopiic_send_stop;
  78         sc->sc_i2c.ic_initiate_xfer = iopiic_initiate_xfer;
  79         sc->sc_i2c.ic_read_byte = iopiic_read_byte;
  80         sc->sc_i2c.ic_write_byte = iopiic_write_byte;
  81
  82         iba.iba_tag = &sc->sc_i2c;
  83         (void) config_found_ia(&sc->sc_dev, "i2cbus", &iba, iicbus_print);
  84 }
  85
  86 static int
  87 iopiic_acquire_bus(void *cookie, int flags)
  88 {
  89         struct iopiic_softc *sc = cookie;
  90
  91         /* XXX What should we do for the polling case? */
  92         if (flags & I2C_F_POLL)
  93                 return (0);
  94
  95         mutex_enter(&sc->sc_buslock);
  96         return (0);
  97 }
  98
  99 static void
 100 iopiic_release_bus(void *cookie, int flags)
 101 {
 102         struct iopiic_softc *sc = cookie;
 103
 104         /* XXX See above. */
 105         if (flags & I2C_F_POLL)
 106                 return;
 107
 108         mutex_exit(&sc->sc_buslock);
 109 }
 110
 111 #define IOPIIC_TIMEOUT          100     /* protocol timeout, in uSecs */
 112
 113 static int
 114 iopiic_wait(struct iopiic_softc *sc, int bit, int flags)
 115 {
 116         uint32_t isr;
 117         int timeout, error=0;
 118
 119         /* XXX We never sleep, we always poll.  Fix me. */
 120
 121         /*
 122          * For some reason, we seem to run into problems if we poll
 123          * the ISR while the transfer is in progress--at least on the
 124          * i80312.  The condition that we're looking for never seems
 125          * to appear on a read, and it's not clear why; perhaps reads
 126          * of the I2C register file interfere with its proper operation?
 127          * For now, just delay for a while up front.
 128          *
 129          * We _really_ need this to be interrupt-driven, but a problem
 130          * with that is that the i80312 has no way to mask interrupts...
 131          * So we need to deal with that.  For DMA and AAU, too, for that
 132          * matter.
 133          * Note that delay(100) doesn't quite work on the npwr w/ m41t00.
 134          */
 135         delay(110);
 136         for (timeout = IOPIIC_TIMEOUT; timeout != 0; timeout--) {
 137                 isr = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_ISR);
 138                 if (isr & (bit | IIC_ISR_BED))
 139                         break;
 140                 delay(1);
 141         }
 142
 143         if (isr & (IIC_ISR_BED | (bit & IIC_ISR_ALD)))
 144                 error = EIO;
 145         else if (isr & (bit & ~IIC_ISR_ALD))
 146                 error = 0;
 147         else
 148                 error = ETIMEDOUT;
 149
 150         if (error)
 151                 printf("%s: iopiic_wait, (%08x) error %d: ISR = 0x%08x\n",
 152                     sc->sc_dev.dv_xname, bit, error, isr);
 153
 154         /*
 155          * The IIC_ISR is Read/Clear apart from the bottom 4 bits, which are
 156          * read-only. So simply write back our copy of the ISR to clear any
 157          * latched status.
 158          */
 159         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ISR, isr);
 160
 161         return (error);
 162 }
 163
 164 static int
 165 iopiic_send_start(void *cookie, int flags)
 166 {
 167         struct iopiic_softc *sc = cookie;
 168
 169         /*
 170          * This may only work in conjunction with a data transfer;
 171          * we might need to un-export the "start" primitive.
 172          */
 173         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
 174             sc->sc_icr | IIC_ICR_START);
 175         delay(IOPIIC_TIMEOUT);
 176
 177         return (0);
 178 }
 179
 180 static int
 181 iopiic_send_stop(void *cookie, int flags)
 182 {
 183         struct iopiic_softc *sc = cookie;
 184
 185         /*
 186          * The STOP bit is only used in conjunction with
 187          * a data transfer, so we need to use MA in this
 188          * case.
 189          *
 190          * Consider adding an I2C_F_STOP so we can
 191          * do a read-with-STOP and write-with-STOP.
 192          */
 193         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
 194             sc->sc_icr | IIC_ICR_MA);
 195         delay(IOPIIC_TIMEOUT);
 196
 197         return (0);
 198 }
 199
 200 static int
 201 iopiic_initiate_xfer(void *cookie, uint16_t addr, int flags)
 202 {
 203         struct iopiic_softc *sc = cookie;
 204         int error, rd_req = (flags & I2C_F_READ) != 0;
 205         uint32_t idbr;
 206
 207         /* We only support 7-bit addressing. */
 208         if ((addr & 0x78) == 0x78)
 209                 return (EINVAL);
 210
 211         idbr = (addr << 1) | (rd_req ? 1 : 0);
 212         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, idbr);
 213         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
 214             sc->sc_icr | IIC_ICR_START | IIC_ICR_TB);
 215
 216         error = iopiic_wait(sc, IIC_ISR_ITE, flags);
 217 #if 0
 218         if (error)
 219                 printf("%s: failed to initiate %s xfer\n", sc->sc_dev.dv_xname,
 220                     rd_req ? "read" : "write");
 221 #endif
 222         return (error);
 223 }
 224
 225 static int
 226 iopiic_read_byte(void *cookie, uint8_t *bytep, int flags)
 227 {
 228         struct iopiic_softc *sc = cookie;
 229         int error, last_byte = (flags & I2C_F_LAST) != 0,
 230             send_stop = (flags & I2C_F_STOP) != 0;
 231
 232         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
 233             sc->sc_icr | IIC_ICR_TB | (last_byte ? IIC_ICR_NACK : 0) |
 234             (send_stop ? IIC_ICR_STOP : 0));
 235         if ((error = iopiic_wait(sc, IIC_ISR_IRF | IIC_ISR_ALD, flags)) == 0)
 236                 *bytep = bus_space_read_4(sc->sc_st, sc->sc_sh, IIC_IDBR);
 237 #if 0
 238         if (error)
 239                 printf("%s: read byte failed\n", sc->sc_dev.dv_xname);
 240 #endif
 241
 242         return (error);
 243 }
 244
 245 static int
 246 iopiic_write_byte(void *cookie, uint8_t byte, int flags)
 247 {
 248         struct iopiic_softc *sc = cookie;
 249         int error, send_stop = (flags & I2C_F_STOP) != 0;
 250
 251         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_IDBR, byte);
 252         bus_space_write_4(sc->sc_st, sc->sc_sh, IIC_ICR,
 253             sc->sc_icr | IIC_ICR_TB | (send_stop ? IIC_ICR_STOP : 0));
 254         error = iopiic_wait(sc, IIC_ISR_ITE | IIC_ISR_ALD, flags);
 255
 256 #if 0
 257         if (error)
 258                 printf("%s: write byte failed\n", sc->sc_dev.dv_xname);
 259 #endif
 260
 261         return (error);
 262 }