sys/arch/arm/xscale/iopi2creg.h

   1 /*      $NetBSD: iopi2creg.h,v 1.1.4.3 2004/09/21 13:13:42 skrll Exp $  */
   2
   3 /*
   4  * Copyright (c) 2003 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ARM_XSCALE_IOPIICREG_H_
  39 #define _ARM_XSCALE_IOPIICREG_H_
  40
  41 #define IIC_ICR         0x00    /* i2c control register */
  42 #define IIC_ISR         0x04    /* i2c status register */
  43 #define IIC_ISAR        0x08    /* i2c slave address register */
  44 #define IIC_IDBR        0x0c    /* i2c data buffer register */
  45 #define IIC_ICCR        0x10    /* i2c clock control register (i80312 only) */
  46 #define IIC_IBMR        0x14    /* i2c bus monitor register */
  47
  48 #define IIC_ICR_FM              (1U << 15)      /* fast mode (i80321 only) */
  49 #define IIC_ICR_RESET           (1U << 14)      /* i2c unit reset */
  50 #define IIC_ICR_SADIE           (1U << 13)      /* slave addr det int en */
  51 #define IIC_ICR_ALDIE           (1U << 12)      /* arb loss det int en */
  52 #define IIC_ICR_SSDIE           (1U << 11)      /* slave stop det in en */
  53 #define IIC_ICR_BEIE            (1U << 10)      /* bus error int en */
  54 #define IIC_ICR_IRFIE           (1U << 9)       /* IDBR Rx full int en */
  55 #define IIC_ICR_ITEIE           (1U << 8)       /* IDBR Tx empty int en */
  56 #define IIC_ICR_GCD             (1U << 7)       /* general call disable */
  57 #define IIC_ICR_UE              (1U << 6)       /* i2c unit enable */
  58 #define IIC_ICR_SCLE            (1U << 5)       /* SCL master enable */
  59 #define IIC_ICR_MA              (1U << 4)       /* abort as master */
  60 #define IIC_ICR_TB              (1U << 3)       /* transfer byte */
  61 #define IIC_ICR_NACK            (1U << 2)       /* 0=ACK, 1=NACK */
  62 #define IIC_ICR_STOP            (1U << 1)       /* initiate STOP condition */
  63 #define IIC_ICR_START           (1U << 0)       /* initiate START condition */
  64
  65 #define IIC_ISR_BED             (1U << 10)      /* bus error detected */
  66 #define IIC_ISR_SAD             (1U << 9)       /* slave address detected */
  67 #define IIC_ISR_GCAD            (1U << 8)       /* general call addr detected */
  68 #define IIC_ISR_IRF             (1U << 7)       /* IDBR Rx full */
  69 #define IIC_ISR_ITE             (1U << 6)       /* IDBR Tx empty */
  70 #define IIC_ISR_ALD             (1U << 5)       /* arb loss detected */
  71 #define IIC_ISR_SSD             (1U << 4)       /* slave STOP detected */
  72 #define IIC_ISR_IBB             (1U << 3)       /* i2c bus busy */
  73 #define IIC_ISR_UB              (1U << 2)       /* unit busy */
  74 #define IIC_ISR_NACK            (1U << 1)       /* NACK received */
  75 #define IIC_ISR_RW              (1U << 0)       /* 0=mt/sr, 1=mr/st */
  76
  77 #endif /* _ARM_XSCALE_IOPIICREG_H_  */