sys/arch/arm/xscale/ixp425_qmgr.h

   1 /*      $NetBSD$        */
   2
   3 /*-
   4  * Copyright (c) 2006 Sam Leffler, Errno Consulting
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  15  *    redistribution must be conditioned upon including a substantially
  16  *    similar Disclaimer requirement for further binary redistribution.
  17  *
  18  * NO WARRANTY
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  22  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  23  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  24  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  27  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  29  * THE POSSIBILITY OF SUCH DAMAGES.
  30  *
  31  * $FreeBSD: src/sys/arm/xscale/ixp425/ixp425_qmgr.h,v 1.1 2006/11/19 23:55:23 sam Exp $
  32  */
  33
  34 /*-
  35  * Copyright (c) 2001-2005, Intel Corporation.
  36  * All rights reserved.
  37  *
  38  * Redistribution and use in source and binary forms, with or without
  39  * modification, are permitted provided that the following conditions
  40  * are met:
  41  * 1. Redistributions of source code must retain the above copyright
  42  *    notice, this list of conditions and the following disclaimer.
  43  * 2. Redistributions in binary form must reproduce the above copyright
  44  *    notice, this list of conditions and the following disclaimer in the
  45  *    documentation and/or other materials provided with the distribution.
  46  * 3. Neither the name of the Intel Corporation nor the names of its contributors
  47  *    may be used to endorse or promote products derived from this software
  48  *    without specific prior written permission.
  49  *
  50  *
  51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
  52  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  53  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  54  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  55  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  56  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  57  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  58  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  59  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  60  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  61  * SUCH DAMAGE.
  62 */
  63
  64 #ifndef ARM_XSCALE_IXP425_QMGR_H
  65 #define ARM_XSCALE_IXP425_QMGR_H
  66
  67 #define IX_QMGR_MAX_NUM_QUEUES          64
  68 #define IX_QMGR_MIN_QUEUPP_QID          32
  69
  70 #define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16
  71
  72 /* Total size of SRAM */
  73 #define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000
  74
  75 #define IX_QMGR_Q_PRIORITY_0            0
  76 #define IX_QMGR_Q_PRIORITY_1            1
  77 #define IX_QMGR_Q_PRIORITY_2            2
  78 #define IX_QMGR_NUM_PRIORITY_LEVELS     3       /* number of priority levels */
  79
  80 #define IX_QMGR_Q_STATUS_E_BIT_MASK     0x1     /* Empty */
  81 #define IX_QMGR_Q_STATUS_NE_BIT_MASK    0x2     /* Nearly Empty */
  82 #define IX_QMGR_Q_STATUS_NF_BIT_MASK    0x4     /* Nearly Full */
  83 #define IX_QMGR_Q_STATUS_F_BIT_MASK     0x8     /* Full */
  84 #define IX_QMGR_Q_STATUS_UF_BIT_MASK    0x10    /* Underflow */
  85 #define IX_QMGR_Q_STATUS_OF_BIT_MASK    0x20    /* Overflow */
  86
  87 #define IX_QMGR_Q_SOURCE_ID_E           0 /* Q Empty after last read */
  88 #define IX_QMGR_Q_SOURCE_ID_NE          1 /* Q Nearly Empty after last read */
  89 #define IX_QMGR_Q_SOURCE_ID_NF          2 /* Q Nearly Full after last write */
  90 #define IX_QMGR_Q_SOURCE_ID_F           3 /* Q Full after last write */
  91 #define IX_QMGR_Q_SOURCE_ID_NOT_E       4 /* Q !Empty after last write */
  92 #define IX_QMGR_Q_SOURCE_ID_NOT_NE      5 /* Q !Nearly Empty after last write */
  93 #define IX_QMGR_Q_SOURCE_ID_NOT_NF      6 /* Q !Nearly Full after last read */
  94 #define IX_QMGR_Q_SOURCE_ID_NOT_F       7 /* Q !Full after last read */
  95
  96 #define IX_QMGR_UNDERFLOW_BIT_OFFSET    0x0     /* underflow bit mask */
  97 #define IX_QMGR_OVERFLOW_BIT_OFFSET     0x1     /* overflow bit mask */
  98
  99 #define IX_QMGR_QUEACC0_OFFSET          0x0000  /* q 0 access register */
 100 #define IX_QMGR_QUEACC_SIZE             0x4/*words*/
 101
 102 #define IX_QMGR_QUELOWSTAT0_OFFSET      0x400   /* Q status, q's 0-7 */
 103 #define IX_QMGR_QUELOWSTAT1_OFFSET      0x404   /* Q status, q's 8-15 */
 104 #define IX_QMGR_QUELOWSTAT2_OFFSET      0x408   /* Q status, q's 16-23 */
 105 #define IX_QMGR_QUELOWSTAT3_OFFSET      0x40c   /* Q status, q's 24-31 */
 106
 107 /* Queue status register Q status bits mask */
 108 #define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
 109 /* Size of queue 0-31 status register */
 110 #define IX_QMGR_QUELOWSTAT_SIZE     0x4 /*words*/
 111 #define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 8   /* # status/word */
 112
 113 #define IX_QMGR_QUEUOSTAT0_OFFSET       0x410   /* Q UF/OF status, q's 0-15 */
 114 #define IX_QMGR_QUEUOSTAT1_OFFSET       0x414   /* Q UF/OF status, q's 16-31 */
 115
 116 #define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 16   /* # UF/OF status/word */
 117
 118 #define IX_QMGR_QUEUPPSTAT0_OFFSET      0x418   /* NE status, q's 32-63 */
 119 #define IX_QMGR_QUEUPPSTAT1_OFFSET      0x41c   /* F status, q's 32-63 */
 120
 121 #define IX_QMGR_INT0SRCSELREG0_OFFSET   0x420   /* INT src select, q's 0-7 */
 122 #define IX_QMGR_INT0SRCSELREG1_OFFSET   0x424   /* INT src select, q's 8-15 */
 123 #define IX_QMGR_INT0SRCSELREG2_OFFSET   0x428   /* INT src select, q's 16-23 */
 124 #define IX_QMGR_INT0SRCSELREG3_OFFSET   0x42c   /* INT src select, q's 24-31 */
 125
 126 #define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 8       /* # INT src select/word */
 127
 128 #define IX_QMGR_QUEIEREG0_OFFSET        0x430   /* INT enable, q's 0-31 */
 129 #define IX_QMGR_QUEIEREG1_OFFSET        0x434   /* INT enable, q's 32-63 */
 130 #define IX_QMGR_QINTREG0_OFFSET         0x438   /* INT status, q's 0-31 */
 131 #define IX_QMGR_QINTREG1_OFFSET         0x43c   /* INT status, q's 32-63 */
 132
 133 #define IX_QMGR_QUECONFIG_BASE_OFFSET   0x2000  /* Q config register, q 0 */
 134
 135 #define IX_QMGR_QUECONFIG_SIZE          0x100   /* total size of Q config regs*/
 136
 137 #define IX_QMGR_QUEBUFFER_SPACE_OFFSET  0x2100  /* start of SRAM */
 138
 139 /* Total bits in a word */
 140 #define BITS_PER_WORD 32
 141
 142 /* Size of queue buffer space */
 143 #define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
 144
 145 /*
 146  * This macro will return the address of the access register for the
 147  * queue  specified by qId
 148  */
 149 #define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
 150         (((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\
 151          + IX_QMGR_QUEACC0_OFFSET)
 152
 153 /*
 154  * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
 155  * sticky interrupt register.
 156  */
 157 #define IX_QMGR_INT0SRCSELREG0_BIT3 3
 158
 159 /*
 160  * These defines are the bit offsets of the various fields of
 161  * the queue configuration register.
 162  */
 163 #if 0
 164 #define IX_QMGR_Q_CONFIG_WRPTR_OFFSET       0x00
 165 #define IX_QMGR_Q_CONFIG_RDPTR_OFFSET       0x07
 166 #define IX_QMGR_Q_CONFIG_BADDR_OFFSET       0x0E
 167 #define IX_QMGR_Q_CONFIG_ESIZE_OFFSET       0x16
 168 #define IX_QMGR_Q_CONFIG_BSIZE_OFFSET       0x18
 169 #define IX_QMGR_Q_CONFIG_NE_OFFSET          0x1A
 170 #define IX_QMGR_Q_CONFIG_NF_OFFSET          0x1D
 171
 172 #define IX_QMGR_NE_NF_CLEAR_MASK            0x03FFFFFF
 173 #define IX_QMGR_NE_MASK                     0x7
 174 #define IX_QMGR_NF_MASK                     0x7
 175 #define IX_QMGR_SIZE_MASK                   0x3
 176 #define IX_QMGR_ENTRY_SIZE_MASK             0x3
 177 #define IX_QMGR_BADDR_MASK                  0x003FC000
 178 #define IX_QMGR_RDPTR_MASK                  0x7F
 179 #define IX_QMGR_WRPTR_MASK                  0x7F
 180 #define IX_QMGR_RDWRPTR_MASK                0x00003FFF
 181 #else
 182 #define IX_QMGR_Q_CONFIG_WRPTR_OFFSET       0
 183 #define IX_QMGR_WRPTR_MASK                  0x7F
 184 #define IX_QMGR_Q_CONFIG_RDPTR_OFFSET       7
 185 #define IX_QMGR_RDPTR_MASK                  0x7F
 186 #define IX_QMGR_Q_CONFIG_BADDR_OFFSET       14
 187 #define IX_QMGR_BADDR_MASK                  0x3FC000    /* XXX not used */
 188 #define IX_QMGR_Q_CONFIG_ESIZE_OFFSET       22
 189 #define IX_QMGR_ENTRY_SIZE_MASK             0x3
 190 #define IX_QMGR_Q_CONFIG_BSIZE_OFFSET       24
 191 #define IX_QMGR_SIZE_MASK                   0x3
 192 #define IX_QMGR_Q_CONFIG_NE_OFFSET          26
 193 #define IX_QMGR_NE_MASK                     0x7
 194 #define IX_QMGR_Q_CONFIG_NF_OFFSET          29
 195 #define IX_QMGR_NF_MASK                     0x7
 196
 197 #define IX_QMGR_RDWRPTR_MASK                0x00003FFF
 198 #define IX_QMGR_NE_NF_CLEAR_MASK            0x03FFFFFF
 199 #endif
 200
 201 #define IX_QMGR_BASE_ADDR_16_WORD_ALIGN     64
 202 #define IX_QMGR_BASE_ADDR_16_WORD_SHIFT     6
 203
 204 #define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000
 205
 206 /* Base address of AQM SRAM */
 207 #define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \
 208 ((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE))
 209
 210 /* Min buffer size used for generating buffer size in QUECONFIG */
 211 #define IX_QMGR_MIN_BUFFER_SIZE 16
 212
 213 /* Reset values of QMgr hardware registers */
 214 #define IX_QMGR_QUELOWSTAT_RESET_VALUE    0x33333333
 215 #define IX_QMGR_QUEUOSTAT_RESET_VALUE     0x00000000
 216 #define IX_QMGR_QUEUPPSTAT0_RESET_VALUE   0xFFFFFFFF
 217 #define IX_QMGR_QUEUPPSTAT1_RESET_VALUE   0x00000000
 218 #define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000
 219 #define IX_QMGR_QUEIEREG_RESET_VALUE      0x00000000
 220 #define IX_QMGR_QINTREG_RESET_VALUE       0xFFFFFFFF
 221 #define IX_QMGR_QUECONFIG_RESET_VALUE     0x00000000
 222
 223 #define IX_QMGR_QUELOWSTAT_BITS_PER_Q \
 224         (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)
 225
 226 #define IX_QMGR_QUELOWSTAT_QID_MASK 0x7
 227 #define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\
 228         (((qId) * sizeof(uint32_t)) + IX_QMGR_QUECONFIG_BASE_OFFSET)
 229
 230 #define IX_QMGR_ENTRY1_OFFSET 0
 231 #define IX_QMGR_ENTRY2_OFFSET 1
 232 #define IX_QMGR_ENTRY4_OFFSET 3
 233
 234 #ifdef __NetBSD__
 235 void    *ixpqmgr_init(bus_space_tag_t);
 236 #endif
 237
 238 int     ixpqmgr_qconfig(int qId, int qSizeInWords, int ne, int nf, int srcSel,
 239             void (*cb)(int, void *), void *cbarg);
 240 int     ixpqmgr_qwrite(int qId, uint32_t entry);
 241 int     ixpqmgr_qread(int qId, uint32_t *entry);
 242 int     ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p);
 243 uint32_t ixpqmgr_getqstatus(int qId);
 244 uint32_t ixpqmgr_getqconfig(int qId);
 245 void    ixpqmgr_notify_enable(int qId, int srcSel);
 246 void    ixpqmgr_notify_disable(int qId);
 247 void    ixpqmgr_dump(void);
 248
 249 #endif /* ARM_XSCALE_IXP425_QMGR_H */