sys/arch/arm/xscale/ixp425reg.h

   1 /*      $NetBSD: ixp425reg.h,v 1.20 2006/12/10 10:01:49 scw Exp $ */
   2 /*
   3  * Copyright (c) 2003
   4  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 #ifndef _IXP425REG_H_
  30 #define _IXP425REG_H_
  31
  32 /*
  33  * Physical memory map for the Intel IXP425
  34  */
  35 /*
  36  * CC00 00FF ---------------------------
  37  *           SDRAM Configuration Registers
  38  * CC00 0000 ---------------------------
  39  *
  40  * C800 BFFF ---------------------------
  41  *           System and Peripheral Registers
  42  * C800 0000 ---------------------------
  43  *           Expansion Bus Configuration Registers
  44  * C400 0000 ---------------------------
  45  *           PCI Configuration and Status Registers
  46  * C000 0000 ---------------------------
  47  *
  48  * 6400 0000 ---------------------------
  49  *           Queue manager
  50  * 6000 0000 ---------------------------
  51  *           Expansion Bus Data
  52  * 5000 0000 ---------------------------
  53  *           PCI Data
  54  * 4800 0000 ---------------------------
  55  *
  56  * 4000 0000 ---------------------------
  57  *           SDRAM
  58  * 1000 0000 ---------------------------
  59  */
  60
  61 /*
  62  * Virtual memory map for the Intel IXP425 integrated devices
  63  */
  64 /*
  65  * FFFF FFFF ---------------------------
  66  *
  67  * FC00 0000 ---------------------------
  68  *           PCI Data (memory space)
  69  * F800 0000 ---------------------------
  70  *
  71  * F020 1000 ---------------------------
  72  *           SDRAM Controller
  73  * F020 0000 ---------------------------
  74  *
  75  * F001 2000 ---------------------------
  76  *           PCI Configuration and Status Registers
  77  * F001 1000 ---------------------------
  78  *           Expansion bus Configuration Registers
  79  * F001 0000 ---------------------------
  80  *           System and Peripheral Registers
  81  *            VA F000 0000 = PA C800 0000 (SIZE 0x10000)
  82  * F000 0000 ---------------------------
  83  *
  84  * 0000 0000 ---------------------------
  85  *
  86  */
  87
  88 /* Physical/Virtual address for I/O space */
  89
  90 #define IXP425_IO_VBASE         0xf0000000UL
  91 #define IXP425_IO_HWBASE        0xc8000000UL
  92 #define IXP425_IO_SIZE          0x00010000UL
  93
  94 /* Offset */
  95
  96 #define IXP425_UART0_OFFSET     0x00000000UL
  97 #define IXP425_UART1_OFFSET     0x00001000UL
  98 #define IXP425_PMC_OFFSET       0x00002000UL
  99 #define IXP425_INTR_OFFSET      0x00003000UL
 100 #define IXP425_GPIO_OFFSET      0x00004000UL
 101 #define IXP425_TIMER_OFFSET     0x00005000UL
 102 #define IXP425_NPE_A_OFFSET     0x00006000UL    /* Not User Programmable */
 103 #define IXP425_NPE_B_OFFSET     0x00007000UL    /* Not User Programmable */
 104 #define IXP425_NPE_C_OFFSET     0x00008000UL    /* Not User Programmable */
 105 #define IXP425_MAC_A_OFFSET     0x00009000UL
 106 #define IXP425_MAC_B_OFFSET     0x0000a000UL
 107 #define IXP425_USB_OFFSET       0x0000b000UL
 108
 109 #define IXP425_REG_SIZE         0x1000
 110
 111 /*
 112  * UART
 113  *      UART0 0xc8000000
 114  *      UART1 0xc8001000
 115  *
 116  */
 117 /* I/O space */
 118 #define IXP425_UART0_HWBASE     (IXP425_IO_HWBASE + IXP425_UART0_OFFSET)
 119 #define IXP425_UART1_HWBASE     (IXP425_IO_HWBASE + IXP425_UART1_OFFSET)
 120
 121 #define IXP425_UART0_VBASE      (IXP425_IO_VBASE + IXP425_UART0_OFFSET)
 122                                                 /* 0xf0000000 */
 123 #define IXP425_UART1_VBASE      (IXP425_IO_VBASE + IXP425_UART1_OFFSET)
 124                                                 /* 0xf0001000 */
 125
 126 #define IXP425_UART_FREQ        14745600
 127
 128 /*#define       IXP4XX_COM_NPORTS       8*/
 129
 130 /*
 131  * Timers
 132  *
 133  */
 134 #define IXP425_TIMER_HWBASE     (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET)
 135 #define IXP425_TIMER_VBASE      (IXP425_IO_VBASE + IXP425_TIMER_OFFSET)
 136
 137 #define IXP425_OST_TS           0x0000
 138 #define IXP425_OST_TIM0         0x0004
 139 #define IXP425_OST_TIM1         0x000C
 140
 141 #define IXP425_OST_TIM0_RELOAD  0x0008
 142 #define IXP425_OST_TIM1_RELOAD  0x0010
 143 #define TIMERRELOAD_MASK        0xFFFFFFFC
 144 #define OST_ONESHOT_EN          (1U << 1)
 145 #define OST_TIMER_EN            (1U << 0)
 146
 147 #define IXP425_OST_STATUS       0x0020
 148 #define OST_WARM_RESET          (1U << 4)
 149 #define OST_WDOG_INT            (1U << 3)
 150 #define OST_TS_INT              (1U << 2)
 151 #define OST_TIM1_INT            (1U << 1)
 152 #define OST_TIM0_INT            (1U << 0)
 153
 154 #define IXP425_OST_WDOG_HWBASE  (IXP425_TIMER_HWBASE + 0x14)
 155 #define IXP425_OST_WDOG_VBASE   (IXP425_TIMER_VBASE + 0x14)
 156 #define IXP425_OST_WDOG_SIZE    0x0c
 157 #define IXP425_OST_WDOG         0x0000
 158 #define IXP425_OST_WDOG_ENAB    0x0004
 159 #define IXP425_OST_WDOG_KEY     0x0008
 160 #define OST_WDOG_KEY_MAJICK     0x482e
 161 #define OST_WDOG_ENAB_RST_ENA   (1u << 0)
 162 #define OST_WDOG_ENAB_INT_ENA   (1u << 1)
 163 #define OST_WDOG_ENAB_CNT_ENA   (1u << 2)
 164
 165 /*
 166  * Interrupt Controller Unit.
 167  *  PA 0xc8003000
 168  */
 169
 170 #define IXP425_IRQ_HWBASE       IXP425_IO_HWBASE + IXP425_INTR_OFFSET
 171 #define IXP425_IRQ_VBASE        IXP425_IO_VBASE  + IXP425_INTR_OFFSET
 172                                                 /* 0xf0003000 */
 173 #define IXP425_IRQ_SIZE         0x00000020UL
 174
 175 #define IXP425_INT_STATUS       (IXP425_IRQ_VBASE + 0x00)
 176 #define IXP425_INT_ENABLE       (IXP425_IRQ_VBASE + 0x04)
 177 #define IXP425_INT_SELECT       (IXP425_IRQ_VBASE + 0x08)
 178 #define IXP425_IRQ_STATUS       (IXP425_IRQ_VBASE + 0x0C)
 179 #define IXP425_FIQ_STATUS       (IXP425_IRQ_VBASE + 0x10)
 180 #define IXP425_INT_PRTY         (IXP425_IRQ_VBASE + 0x14)
 181 #define IXP425_IRQ_ENC          (IXP425_IRQ_VBASE + 0x18)
 182 #define IXP425_FIQ_ENC          (IXP425_IRQ_VBASE + 0x1C)
 183
 184 #define IXP425_INT_SW1          31      /* SW Interrupt 1 */
 185 #define IXP425_INT_SW0          30      /* SW Interrupt 0 */
 186 #define IXP425_INT_GPIO_12      29      /* GPIO 12 */
 187 #define IXP425_INT_GPIO_11      28      /* GPIO 11 */
 188 #define IXP425_INT_GPIO_10      27      /* GPIO 11 */
 189 #define IXP425_INT_GPIO_9       26      /* GPIO 9 */
 190 #define IXP425_INT_GPIO_8       25      /* GPIO 8 */
 191 #define IXP425_INT_GPIO_7       24      /* GPIO 7 */
 192 #define IXP425_INT_GPIO_6       23      /* GPIO 6 */
 193 #define IXP425_INT_GPIO_5       22      /* GPIO 5 */
 194 #define IXP425_INT_GPIO_4       21      /* GPIO 4 */
 195 #define IXP425_INT_GPIO_3       20      /* GPIO 3 */
 196 #define IXP425_INT_GPIO_2       19      /* GPIO 2 */
 197 #define IXP425_INT_XSCALE_PMU   18      /* XScale PMU */
 198 #define IXP425_INT_AHB_PMU      17      /* AHB PMU */
 199 #define IXP425_INT_WDOG         16      /* Watchdog Timer */
 200 #define IXP425_INT_UART0        15      /* HighSpeed UART */
 201 #define IXP425_INT_STAMP        14      /* Timestamp Timer */
 202 #define IXP425_INT_UART1        13      /* Console UART */
 203 #define IXP425_INT_USB          12      /* USB */
 204 #define IXP425_INT_TMR1         11      /* General-Purpose Timer1 */
 205 #define IXP425_INT_PCIDMA2      10      /* PCI DMA Channel 2 */
 206 #define IXP425_INT_PCIDMA1       9      /* PCI DMA Channel 1 */
 207 #define IXP425_INT_PCIINT        8      /* PCI Interrupt */
 208 #define IXP425_INT_GPIO_1        7      /* GPIO 1 */
 209 #define IXP425_INT_GPIO_0        6      /* GPIO 0 */
 210 #define IXP425_INT_TMR0          5      /* General-Purpose Timer0 */
 211 #define IXP425_INT_QUE33_64      4      /* Queue Manager 33-64 */
 212 #define IXP425_INT_QUE1_32       3      /* Queue Manager  1-32 */
 213 #define IXP425_INT_NPE_C         2      /* Ethernet NPE C */
 214 #define IXP425_INT_NPE_B         1      /* Ethernet NPE B */
 215 #define IXP425_INT_NPE_A         0      /* NPE A */
 216
 217 /*
 218  * software interrupt
 219  */
 220 #define IXP425_INT_bit31        31
 221 #define IXP425_INT_bit30        30
 222 #define IXP425_INT_bit14        14
 223 #define IXP425_INT_bit11        11
 224
 225 #define IXP425_INT_HWMASK       (0xffffffff & \
 226                                         ~((1 << IXP425_INT_bit31) | \
 227                                           (1 << IXP425_INT_bit30) | \
 228                                           (1 << IXP425_INT_bit14) | \
 229                                           (1 << IXP425_INT_bit11)))
 230 #define IXP425_INT_GPIOMASK     (0x3ff800c0u)
 231
 232 /*
 233  * GPIO
 234  */
 235 #define IXP425_GPIO_HWBASE      IXP425_IO_HWBASE + IXP425_GPIO_OFFSET
 236 #define IXP425_GPIO_VBASE       IXP425_IO_VBASE  + IXP425_GPIO_OFFSET
 237                                         /* 0xf0004000 */
 238 #define IXP425_GPIO_SIZE        0x00000020UL
 239
 240 #define IXP425_GPIO_GPOUTR      0x00
 241 #define IXP425_GPIO_GPOER       0x04
 242 #define IXP425_GPIO_GPINR       0x08
 243 #define IXP425_GPIO_GPISR       0x0c
 244 #define IXP425_GPIO_GPIT1R      0x10
 245 #define IXP425_GPIO_GPIT2R      0x14
 246 #define IXP425_GPIO_GPCLKR      0x18
 247 # define GPCLKR_MUX14   (1U << 8)
 248 # define GPCLKR_CLK0TC_SHIFT    4
 249 # define GPCLKR_CLK0DC_SHIFT    0
 250
 251 /* GPIO Output */
 252 #define GPOUT_ON                0x1
 253 #define GPOUT_OFF               0x0
 254
 255 /* GPIO direction */
 256 #define GPOER_INPUT             0x1
 257 #define GPOER_OUTPUT            0x0
 258
 259 /* GPIO Type bits */
 260 #define GPIO_TYPE_ACT_HIGH      0x0
 261 #define GPIO_TYPE_ACT_LOW       0x1
 262 #define GPIO_TYPE_EDG_RISING    0x2
 263 #define GPIO_TYPE_EDG_FALLING   0x3
 264 #define GPIO_TYPE_TRANSITIONAL  0x4
 265 #define GPIO_TYPE_MASK          0x7
 266 #define GPIO_TYPE(b,v)          ((v) << (((b) & 0x7) * 3))
 267 #define GPIO_TYPE_REG(b)        (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R)
 268
 269 /*
 270  * Expansion Bus
 271  */
 272 #define IXP425_EXP_HWBASE       0xc4000000UL
 273 #define IXP425_EXP_VBASE        (IXP425_IO_VBASE + IXP425_IO_SIZE)
 274                                                 /* 0xf0010000 */
 275 #define IXP425_EXP_SIZE         IXP425_REG_SIZE /* 0x1000 */
 276
 277 /* offset */
 278 #define EXP_TIMING_CS0_OFFSET           0x0000
 279 #define EXP_TIMING_CS1_OFFSET           0x0004
 280 #define EXP_TIMING_CS2_OFFSET           0x0008
 281 #define EXP_TIMING_CS3_OFFSET           0x000c
 282 #define EXP_TIMING_CS4_OFFSET           0x0010
 283 #define EXP_TIMING_CS5_OFFSET           0x0014
 284 #define EXP_TIMING_CS6_OFFSET           0x0018
 285 #define EXP_TIMING_CS7_OFFSET           0x001c
 286 #define EXP_CNFG0_OFFSET                0x0020
 287 #define EXP_CNFG1_OFFSET                0x0024
 288 #define EXP_FCTRL_OFFSET                0x0028
 289
 290 #define IXP425_EXP_RECOVERY_SHIFT       16
 291 #define IXP425_EXP_HOLD_SHIFT           20
 292 #define IXP425_EXP_STROBE_SHIFT         22
 293 #define IXP425_EXP_SETUP_SHIFT          26
 294 #define IXP425_EXP_ADDR_SHIFT           28
 295 #define IXP425_EXP_CS_EN                (1U << 31)
 296
 297 #define IXP425_EXP_RECOVERY_T(x)        (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT)
 298 #define IXP425_EXP_HOLD_T(x)            (((x) & 3)  << IXP425_EXP_HOLD_SHIFT)
 299 #define IXP425_EXP_STROBE_T(x)          (((x) & 15) << IXP425_EXP_STROBE_SHIFT)
 300 #define IXP425_EXP_SETUP_T(x)           (((x) & 3)  << IXP425_EXP_SETUP_SHIFT)
 301 #define IXP425_EXP_ADDR_T(x)            (((x) & 3)  << IXP425_EXP_ADDR_SHIFT)
 302
 303 // EXP_CSn bits
 304 #define EXP_BYTE_EN                (1 << 0)
 305 #define EXP_WR_EN                  (1 << 1)
 306 #define EXP_SPLT_EN                (1 << 3)
 307 #define EXP_MUX_EN                 (1 << 4)
 308 #define EXP_HRDY_POL               (1 << 5)
 309 #define EXP_BYTE_RD16              (1 << 6)
 310 #define EXP_SZ_512                 (0 << 10)
 311 #define EXP_SZ_1K                  (1 << 10)
 312 #define EXP_SZ_2K                  (2 << 10)
 313 #define EXP_SZ_4K                  (3 << 10)
 314 #define EXP_SZ_8K                  (4 << 10)
 315 #define EXP_SZ_16K                 (5 << 10)
 316 #define EXP_SZ_32K                 (6 << 10)
 317 #define EXP_SZ_64K                 (7 << 10)
 318 #define EXP_SZ_128K                (8 << 10)
 319 #define EXP_SZ_256K                (9 << 10)
 320 #define EXP_SZ_512K                (10 << 10)
 321 #define EXP_SZ_1M                  (11 << 10)
 322 #define EXP_SZ_2M                  (12 << 10)
 323 #define EXP_SZ_4M                  (13 << 10)
 324 #define EXP_SZ_8M                  (14 << 10)
 325 #define EXP_SZ_16M                 (15 << 10)
 326 #define EXP_CYC_INTEL              (0 << 14)
 327 #define EXP_CYC_MOTO               (1 << 14)
 328 #define EXP_CYC_HPI                (2 << 14)
 329
 330 // EXP_CNFG0 bits
 331 #define EXP_CNFG0_8BIT             (1 << 0)
 332 #define EXP_CNFG0_PCI_HOST         (1 << 1)
 333 #define EXP_CNFG0_PCI_ARB          (1 << 2)
 334 #define EXP_CNFG0_PCI_66MHZ        (1 << 4)
 335 #define EXP_CNFG0_MEM_MAP          (1 << 31)
 336
 337 // EXP_CNFG1 bits
 338 #define EXP_CNFG1_SW_INT0          (1 << 0)
 339 #define EXP_CNFG1_SW_INT1          (1 << 1)
 340
 341 /*
 342  * PCI
 343  */
 344 #define IXP425_PCI_HWBASE       0xc0000000
 345 #define IXP425_PCI_VBASE        (IXP425_EXP_VBASE + IXP425_EXP_SIZE)
 346                                                         /* 0xf0011000 */
 347 #define IXP425_PCI_SIZE         IXP425_REG_SIZE         /* 0x1000 */
 348
 349 /*
 350  * Mapping registers of IXP425 PCI Configuration
 351  */
 352 /* PCI_ID_REG                   0x00 */
 353 /* PCI_COMMAND_STATUS_REG       0x04 */
 354 /* PCI_CLASS_REG                0x08 */
 355 /* PCI_BHLC_REG                 0x0c */
 356 #define PCI_MAPREG_BAR0         0x10    /* Base Address 0 */
 357 #define PCI_MAPREG_BAR1         0x14    /* Base Address 1 */
 358 #define PCI_MAPREG_BAR2         0x18    /* Base Address 2 */
 359 #define PCI_MAPREG_BAR3         0x1c    /* Base Address 3 */
 360 #define PCI_MAPREG_BAR4         0x20    /* Base Address 4 */
 361 #define PCI_MAPREG_BAR5         0x24    /* Base Address 5 */
 362 /* PCI_SUBSYS_ID_REG            0x2c */
 363 /* PCI_INTERRUPT_REG            0x3c */
 364 #define PCI_RTOTTO              0x40
 365
 366 /* PCI Controller CSR Base Address */
 367 #define IXP425_PCI_CSR_BASE     IXP425_PCI_VBASE
 368
 369 /* PCI Memory Space */
 370 #define IXP425_PCI_MEM_HWBASE   0x48000000UL
 371 #define IXP425_PCI_MEM_VBASE    0xf8000000UL
 372 #define IXP425_PCI_MEM_SIZE     0x04000000UL    /* 64MB */
 373
 374 /* PCI I/O Space */
 375 #define IXP425_PCI_IO_HWBASE    0x00000000UL
 376 #define IXP425_PCI_IO_SIZE      0x00100000UL    /* 1Mbyte */
 377
 378 /* PCI Controller Configuration Offset */
 379 #define PCI_NP_AD               0x00
 380 #define PCI_NP_CBE              0x04
 381 # define NP_CBE_SHIFT           4
 382 #define PCI_NP_WDATA            0x08
 383 #define PCI_NP_RDATA            0x0c
 384 #define PCI_CRP_AD_CBE          0x10
 385 #define PCI_CRP_AD_WDATA        0x14
 386 #define PCI_CRP_AD_RDATA        0x18
 387 #define PCI_CSR                 0x1c
 388 # define CSR_PRST               (1U << 16)
 389 # define CSR_IC                 (1U << 15)
 390 # define CSR_ABE                (1U << 4)
 391 # define CSR_PDS                (1U << 3)
 392 # define CSR_ADS                (1U << 2)
 393 # define CSR_HOST               (1U << 0)
 394 #define PCI_ISR                 0x20
 395 # define ISR_AHBE               (1U << 3)
 396 # define ISR_PPE                (1U << 2)
 397 # define ISR_PFE                (1U << 1)
 398 # define ISR_PSE                (1U << 0)
 399 #define PCI_INTEN               0x24
 400 #define PCI_DMACTRL             0x28
 401 #define PCI_AHBMEMBASE          0x2c
 402 #define PCI_AHBIOBASE           0x30
 403 #define PCI_PCIMEMBASE          0x34
 404 #define PCI_AHBDOORBELL         0x38
 405 #define PCI_PCIDOORBELL         0x3c
 406 #define PCI_ATPDMA0_AHBADDR     0x40
 407 #define PCI_ATPDMA0_PCIADDR     0x44
 408 #define PCI_ATPDMA0_LENGTH      0x48
 409 #define PCI_ATPDMA1_AHBADDR     0x4c
 410 #define PCI_ATPDMA1_PCIADDR     0x50
 411 #define PCI_ATPDMA1_LENGTH      0x54
 412 #define PCI_PTADMA0_AHBADDR     0x58
 413 #define PCI_PTADMA0_PCIADDR     0x5c
 414 #define PCI_PTADMA0_LENGTH      0x60
 415 #define PCI_PTADMA1_AHBADDR     0x64
 416 #define PCI_PTADMA1_PCIADDR     0x68
 417 #define PCI_PTADMA1_LENGTH      0x6c
 418
 419 /* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */
 420 #define COMMAND_NP_IA           0x0     /* Interrupt Acknowledge   (I)*/
 421 #define COMMAND_NP_SC           0x1     /* Special Cycle           (I)*/
 422 #define COMMAND_NP_IO_READ      0x2     /* I/O Read             (T)(I) */
 423 #define COMMAND_NP_IO_WRITE     0x3     /* I/O Write            (T)(I) */
 424 #define COMMAND_NP_MEM_READ     0x6     /* Memory Read          (T)(I) */
 425 #define COMMAND_NP_MEM_WRITE    0x7     /* Memory Write         (T)(I) */
 426 #define COMMAND_NP_CONF_READ    0xa     /* Configuration Read   (T)(I) */
 427 #define COMMAND_NP_CONF_WRITE   0xb     /* Configuration Write  (T)(I) */
 428
 429 /* PCI byte enables */
 430 #define BE_8BIT(a)              ((0x10u << ((a) & 0x03)) ^ 0xf0)
 431 #define BE_16BIT(a)             ((0x30u << ((a) & 0x02)) ^ 0xf0)
 432 #define BE_32BIT(a)             0x00
 433
 434 /* PCI byte selects */
 435 #define READ_8BIT(v,a)          ((u_int8_t)((v) >> (((a) & 3) * 8)))
 436 #define READ_16BIT(v,a)         ((u_int16_t)((v) >> (((a) & 2) * 8)))
 437 #define WRITE_8BIT(v,a)         (((u_int32_t)(v)) << (((a) & 3) * 8))
 438 #define WRITE_16BIT(v,a)        (((u_int32_t)(v)) << (((a) & 2) * 8))
 439
 440 /* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */
 441 #define COMMAND_CRP_READ        0x00
 442 #define COMMAND_CRP_WRITE       (1U << 16)
 443
 444 /*
 445  * SDRAM Configuration Register
 446  */
 447 #define IXP425_MCU_HWBASE       0xcc000000UL
 448 #define IXP425_MCU_VBASE        0xf0200000UL
 449 #define IXP425_MCU_SIZE         0x1000          /* Actually only 256 bytes */
 450 #define MCU_SDR_CONFIG          0x00
 451 #define  MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7)
 452 #define  MCU_SDR_CONFIG_64MBIT  (1u << 5)
 453 #define MCU_SDR_REFRESH         0x04
 454 #define MCU_SDR_IR              0x08
 455
 456 /*
 457  * Performance Monitoring Unit          (CP14)
 458  *
 459  *      CP14.0.1        Performance Monitor Control Register(PMNC)
 460  *      CP14.1.1        Clock Counter(CCNT)
 461  *      CP14.4.1        Interrupt Enable Register(INTEN)
 462  *      CP14.5.1        Overflow Flag Register(FLAG)
 463  *      CP14.8.1        Event Selection Register(EVTSEL)
 464  *      CP14.0.2        Performance Counter Register 0(PMN0)
 465  *      CP14.1.2        Performance Counter Register 0(PMN1)
 466  *      CP14.2.2        Performance Counter Register 0(PMN2)
 467  *      CP14.3.2        Performance Counter Register 0(PMN3)
 468  */
 469
 470 #define PMNC_E          0x00000001      /* enable all counters */
 471 #define PMNC_P          0x00000002      /* reset all PMNs to 0 */
 472 #define PMNC_C          0x00000004      /* clock counter reset */
 473 #define PMNC_D          0x00000008      /* clock counter / 64 */
 474
 475 #define INTEN_CC_IE     0x00000001      /* enable clock counter interrupt */
 476 #define INTEN_PMN0_IE   0x00000002      /* enable PMN0 interrupt */
 477 #define INTEN_PMN1_IE   0x00000004      /* enable PMN1 interrupt */
 478 #define INTEN_PMN2_IE   0x00000008      /* enable PMN2 interrupt */
 479 #define INTEN_PMN3_IE   0x00000010      /* enable PMN3 interrupt */
 480
 481 #define FLAG_CC_IF      0x00000001      /* clock counter overflow */
 482 #define FLAG_PMN0_IF    0x00000002      /* PMN0 overflow */
 483 #define FLAG_PMN1_IF    0x00000004      /* PMN1 overflow */
 484 #define FLAG_PMN2_IF    0x00000008      /* PMN2 overflow */
 485 #define FLAG_PMN3_IF    0x00000010      /* PMN3 overflow */
 486
 487 #define EVTSEL_EVCNT_MASK 0x0000000ff   /* event to count for PMNs */
 488 #define PMNC_EVCNT0_SHIFT 0
 489 #define PMNC_EVCNT1_SHIFT 8
 490 #define PMNC_EVCNT2_SHIFT 16
 491 #define PMNC_EVCNT3_SHIFT 24
 492
 493
 494 /*
 495  * Queue Manager
 496  */
 497 #define IXP425_QMGR_HWBASE      0x60000000UL
 498 #define IXP425_QMGR_VBASE       (IXP425_PCI_VBASE + IXP425_PCI_SIZE)
 499 #define IXP425_QMGR_SIZE        0x4000
 500
 501 /*
 502  * Network Processing Engines (NPE's) and associated Ethernet MAC's.
 503  */
 504 #define IXP425_NPE_A_HWBASE     (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET)
 505 #define IXP425_NPE_A_VBASE      (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET)
 506 #define IXP425_NPE_A_SIZE       0x1000          /* Actually only 256 bytes */
 507
 508 #define IXP425_NPE_B_HWBASE     (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET)
 509 #define IXP425_NPE_B_VBASE      (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET)
 510 #define IXP425_NPE_B_SIZE       0x1000          /* Actually only 256 bytes */
 511
 512 #define IXP425_NPE_C_HWBASE     (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET)
 513 #define IXP425_NPE_C_VBASE      (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET)
 514 #define IXP425_NPE_C_SIZE       0x1000          /* Actually only 256 bytes */
 515
 516 #define IXP425_MAC_A_HWBASE     (IXP425_IO_HWBASE + IXP425_MAC_A_OFFSET)
 517 #define IXP425_MAC_A_VBASE      (IXP425_IO_VBASE + IXP425_MAC_A_OFFSET)
 518 #define IXP425_MAC_A_SIZE       0x1000          /* Actually only 256 bytes */
 519
 520 #define IXP425_MAC_B_HWBASE     (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET)
 521 #define IXP425_MAC_B_VBASE      (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET)
 522 #define IXP425_MAC_B_SIZE       0x1000          /* Actually only 256 bytes */
 523
 524 #endif /* _IXP425REG_H_ */