sys/arch/arm/xscale/ixp425var.h

   1 /*      $NetBSD: ixp425var.h,v 1.11 2006/12/10 10:01:49 scw Exp $ */
   2
   3 /*
   4  * Copyright (c) 2003
   5  *      Ichiro FUKUHARA <ichiro@ichiro.org>.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
  21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  */
  29
  30 #ifndef _IXP425VAR_H_
  31 #define _IXP425VAR_H_
  32
  33 #include <sys/conf.h>
  34 #include <sys/device.h>
  35 #include <sys/queue.h>
  36
  37 #include <machine/bus.h>
  38
  39 #include <dev/pci/pcivar.h>
  40
  41 #define PCI_CSR_WRITE_4(sc, reg, data)  \
  42         bus_space_write_4(sc->sc_iot, sc->sc_pci_ioh,   \
  43                 reg, data)
  44
  45 #define PCI_CSR_READ_4(sc, reg) \
  46         bus_space_read_4(sc->sc_iot, sc->sc_pci_ioh, reg)
  47
  48 #define GPIO_CONF_WRITE_4(sc, reg, data)        \
  49         bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh,  \
  50                 reg, data)
  51
  52 #define GPIO_CONF_READ_4(sc, reg) \
  53         bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg)
  54
  55 #define EXP_BUS_WRITE_4(sc, reg, data)  \
  56         bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data)
  57
  58 #define EXP_BUS_READ_4(sc, reg) \
  59         bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg)
  60
  61 #define PCI_CONF_LOCK(s)        (s) = disable_interrupts(I32_bit)
  62 #define PCI_CONF_UNLOCK(s)      restore_interrupts((s))
  63
  64 struct ixp425_softc {
  65         struct device sc_dev;
  66         bus_space_tag_t sc_iot;
  67         bus_space_handle_t sc_ioh;              /* IRQ handle */
  68
  69         u_int32_t sc_intrmask;
  70
  71         /* Handles for the various subregions. */
  72         bus_space_handle_t sc_pci_ioh;          /* PCI mem handler */
  73         bus_space_handle_t sc_gpio_ioh;         /* GPIOs handler */
  74         bus_space_handle_t sc_exp_ioh;          /* Expansion bus handle */
  75
  76         /* Bus space, DMA, and PCI tags for the PCI bus */
  77         struct bus_space sc_pci_iot;
  78         struct bus_space sc_pci_memt;
  79         struct arm32_bus_dma_tag ia_pci_dmat;
  80         struct arm32_pci_chipset ia_pci_chipset;
  81         vaddr_t sc_pci_va;
  82
  83         /* DMA window info for PCI DMA. */
  84         struct arm32_dma_range ia_pci_dma_range;
  85
  86         /* GPIO configuration */
  87         u_int32_t sc_gpio_out;
  88         u_int32_t sc_gpio_oe;
  89         u_int32_t sc_gpio_intr1;
  90         u_int32_t sc_gpio_intr2;
  91 };
  92
  93 /*
  94  * There are roughly 32 interrupt sources.
  95  */
  96 #define NIRQ            32
  97
  98 struct intrhand {
  99         TAILQ_ENTRY(intrhand) ih_list;  /* link on intrq list */
 100         int (*ih_func)(void *);         /* interrupt handler */
 101         void *ih_arg;                   /* arg for handler */
 102         int ih_ipl;                     /* IPL_* */
 103         int ih_irq;                     /* IRQ number */
 104 };
 105
 106 #define IRQNAMESIZE     sizeof("ixp425 irq xx")
 107
 108 struct intrq {
 109         TAILQ_HEAD(, intrhand) iq_list; /* handler list */
 110         struct evcnt iq_ev;             /* event counter */
 111         u_int32_t iq_mask;              /* IRQs to mask while handling */
 112         u_int32_t iq_pci_mask;          /* PCI IRQs to mask while handling */
 113         u_int32_t iq_levels;            /* IPL_*'s this IRQ has */
 114         char iq_name[IRQNAMESIZE];      /* interrupt name */
 115         int iq_ist;                     /* share type */
 116 };
 117
 118 struct pmap_ent {
 119         const char*     msg;
 120         vaddr_t         va;
 121         paddr_t         pa;
 122         vsize_t         sz;
 123         int             prot;
 124         int             cache;
 125 };
 126
 127 extern struct ixp425_softc *ixp425_softc;
 128
 129 extern struct bus_space ixpsip_bs_tag;
 130 extern struct bus_space ixp425_bs_tag;
 131 extern struct bus_space ixp425_a4x_bs_tag;
 132
 133 void    ixp425_bs_init(bus_space_tag_t, void *);
 134 void    ixp425_md_pci_init(struct ixp425_softc *);
 135 void    ixp425_md_pci_conf_interrupt(pci_chipset_tag_t, int, int, int,
 136             int, int *);
 137 void    ixp425_pci_init(struct ixp425_softc *);
 138 void    ixp425_pci_dma_init(struct ixp425_softc *);
 139 void    ixp425_io_bs_init(bus_space_tag_t, void *);
 140 void    ixp425_mem_bs_init(bus_space_tag_t, void *);
 141
 142 void    ixp425_pci_conf_reg_write(struct ixp425_softc *, uint32_t, uint32_t);
 143 uint32_t ixp425_pci_conf_reg_read(struct ixp425_softc *, uint32_t);
 144
 145 void    ixp425_attach(struct ixp425_softc *);
 146 void    ixp425_icu_init(void);
 147 void    ixp425_clk_bootstrap(bus_space_tag_t);
 148 void    ixp425_intr_init(void);
 149 void    *ixp425_intr_establish(int, int, int (*)(void *), void *);
 150 void    ixp425_intr_disestablish(void *);
 151
 152 uint32_t ixp425_sdram_size(void);
 153
 154 #endif /* _IXP425VAR_H_ */