sys/arch/atari/dev/fdreg.h

   1 /*      $NetBSD: fdreg.h,v 1.2 1995/04/22 22:18:21 leo Exp $    */
   2
   3 /*
   4  * Copyright (c) 1995 Leo Weppelman.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef _FDREG_H
  29 #define _FDREG_H
  30 /*
  31  * Atari TT hardware:
  32  * Western Digital 1772 Floppy Disk Controller.
  33  */
  34
  35 /*
  36  * Accessing the FDC registers is indirect through ST-specific
  37  * DMA circuitry. See also dma.h.
  38  */
  39 #define FDC_CS  (DMA_FDC              ) /* command/status               */
  40 #define FDC_TR  (DMA_FDC|       DMA_A0) /* track register               */
  41 #define FDC_SR  (DMA_FDC|DMA_A1       ) /* sector register              */
  42 #define FDC_DR  (DMA_FDC|DMA_A1|DMA_A0) /* data register                */
  43
  44 /*
  45  * commands (relevant bits/fields indicated)
  46  */
  47 #define RESTORE 0x00            /* ( HVRR) seek to track 0              */
  48 #define SEEK    0x10            /* ( HVRR) seek to track                */
  49 #define STEP    0x20            /* (UHVRR) step in same direction       */
  50 #define STEPI   0x40            /* (UHVRR) step in                      */
  51 #define STEPO   0x60            /* (UHVRR) step out                     */
  52 #define F_READ  0x80            /* (MHE00) read sector                  */
  53 #define F_WRITE 0xA0            /* (MHEPA) write sector                 */
  54 #define READID  0xC0            /* ( HE00) read sector ID               */
  55 #define READTR  0xE0            /* ( HE00) read track                   */
  56 #define WRITETR 0xF0            /* ( HEP0) write track                  */
  57 #define IRUPT   0xD0            /* ( IIII) force interrupt              */
  58
  59 /*
  60  * other bits/fields in command register
  61  */
  62 #define RATE6   0x00            /* not 2, but  6 msec steprate          */
  63 #define RATE12  0x01            /* not 3, but 12 msec steprate          */
  64 #define RATE2   0x02            /* not 5, but  2 msec steprate          */
  65 #define RATE3   0x03            /* not 6, but  3 msec steprate          */
  66 #define VBIT    0x04            /* verify sector ID                     */
  67 #define HBIT    0x08            /* suppress motor on sequence           */
  68 #define UBIT    0x10            /* update track register                */
  69 #define EBIT    0x04            /* wait 30 msec to settle               */
  70 #define MBIT    0x10            /* multi-sector                         */
  71 #define PBIT    0x02            /* write precompensate                  */
  72 #define A0BIT   0x01            /* suppress (?) data address mark       */
  73 #define IINDEX  0x04            /* interrupt on each index pulse        */
  74 #define IFORCE  0x08            /* force interrupt                      */
  75
  76 /*
  77  * status register
  78  */
  79 #define BUSY    0x01            /* set if command under execution       */
  80 #define DRQ     0x02            /* Data Register status (pin c1)        */
  81 #define LD_T00  0x04            /* lost data; track 00                  */
  82 #define CRCERR  0x08            /* CRC error                            */
  83 #define RNF     0x10            /* Record Not Found                     */
  84 #define RT_SU   0x20            /* Record Type; Spin Up completed       */
  85 #define WRI_PRO 0x40            /* Write Protected                      */
  86 #define MOTORON 0x80            /* Motor On                             */
  87
  88 #endif /* _FDREG_H */