sys/arch/atari/dev/ncr5380reg.h

   1 /*      $NetBSD: ncr5380reg.h,v 1.20 2009/03/14 14:45:56 dsl Exp $      */
   2
   3 /*
   4  * Copyright (c) 1995 Leo Weppelman.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef _NCR5380REG_H
  29 #define _NCR5380REG_H
  30 /*
  31  * NCR5380 common interface definitions.
  32  */
  33
  34 /*
  35  * Register numbers: (first argument to GET/SET_5380_REG )
  36  */
  37 #define NCR5380_DATA    0               /* Data register                */
  38 #define NCR5380_ICOM    1               /* Initiator command register   */
  39 #define NCR5380_MODE    2               /* Mode register                */
  40 #define NCR5380_TCOM    3               /* Target command register      */
  41 #define NCR5380_IDSTAT  4               /* Bus status register          */
  42 #define NCR5380_DMSTAT  5               /* DMA status register          */
  43 #define NCR5380_TRCV    6               /* Target receive register      */
  44 #define NCR5380_IRCV    7               /* Initiator receive register   */
  45
  46 /*
  47  * Definitions for Initiator command register.
  48  */
  49 #define SC_A_RST        0x80    /* RW - Assert RST                      */
  50 #define SC_TEST         0x40    /* W  - Test mode                       */
  51 #define SC_AIP          0x40    /* R  - Arbitration in progress         */
  52 #define SC_LA           0x20    /* R  - Lost arbitration                */
  53 #define SC_A_ACK        0x10    /* RW - Assert ACK                      */
  54 #define SC_A_BSY        0x08    /* RW - Assert BSY                      */
  55 #define SC_A_SEL        0x04    /* RW - Assert SEL                      */
  56 #define SC_A_ATN        0x02    /* RW - Assert ATN                      */
  57 #define SC_ADTB         0x01    /* RW - Assert Data To Bus              */
  58
  59 /*
  60  * Definitions for mode register
  61  */
  62 #define SC_B_DMA        0x80    /* RW - Block mode DMA (not on TT!)     */
  63 #define SC_T_MODE       0x40    /* RW - Target mode                     */
  64 #define SC_E_PAR        0x20    /* RW - Enable parity check             */
  65 #define SC_E_PARI       0x10    /* RW - Enable parity interrupt         */
  66 #define SC_E_EOPI       0x08    /* RW - Enable End Of Process Interrupt */
  67 #define SC_MON_BSY      0x04    /* RW - Monitor BSY                     */
  68 #define SC_M_DMA        0x02    /* RW - Set DMA mode                    */
  69 #define SC_ARBIT        0x01    /* RW - Arbitrate                       */
  70
  71 /*
  72  * Definitions for tcom register
  73  */
  74 #define SC_LBS          0x80    /* RW - Last Byte Send (not on TT!)     */
  75 #define SC_A_REQ        0x08    /* RW - Assert REQ                      */
  76 #define SC_A_MSG        0x04    /* RW - Assert MSG                      */
  77 #define SC_A_CD         0x02    /* RW - Assert C/D                      */
  78 #define SC_A_IO         0x01    /* RW - Assert I/O                      */
  79
  80 /*
  81  * Definitions for idstat register
  82  */
  83 #define SC_S_RST        0x80    /* R  - RST is set                      */
  84 #define SC_S_BSY        0x40    /* R  - BSY is set                      */
  85 #define SC_S_REQ        0x20    /* R  - REQ is set                      */
  86 #define SC_S_MSG        0x10    /* R  - MSG is set                      */
  87 #define SC_S_CD         0x08    /* R  - C/D is set                      */
  88 #define SC_S_IO         0x04    /* R  - I/O is set                      */
  89 #define SC_S_SEL        0x02    /* R  - SEL is set                      */
  90 #define SC_S_PAR        0x01    /* R  - Parity bit                      */
  91
  92 /*
  93  * Definitions for dmastat register
  94  */
  95 #define SC_END_DMA      0x80    /* R  - End of DMA                      */
  96 #define SC_DMA_REQ      0x40    /* R  - DMA request                     */
  97 #define SC_PAR_ERR      0x20    /* R  - Parity error                    */
  98 #define SC_IRQ_SET      0x10    /* R  - IRQ is active                   */
  99 #define SC_PHS_MTCH     0x08    /* R  - Phase Match                     */
 100 #define SC_BSY_ERR      0x04    /* R  - Busy error                      */
 101 #define SC_ATN_STAT     0x02    /* R  - State of ATN line               */
 102 #define SC_ACK_STAT     0x01    /* R  - State of ACK line               */
 103 #define SC_S_SEND       0x00    /* W  - Start DMA output                */
 104
 105 #define SC_CLINT        {               /* Clear interrupts     */      \
 106                         int i = GET_5380_REG(NCR5380_IRCV);             \
 107                         }
 108
 109
 110 /*
 111  * Definition of SCSI-bus phases. The values are determined by signals
 112  * on the SCSI-bus. DO NOT CHANGE!
 113  * The values must be used to index the pointers in SCSI-PARMS.
 114  */
 115 #define NR_PHASE        8
 116 #define PH_DATAOUT      0
 117 #define PH_DATAIN       1
 118 #define PH_CMD          2
 119 #define PH_STATUS       3
 120 #define PH_RES1         4
 121 #define PH_RES2         5
 122 #define PH_MSGOUT       6
 123 #define PH_MSGIN        7
 124
 125 #define PH_OUT(phase)   (!(phase & 1))  /* TRUE if output phase         */
 126 #define PH_IN(phase)    (phase & 1)     /* TRUE if input phase          */
 127
 128 /*
 129  * Id of Host-adapter
 130  */
 131 #define SC_HOST_ID      0x80
 132
 133 /*
 134  * Base setting for 5380 mode register
 135  */
 136 #define IMODE_BASE      SC_E_PAR
 137
 138 /*
 139  * SCSI completion status codes, should move to sys/scsi/????
 140  */
 141 #define SCSMASK         0x1e    /* status code mask                     */
 142 #define SCSGOOD         0x00    /* good status                          */
 143 #define SCSCHKC         0x02    /* check condition                      */
 144 #define SCSBUSY         0x08    /* busy status                          */
 145 #define SCSCMET         0x04    /* condition met / good                 */
 146
 147 /*
 148  * Return values of check_intr()
 149  */
 150 #define INTR_SPURIOUS   0
 151 #define INTR_RESEL      2
 152 #define INTR_DMA        3
 153
 154 struct  ncr_softc {
 155         struct  device          sc_dev;
 156         struct  scsipi_channel  sc_channel;
 157         struct  scsipi_adapter  sc_adapter;
 158
 159         /*
 160          * Some (pre-SCSI2) devices don't support select with ATN.
 161          * If the device responds to select with ATN by going into
 162          * command phase (ignoring ATN), then we flag it in the
 163          * following bitmask.
 164          * We also keep track of which devices have been selected
 165          * before.  This allows us to not even try raising ATN if
 166          * the target doesn't respond to it the first time.
 167          */
 168         u_int8_t        sc_noselatn;
 169         u_int8_t        sc_selected;
 170 };
 171
 172 /*
 173  * Max. number of DMA-chains per request
 174  */
 175 #define MAXDMAIO        (MAXPHYS/PAGE_SIZE + 1)
 176
 177 /*
 178  * Some requests are not contiguous in physical memory. We need to break them
 179  * up into contiguous parts for DMA.
 180  */
 181 struct dma_chain {
 182         u_int   dm_count;
 183         u_long  dm_addr;
 184 };
 185
 186 /*
 187  * Define our issue, free and disconnect queue's.
 188  */
 189 typedef struct  req_q {
 190     struct req_q        *next;      /* next in free, issue or discon queue  */
 191     struct req_q        *link;      /* next linked command to execute       */
 192     struct scsipi_xfer  *xs;        /* request from high-level driver       */
 193     u_short             dr_flag;    /* driver state                         */
 194     u_char              phase;      /* current SCSI phase                   */
 195     u_char              msgout;     /* message to send when requested       */
 196     u_char              targ_id;    /* target for command                   */
 197     u_char              targ_lun;   /* lun for command                      */
 198     u_char              status;     /* returned status byte                 */
 199     u_char              message;    /* returned message byte                */
 200     u_char              *bounceb;   /* allocated bounce buffer              */
 201     u_char              *bouncerp;  /* bounce read-pointer                  */
 202     struct dma_chain    dm_chain[MAXDMAIO];
 203     struct dma_chain    *dm_cur;    /* current DMA-request                  */
 204     struct dma_chain    *dm_last;   /* last DMA-request                     */
 205     long                xdata_len;  /* length of transfer                   */
 206     u_char              *xdata_ptr; /* virtual address of transfer          */
 207     struct scsipi_generic xcmd;     /* command to execute                   */
 208     int                 xcmd_len;   /* command length                       */
 209 } SC_REQ;
 210
 211 /*
 212  * Values for dr_flag:
 213  */
 214 #define DRIVER_IN_DMA   0x01    /* Non-polled DMA activated             */
 215 #define DRIVER_AUTOSEN  0x02    /* Doing automatic sense                */
 216 #define DRIVER_NOINT    0x04    /* We are booting: no interrupts        */
 217 #define DRIVER_DMAOK    0x08    /* DMA can be used on this request      */
 218 #define DRIVER_BOUNCING 0x10    /* Using the bounce buffer              */
 219 #define DRIVER_LINKCHK  0x20    /* Doing the linked command check       */
 220
 221 static SC_REQ   *issue_q   = NULL;      /* Commands waiting to be issued*/
 222 static SC_REQ   *discon_q  = NULL;      /* Commands disconnected        */
 223 static SC_REQ   *connected = NULL;      /* Command currently connected  */
 224
 225 /*
 226  * Function decls:
 227  */
 228 static void ack_message(void);
 229 static int  check_autosense(SC_REQ *, int);
 230 static int  check_intr(struct ncr_softc *);
 231 static int  dma_ready(void);
 232 static void finish_req(SC_REQ *);
 233 static int  handle_message(SC_REQ *, u_int);
 234 static int  information_transfer(struct ncr_softc *);
 235 static void nack_message(SC_REQ *, u_char);
 236 static void ncr_aprint(struct ncr_softc *, const char *, ...);
 237 static void ncr_ctrl_intr(struct ncr_softc *);
 238 static void ncr_dma_intr(struct ncr_softc *);
 239 static void ncr_tprint(SC_REQ *, const char *, ...);
 240 static int  reach_msg_out(struct ncr_softc *, u_long);
 241 static void reselect(struct ncr_softc *);
 242 static void run_main(struct ncr_softc *);
 243 static int  scsi_dmaok(SC_REQ *);
 244 static void scsi_main(struct ncr_softc *);
 245 static void scsi_reset_verbose(struct ncr_softc *, const char *);
 246 static int  scsi_select(SC_REQ *, int);
 247 static void show_data_sense(struct scsipi_xfer *);
 248 static void show_phase(SC_REQ *, int);
 249 static void show_request(SC_REQ *, const char *);
 250 static void show_signals(u_char, u_char);
 251 static void transfer_dma(SC_REQ *, u_int, int);
 252 static int  transfer_pio(u_char *, u_char *, u_long *, int);
 253 static int  wait_req_false(void);
 254 static int  wait_req_true(void);
 255
 256         /*
 257          * You might want to call these from the debugger...
 258          */
 259        void scsi_show(void);
 260        void scsi_reset(void);
 261
 262 #endif /* _NCR5380REG_H */