1 /* $NetBSD: dma.h,v 1.10 2009/03/05 13:00:45 tsutsui Exp $ */
4 * Copyright (c) 1995 Leo Weppelman.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #ifndef _MACHINE_DMA_H
29 #define _MACHINE_DMA_H
33 * FDC/ACSI DMA circuitry
36 #define DMA ((struct dma *)AD_DMA)
39 volatile short dma_gap
[2]; /* reserved */
40 volatile u_short dma_data
; /* controller data path */
41 volatile u_short dma_mode
; /* mode register */
42 volatile u_char dma_addr
[6]; /* base address H/M/L */
43 volatile u_short dma_drvmode
; /* floppy density settings */
46 #define dma_nsec dma_data /* sector count */
47 #define dma_stat dma_mode /* status register */
52 /* 0x0001 *//* not used */
53 #define DMA_A0 0x0002 /* signal A0 to fdc/hdc */
54 #define DMA_A1 0x0004 /* signal A1 to fdc/hdc */
55 #define DMA_HDC 0x0008 /* must be on if accessing hdc */
56 #define DMA_SCREG 0x0010 /* access sector count register */
57 /* 0x0020 *//* reserved */
58 #define DMA_NODMA 0x0040 /* no DMA (yet) */
59 #define DMA_FDC 0x0080 /* must be on if accessing fdc */
60 #define DMA_WRBIT 0x0100 /* write to fdc/hdc via dma_data*/
61 #define DMA_SCSI 0x0088 /* select 5380 chip */
64 * Status register bits
66 #define DMAOK 0x0001 /* something wrong */
67 #define SCNOT0 0x0002 /* sector count not 0 */
68 #define DATREQ 0x0004 /* FDC data request signal */
71 * Indices into dma_addr.
72 * Access low byte of 16 bits.
73 * Fill low/mid/high in this order.
80 * Defines for 'dmadrv_mode'.
82 #define FDC_HDSET 1 /* Set FDC for High density */
83 #define FDC_HDSIG 2 /* Signal HD present to drive */
88 #define DMA_LOCK_REQ 1 /* DMA lock requested */
89 #define DMA_LOCK_GRANT 2 /* DMA lock granted */
92 typedef void (*dma_farg
)(void*);
94 int st_dmagrab(dma_farg
, dma_farg
, void *, int *, int);
95 void st_dmafree(void *, int *);
96 int st_dmawanted(void);
97 void st_dmaaddr_set(void *);
98 u_long
st_dmaaddr_get(void);
99 void st_dmacomm(int, int);
102 #endif /* _MACHINE_DMA_H */