sys/arch/evbarm/dev/plcomreg.h

   1 /*      $NetBSD: comreg.h,v 1.11 1997/10/19 14:26:21 fvdl Exp $ */
   2
   3 /*-
   4  * Copyright (c) 2001 ARM Ltd
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The name of the company may not be used to endorse or promote
  16  *    products derived from this software without specific prior written
  17  *    permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  20  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30 */
  31
  32
  33 #define PLCOM_FREQ      1843200 /* 16-bit baud rate divisor */
  34 #define PLCOM_TOLERANCE 30      /* baud rate tolerance, in 0.1% units */
  35
  36 /* control register */
  37 #define CR_LBE          0x80    /* Loopback enable */
  38 #define CR_RTIE         0x40    /* Receive timeout interrupt enable */
  39 #define CR_TIE          0x20    /* Transmit interrupt enable */
  40 #define CR_RIE          0x10    /* Receive interrrupt enable */
  41 #define CR_MSIE         0x08    /* Modem status interrupt enable */
  42 #define CR_SIRLP        0x04    /* IrDA SIR Low power mode */
  43 #define CR_SIREN        0x02    /* SIR Enable */
  44 #define CR_UARTEN       0x01    /* Uart enable */
  45
  46 /* interrupt identification register */
  47 #define IIR_IMASK       0x0f
  48 #define IIR_RTIS        0x08
  49 #define IIR_TIS         0x04
  50 #define IIR_RIS         0x02
  51 #define IIR_MIS         0x01
  52
  53 /* line control register */
  54 #define LCR_WLEN        0x60    /* Mask of size bits */
  55 #define LCR_8BITS       0x60    /* 8 bits per serial word */
  56 #define LCR_7BITS       0x40    /* 7 bits */
  57 #define LCR_6BITS       0x20    /* 6 bits */
  58 #define LCR_5BITS       0x00    /* 5 bits */
  59 #define LCR_FEN         0x10    /* FIFO enable */
  60 #define LCR_STP2        0x08    /* 2 stop bits per serial word */
  61 #define LCR_EPS         0x04    /* Even parity select */
  62 #define LCR_PEN         0x02    /* Parity enable */
  63 #define LCR_PEVEN       (LCR_PEN | LCR_EPS)
  64 #define LCR_PODD        LCR_PEN
  65 #define LCR_PNONE       0x00    /* No parity */
  66 #define LCR_BRK         0x01    /* Break Control */
  67
  68 /* modem control register */
  69 #define MCR_RTS         0x02    /* Request To Send */
  70 #define MCR_DTR         0x01    /* Data Terminal Ready */
  71
  72 /* receive status register */
  73
  74 #define RSR_OE          0x08    /* Overrun Error */
  75 #define RSR_BE          0x04    /* Break */
  76 #define RSR_PE          0x02    /* Parity Error */
  77 #define RSR_FE          0x01    /* Framing Error */
  78
  79 /* flag register */
  80 #define FR_TXFE         0x80    /* Transmit fifo empty */
  81 #define FR_RXFF         0x40    /* Recive fifo full */
  82 #define FR_TXFF         0x20    /* Transmit fifo full */
  83 #define FR_RXFE         0x10    /* Receive fifo empty */
  84 #define FR_BUSY         0x08    /* Uart Busy */
  85 #define FR_DCD          0x04    /* Data carrier detect */
  86 #define FR_DSR          0x02    /* Data set ready */
  87 #define FR_CTS          0x01    /* Clear to send */
  88
  89 /* modem status register */
  90 /* All deltas are from the last read of the MSR. */
  91 #define MSR_DCD         FR_DCD
  92 #define MSR_DSR         FR_DSR
  93 #define MSR_CTS         FR_CTS
  94
  95 /* Register offsets */
  96 #define plcom_dr        0x00
  97 #define plcom_rsr       0x04
  98 #define plcom_ecr       0x04
  99 #define plcom_lcr       0x08
 100 #define plcom_dlbh      0x0c
 101 #define plcom_dlbl      0x10
 102 #define plcom_cr        0x14
 103 #define plcom_fr        0x18
 104 #define plcom_iir       0x1c
 105 #define plcom_icr       0x1c
 106 #define plcom_ilpr      0x20
 107
 108 /* IFPGA specific */
 109 #define PLCOM_UART_SIZE 0x24